Design of reconfigurable access wrappers for embedded core based SoC test

Testing of embedded core based system-on-chip (SoC) ICs is a well known problem, and the upcoming IEEE P1500 Standard on Embedded Core Test (SECT) standard proposes DFT solutions to alleviate it. One of the proposals is to provide every core in the SoC with test access wrappers. Previous approaches to the problem of wrapper design have proposed static core wrappers, which are designed for a fixed test access mechanism (TAM) width. We present the first report of a design of reconfigurable core wrappers which allow for a dynamic change in the width of the TAM executing the core test. Analysis of the corresponding scheduling problem indicates that good approximate schedules can be achieved without significant computational effort. Specifically, we derive a O(N/sub C//sup 2/B) time algorithm which can compute near optimal SoC test schedules, where N/sub C/ is the number of cores and B is the number of top level TAMs. Experimental results on benchmark SoCs are presented which improve upon integer programming based methods, not only in the quality of the schedule, but also significantly reduce the computation time.     

Test response reuse-based SoC core test compression and test scheduling for test application time minimization

This paper presents a novel approach to system-on-a-chip (SoC) core test compression and test scheduling. Every test set is compressed through the test responses of its preceding core in preprocessing step by simulation. Consequently, under our method the test sets contain two parts: (1) the test sets that are compatible with the test responses of their individual preceding cores. This part can be removed from their original test sets, and (2) the test sets that none of the test vectors from them are compatible with the test responses of their individual preceding cores. On hardware implementation, only a couple of 2-1 MUXs are needed. The algorithms for reordering the sequences of core-under-tests and those of the test vectors for each corresponding core are outlined for optimal test compression results. It needs neither coder nor decoder, thus saving hardware overhead. Power-constrained SoC core test pipelining consumes less test application time. Hierarchical clustering-based SoC test scheduling can be implemented easily, and the hardware overhead is negligible. Experimental results on benchmark ISCAS 89 demonstrate that our method achieves significant improvement of test time and less ATE requirement over the previous methods, and it does not discount the fault coverage of each test set, moreover, the fault coverage for some test sets is improved instead.     

一种可重构阵列结构及其任务调度算法

提出了一种可以利用计算时间覆盖配置时间和数据传输时间的可重构阵列结构,并且针对该可重构阵列结构提出了一种表调度算法进行任务调度.在SOCDesigner平台上进行了软硬件协同仿真,对于IDCT,FFT,4×4矩阵乘法新可重构阵列相比原来的可重构阵列有平均约10%的速度提升.     

Defect-oriented test scheduling

As tester complexity and cost increase, reducing test time is an important manufacturing priority. Test time can be reduced by ordering tests so as to fail defective units early in the test process. Algorithms to order tests that guarantee optimality require execution time that is exponential in the number of tests applied. We develop a simple polynomial-time heuristic to order tests. The heuristic, based on criteria that offer local optimality, offers globally optimal solutions in many cases. An ordering algorithm requires information on the ability of tests to detect defective units. One way to obtain this information is by simulation. We obtain it by applying all possible tests to a small subset of manufactured units and assuming the information obtained from this subset is representative. The ordering heuristic was applied to manufactured digital and analog integrated circuits (ICs) tested with commercial testers. When both approaches work, the orders generated by the heuristic are optimal. More importantly, the heuristic is able to generate an improved order for large problem sizes when the optimal algorithm is not able to do so. The new test orders result in a significant reduction, as high as a factor of four, in the time needed to identify defective units. We also assess the validity of using such sampling techniques to order tests     

A framework for reconfigurable computing: task scheduling andcontext management

Dynamically reconfigurable architectures are emerging as a viable design alternative to implement a wide range of computationally intensive applications. At the same time, an urgent necessity has arisen for support tool development to automate the design process and achieve optimal exploitation of the architectural features of the system. Task scheduling and context (configuration) management become very critical issues in achieving the high performance that digital signal processing (DSP) and multimedia applications demand. This article proposes a strategy to automate the design process which considers all possible optimizations that can be carried out at compilation time, regarding context and data transfers. This strategy is general in nature and could be applied to different reconfigurable systems. We also discuss the key aspects of the scheduling problem in a reconfigurable architecture such as MorphoSys. In particular, we focus on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations     

面向分布式业务的可重构光网络资源调度机制研究

针对在光网络中为分布式并发业务提供定制服务的问题,提出了一种负载均衡的多源多路并行调度策略,将网络负载和应用负载均衡分担在不同的资源节点.通过仿真验证,与普通的单源单路最短路策略和多源多路最短路并行传输策略相比,该策略能够有效地降低分布式业务的阻塞率.以分布式服务GridFTP在可重构光网络实验床上的应用为例,通过实验验证了该策略的可行性和有效性.实验结果表明,综合考虑应用资源和网络资源的负载均衡,可以有效降低分布式业务在网格系统中的处理时间,提高系统性能.     

Integrity-based self-validation test scheduling

Intelligent sensors use functional self-testing to confirm measurement validity; this introduces the potential for false diagnosis and unnecessary corrective intervention. For a sensor in an integrity-monitoring context, it is desirable to select a test-interval to minimize the probability of faulty operation between discrete tests. The scheduling of discrete test intervals is examined as an optimization problem under a reliability-based cost-function. A convenient test-interval guideline, accounting for the operating context of the sensor, is derived for a simple case under limiting assumptions.     

A framework for reconfigurable computing: task scheduling and context management-a summary

Reconfigurable computing is consolidating itself as a real alternative to ASICs (Application Specific Integrated Circuits) and general-purpose processors. The main advantage of reconfigurable computing derives from its unique combination of broad applicability, provided by the reconfiguration capability, and achievable performance, through the potential parallelism exploitation. The key aspects of the scheduling problem in a reconfigurable architecture are discussed, focusing on a task scheduling methodology for DSP and multimedia applications, as well as the context management and scheduling optimizations.     

基于Crossbar的可重构网络输入排队分域调度研究

为解决传统网络技术体系中交换结构无法满足大量差异化业务规模化应用的问题,本文基于可重构网络技术体系,采用选择关闭部分Crossbar交叉节点的分域模型,提出了分域调度的思想,分析并推导了承载组内的SDRR调度算法和域内最长队列优先调度算法。最后采用交换性能仿真平台对该调度算法进行了复杂度和时延的仿真比较,结果表明:分域调度的最长队列优先算法比一般最长队列优先算法相对复杂度低,且随着调度域个数增加,相对复杂度降低。在相同业务源输入条件下,Crossbar三分域调度算法的时延小于非分域调度算法的时延,接近公平输出排队调度算法的时延。     

Multiobjective scheduling for IC sort and test with a simulationtestbed

In manufacturing environments such as an integrated circuit (IC) sort and test floor, typically more than one objective, such as cycle time and on-time delivery, needs to be simultaneously considered. With multiple objectives, a good solution is called Pareto optimal if it is not inferior to any other feasible solutions in terms of all objectives. The Pareto boundary is the set of all Pareto optimal solutions, which indicates the tradeoff of all good solutions. In this paper, a multiobjective model for IC sort and test is formulated, based upon the current information at any given instant. An approximate Pareto boundary can then be found using the Lagrangian relaxation method for the model. New algorithms are used to solve the dual problem and obtain feasible solutions from the associated subproblem solutions. The impact of the new scheduling approach on performance is illustrated through numerical examples by comparing it with corresponding single-objective problems and various heuristic dispatching rules. Its performance in dynamic and stochastic environments for real world applications is evaluated by using a simulation testbed. Simulation results definitely indicate a high potential for our approach     

Potential analysis of a superscalar core employing a reconfigurable array for improving instruction-level parallelism

As technology scaling reduces pace and energy efficiency becomes a new important design constraint, superscalar processor designs are reaching their performance limits due to area and power restrictions. As a result, new microarchitectural paradigms need to be developed. This work proposes a new organization for x86 processors, based on a traditional superscalar design coupled to a reconfigurable array. The system exploits the fact that few basic blocks are responsible for most of the instructions that execute in the processor, and transforms these basic blocks into configurations for the reconfigurable array. Each configuration encodes the semantics and dependencies for all instructions in the block, so that the ones already mapped can execute bypassing the fetch, decode and dependency checks stages and improving instruction throughput. Our study on the potential of the architecture shows that performance gains of up to 2.5\(\times \) with respect to a traditional superscalar can be achieved.     

用于DiffServ的核心无状态的虚拟时钟调度算法

提出了一种同时满足对资源进行分配要求和具有良好的可扩展性要求的包调度算法。通过一个基于虚拟时钟的 FIFO 队列来达到公平队列中多个队列的效果,即在不同的流间实现资源的公平分配;同时,由于在核心路由器维持的是一个 FIFO 队列,因此无需进行每流状态的管理和对收到的数据包执行按流分类的工作,这样较之公平队列算法大大地降低了在核心路由器的系统开销,从而满足可扩展性的要求。     

一种光交换核心节点调度算法研究

光交换核心节点是光交换网络的核心设备,其性能的优劣直接影响网络的吞吐量、时延等重要指标。文章提出一种SWC-MSD(基于波长变换器的多播空分交换)模块的严格无阻塞光交换核心节点,在此基础上提出了三种调度算法,通过数学分析和实验仿真验证了算法的正确性。考察了这种核心节点在有无波长变换以及业务优先级不同的场景下阻塞率的变化情况,结果表明所提出的严格无阻塞光交换核心节点具有较低的阻塞率。     

多波段可重构雷达接收自动测试系统的设计与实现

多波段可重构雷达是目前较为先进的雷达系统,其接收机的传统人工测试弊端很多,由于多波段的指标很多,各个功能的实现指标都需要测试,如果人工逐一测试,需要花费的时间和费用非常巨大,这样将导致雷达的开发成本非常高。在研究多波段可重构雷达接收机结构系统的基础上,提出设计了自动测试系统,该系统主要由硬件和软件两大部分组成,多波段可重构雷达接收机的测试系统实现自动化、可视化,系统测试数据图形化,该系统具有成本低、操作简单、使用方便、测试效率高、测试精度高等优点,在其他系统的自动测试设计上也具有借鉴意义。     

Production scheduling algorithms for a semiconductor test facility

The authors develop production scheduling algorithms for semiconductor test operations. The operations in the facility under study are characterized by a broad product mix, variable lot sizes and yields, long and variable setup times, and limited test equipment capacity. The approach presented starts by dividing the facility or job shop into a number of work centers. The method then proceeds to sequence one work center at a time. A disjunctive graph representation of the entire facility is used to capture interactions between work centers. The introduction of different management objectives leads to different work center problems and different production scheduling algorithms. The authors present algorithms for two different work center problems. Direction for future research are discussed     

Enhancing electronic systems with reconfigurable hardware

This article describes how current applications - communications and mobile systems - have employed FPGAs because they are more flexible than ASICs yet with higher speed and lower power consumption than CPUs. This has happened in spite of the fact that we require HDL experts to program them. New applications that can benefit from variable-grain parallelism are hot prospects to emerge as killer applications in the near future, especially as improvements in data movement are made. Enabling these new killer applications can only be accomplished by increasing designer productivity. Graphical tools that provide reusable components and means of expressing parallelism hold great promise in achieving these goals.     

Embedded core test generation using broadcast test architecture and netlist scrambling

In this work, based on the concept of test pattern broadcasting, we propose a new core-based testing method which gives core users the maximum level of test freedom. Instead of only using the test patterns delivered by core providers, core users are allowed to broadcast their own test patterns to the cores of a SoC (system on chip) design for parallel scan testing. The fault coverage of each core test, using test patterns developed by any core user, can be evaluated by an enhanced version of a traditional fault simulator. The netlist of each core is scrambled before it is delivered to core users, thus the netlist will not be revealed. The enhanced fault simulator of a core has the capabilities of decoding the scrambled netlist, and performing fault simulation for the test patterns provided by each of the core users. For each core, both random test patterns (applied by a core user), and golden test patterns (delivered by the core provider) jointly achieve high and flexible fault coverage requirements. The enhanced logic simulator of each core can also decrypt the scrambled netlist, and perform logic simulation with the objective of generating fault-free test responses for signature analysis (for example). The proposed method has the advantages of minimizing the number of scan pins, reducing the test application time, and achieving the maximum level of test quality control by core users. Simulation results demonstrate the feasibility of this method.     

Simple reconfigurable antenna with radiation pattern

A radiation pattern reconfigurable antenna is proposed. By controlling the switch states, the antenna can be worked as a monopole antenna with an omnidirectional radiation pattern or a dipole antenna with reflector, which has directional radiation pattern. Detailed design considerations of the proposed antenna, simulated and experimental results are presented and discussed.     

Thermal-aware test scheduling using network-on-chip under multiple clock rates

The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an optimal integer linear programming (ILP) formulation and a simulated annealing (SA) solution to thermal and power-aware test scheduling of cores in an NoC-based SoC using multiple clock rates. The methods have been implemented and results on various benchmarks are presented.