CCD多晶硅层间复合绝缘介质研究

电荷耦合器件(CCD)多晶硅交叠区域绝缘介质对成品率和器件可靠性具有重要的影响。将氮化硅和二氧化硅作为CCD多晶硅层间复合绝缘介质,采用扫描电子显微镜(SEM)和电学测试系统研究了多晶硅层间氮化硅和二氧化硅复合绝缘介质对CCD多晶硅栅间距和多晶硅层间击穿电压的影响。研究结果表明,多晶硅层间复合绝缘介质中的氮化硅填充了多晶硅热氧化层的微小空隙,可以明显改善绝缘介质质量。多晶硅层间击穿电压随着氮化硅厚度的增加而增大,但太厚的氮化硅会导致CCD暗电流明显增大。由于复合绝缘介质质量好,可以减小CCD多晶硅的氧化厚度。     

CCD多晶硅层间绝缘介质对器件可靠性的影响

采用扫描电子显微镜和电学分析技术研究了电荷耦合器件(CCD)多晶硅层间绝缘介质对器件可靠性的影响.研究结果表明,常规热氧化工艺制作的多晶硅介质层,在台阶侧壁存在薄弱区,多晶硅层间击穿电压仅20 V,器件在可靠性试验后容易因多晶硅层间击穿而失效.采用LPCVD淀积二氧化硅技术消除了多晶硅台阶侧壁氧化层薄弱区,其层间击穿电压大于129 V,明显改善了器件可靠性.     

用镶嵌工艺制作金属/高k晶体管

东芝公司的研究人员认为,２ｍｍ以下的薄栅介质是开发高性能晶体管的最佳材料。这意味着栅材料从现在采用的重掺杂多晶硅栅和ＳｉＯ２栅氧化层向金属栅和高ｋ栅介质材料发展。 金属栅与多晶硅栅相比,其优点是不受栅耗尽效应的影响。高ｋ介质的优点是介质材料具有较高的介质常数（ｋ值）以及较低的隧道电流密度。同时,由于它们具有较大的电容,所以在相似的电特性下,能淀积的膜层厚度比二氧化硅膜厚。高ｋ材料包括Ｔａ氧化层、Ｔｉ氧化层、Ｚｒ氧化层以及Ｈｆ氧化层。 促使开发镶嵌栅工艺的一个因素是用反应离子刻蚀薄栅氧化层图形太难,…     

HDP介质淀积引起的等离子充电损伤机制研究

高密度等离子体化学气相淀积(HDP CVD),具有卓越的填孔能力和可靠的电学特性等诸多优点,因此它被广泛应用于超大规模集成电路制造工艺中.本文研究了金属层间介质(IMD)的HDP CVD过程对栅氧化膜的等离子充电损伤.研究表明在HDP淀积结束时的光电导效应使得IMD层(包括FSG和USG)在较短的时间内处于导电状态,较大电流由IMD层流经栅氧化膜,在栅氧化膜中产生缺陷,从而降低了栅氧化膜可靠性.通过对HDP CVD结束后反应腔内气体组分的调节,IMD层的光电导现象得到了一定程度的抑制,等离子充电损伤得到了改善.     

高k HfO2栅介质淀积后退火工艺研究

研究了淀积后退火(PDA)工艺(包括退火环境和退火温度)对高介电常数(k)HfO2栅介质MOS电容(MOSCAP)电学特性的影响.通过对比O2和N2环境中,不同退火温度下的HfO2栅介质MOSCAP的C-V曲线发现,高kHfO2栅介质在N2环境中退火时具有更大的工艺窗口.通过对HfO2栅介质MOSCAP的等效氧化层厚度(dEOT)、平带电压(Vfb)和栅极泄漏电流(Ig)等参数进一步分析发现,与O2环境相比,高kHfO2栅介质在N2环境中PDA处理时dEOT和Ig更小、Vfb相差不大,更适合纳米器件的进一步微缩.HfO2栅介质PDA处理的最佳工艺条件是在N2环境中600℃下进行.该优化条件下高kHfO2栅介质MOSCAP的dEOT=0.75 nm,Vnb=0.37 V,Ig=0.27 A/cm2,满足14或16 nm技术节点对HfO2栅介质的要求.     

LOCOS(局域硅氧化工艺)一种用于静电电机的微加工工艺

本文给出了一种利用局域硅氧化工艺生产静电微米规模电机的新型工艺.这种电机的草图如(1)图所示,它基于五道掩膜工艺,简述如下,具有连续腐蚀到衬底的氮化硅层的淀积和光刻,硅的选择性氧化LOCOS,用于转子电刷的部分选择性氧化物的腐蚀,多晶硅的淀     

TDDB击穿特性评估薄介质层质量

与时间相关电介质击穿(TDDB)测量是评估厚度小于20nm薄栅介质层质量的重要方法.氧化层击穿前,隧穿电子和空穴在氧化层中或界面附近产生陷阱、界面态,当陷阱密度超过临界平均值 _bd时,发生击穿.击穿电量Q_bd值表征了介质层的质量.Q_bd值及其失效统计分布与测试电流密度、电场强度、温度及氧化层面积等有定量关系.TDDB的早期失效分布可以反映工艺引入的缺陷.TDDB可以直接评估氧化、氮化、清洗、刻蚀等工艺对厚度小于10nm的栅介质质量的影响.它是硅片级评估可靠性和预测EEPROM擦写次数的重要方法.     

氮注入多晶硅栅对超薄SiO2栅介质性能的影响

p+多晶硅栅中的硼在SiO2栅介质中的扩散会引起栅介质可靠性退化,在多晶硅栅内注入N+的工艺可抑制硼扩散.制备出栅介质厚度为4.6nm的p+栅MOS电容,通过SIMS测试分析和I-V、C-V特性及电应力下击穿特性的测试,观察了多晶硅栅中注N+工艺对栅介质性能的影响.实验结果表明:在多晶硅栅中注入氮可以有效抑制硼扩散,降低了低场漏电和平带电压的漂移,改善了栅介质的击穿性能,但同时使多晶硅耗尽效应增强、方块电阻增大,需要折衷优化设计.     

氮注入多晶硅栅对超薄SiO_2栅介质性能的影响

p+ 多晶硅栅中的硼在 Si O2 栅介质中的扩散会引起栅介质可靠性退化 ,在多晶硅栅内注入 N+ 的工艺可抑制硼扩散 .制备出栅介质厚度为 4 .6 nm的 p+栅 MOS电容 ,通过 SIMS测试分析和 I- V、C- V特性及电应力下击穿特性的测试 ,观察了多晶硅栅中注 N+工艺对栅介质性能的影响 .实验结果表明 :在多晶硅栅中注入氮可以有效抑制硼扩散 ,降低了低场漏电和平带电压的漂移 ,改善了栅介质的击穿性能 ,但同时使多晶硅耗尽效应增强、方块电阻增大 ,需要折衷优化设计 .     

LPCVD多晶硅形貌对氧化层击穿特性的影响

多晶硅表面对于电荷耦合器件(CCD)的制作非常重要。采用扫描电子显微镜(SEM)和电学分析技术研究了低压化学气相(LPCVD)法淀积的多晶硅形貌对击穿特性的影响。研究结果表明,减小多晶硅表面颗粒尺寸有助于改善多晶硅氧化层击穿特性。多晶硅氧化层击穿特性与多晶硅和绝缘层交界面的平滑度有关。多晶硅薄膜表面平整度变差,则多晶硅与氧化层之间的界面平滑性变差,多晶硅介质层击穿强度降低。     

Investigation of the Process of Plasma Through Etching of HkMG Stack of Nanotransistor with a 32-nm Critical Dimension

The processes of plasma etching of stack layers to form a structure of a metal gate of a nanoscale transistor with a dielectric with a high level of dielectric permittivity (HkMG) are investigated. A resist mask formed by fine-resolution electron-beam lithography is used in the etching. The plasma etching of the stack’s layers is carried out in one technological etching cycle without a vacuum break. The sequential anisotropic etching process of the stack of polysilicon, tantalum nitride, and hafnium nitride, as well as the etching process of the gate insulator based on hafnium oxide with a high degree of selectivity in relation to the underlying crystalline silicon, which guarantees the complete removal of the layer of hafnium oxide and the minimal loss of the silicon layer (not more than 0.5 nm), is investigated.     

优化了栅电极溅射工艺的难熔金属栅MOS电容的性能

论述了通过优化难熔金属栅电极的溅射工艺及采用适当的退火温度修复损伤来提高3nm栅氧W/TiN叠层栅MOS电容的性能.实验选取了合适的TiN厚度来减小应力,以较小的TiN溅射率避免溅射过程对栅介质的损伤,并采用了较高的N2/Ar比率在TiN溅射过程中进一步氮化了栅介质.实验得到了高质量的C-V曲线,并成功地把Nss(表面态密度)降低到了8×1010/cm2以下,达到了与多晶硅栅MOS电容相当的水平.     

一种提高栅氧化物介电常数的方法

从90 nm技术节点开始,等离子氮化SiON栅氧化层被广泛用作先进的CMOS器件制造。作为传统SiO2栅氧化层的替代材料,SiON栅氧化层因其具有较高的介电常数而能有效地抑制硼等栅极掺杂原子在栅氧化层中的扩散。氮化后热退火处理(Post Nitridation Anneal,PNA)是制备等离子氮化SiON栅氧化层的一个重要步骤,主要用于修复晶格损伤并形成稳定Si-N键,同时在氧化氛围下通过界面的二次氧化反应来修复SiO2/Si界面的损伤。本文通过对传统栅氧制备工艺中PNA单一高温退火工艺的温度、气体氛围进行优化,提供了一种通过提高栅氧化物的氮含量来提其高介电常数的方法。实验数据表明,与传统的制备方法相比,采用本方法所制备的SiON栅氧化层中氮含量可以提高30%以上,栅氧界面态总电荷可减少一个数量级,PMOS器件的NBTI寿命t0.1%和t50%可分别提高15.3%和32.4%。     

高性能亚100nm栅长氮氧叠层栅介质难熔W/TiN金属栅电极CMOS器件

在国内首次将等效氧化层厚度为1.7nm的N/O叠层栅介质技术与W/TiN金属栅电极技术结合起来,用于栅长为亚100nm的金属栅CMOS器件的制备.为抑制短沟道效应并提高器件驱动能力,采用的关键技术主要包括:1.7nm N/O叠层栅介质,非CMP平坦化技术,T型难熔W/TiN金属叠层栅电极,新型重离子超陡倒掺杂沟道剖面技术以及双侧墙技术.成功地制备了具有良好的短沟道效应抑制能力和驱动能力的栅长为95nm的金属栅CMOS器件.在VDS=±1.5V,VGS=±1.8V下,nMOS和pMOS的饱和驱动电流分别为679和-327μA/μm.nMOS的亚阈值斜率,DIBL因子以及阈值电压分别为84.46mV/dec,34.76mV/V和0.26V.pMOS的亚阈值斜率,DIBL因子以及阈值电压分别为107.4mV/dec,54.46mV/V和0.27V.结果表明,这种结合技术可以完全消除B穿透现象和多晶硅耗尽效应,有效地降低栅隧穿漏电并提高器件可靠性.     

Atomic Layer Deposition in the Production of a Gate HkMG Stack Structure with a Minimum Topological Size of 32 nm

The plasma-enhanced atomic layer deposition (PEALD) of a High-K Dielectric and Metal Gate (HkMG) stack for MIS transistors, including the subgate HfO₂ (2–4 nm) dielectric layer, the ultrathin metallic stabilizing hafnium nitride HfN (1–3 nm) layer, and the basic metallic gate layer from tantalum nitride ТаN (10–20 nm), on silicon plates with a diameter of 200 mm is studied. The spectral ellipsometry method is applied to measure the homogeneity of the deposited film thickness. The dielectric constant of the dielectric in the stack, the leak current, and the breakdown voltage are examined. The four-probe method is used to study the specific electric resistance of tantalum nitride deposited by the atomic layer deposition ALD method. The film thickness homogeneity as a function of the ALD process parameters is examined. The specific resistance of the metallic TaN layer as a function of the composition and parameters of the plasma discharge are studied.     

Submicrometer Silicon MOSFET's fabricated using focused ion-beam lithography

Submicrometer n-channel enhancement-mode silicon MOSFET's with polysilicon gate lengths as small as 0.35 µm were fabricated using focused-ion-beam lithography. The polysilicon gate was patterned by a 80-kV Au-Si ion beam using a negative polystyrene resist. Transconductance values of 140 mS/mm were obtained for devices with gatelengths of 0.4 µm and gate oxide thickness of 10 nm. Short-channel effects were minimal in these devices.     

Physical and electrical characterization of polysilicon vs. TiN gate electrodes for HfO2 transistors

The effects of pre-deposition substrate treatments and gate electrode materials on the properties and performance of high-k gate dielectric transistors were investigated. The performance of O₃ vs. HF-last/NH₃ pre-deposition treatments followed by either polysilicon (poly-Si) or TiN gate electrodes was systematically studied in devices consisting of HfO₂ gate dielectric produced by atomic layer deposition (ALD). High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) using X-ray spectra and Electron Energy Loss Spectra (EELS) were used to produce elemental profiles of nitrogen, oxygen, silicon, titanium, and hafnium to provide interfacial chemical information and to convey their changes in concentration across these high-k transistor gate-stacks of 1.0–1.8 nm equivalent oxide thickness (EOT). For the TiN electrode case, EELS spectra illustrate interfacial elemental overlap on a scale comparable to the HfO₂ microroughness. For the poly-Si electrode, an amorphous reaction region exists at the HfO₂/poly-Si interface. Using fast transient single pulse (SP) electrical measurements, electron trapping was found to be greater with poly-Si electrode devices, as compared to TiN. This may be rationalized as a result of a higher density of trap centers induced by the high-k/poly-Si material interactions and may be related to increased physical thickness of the dielectric film, as illustrated by HAADF-STEM images, and may also derive from the approximately 0.5 nm larger EOT associated with polysilicon electrodes on otherwise identical gate stacks.     

High Transconductance MISFET With a Single InAs Nanowire Channel

Metal-insulator field-effect transistors (FETs) are fabricated using a single n-InAs nanowire (NW) with a diameter of d = 50 nm as a channel and a silicon nitride gate dielectric. The gate length and dielectric scaling behavior is experimentally studied by means of dc output- and transfer-characteristics and is modeled using the long-channel MOSFET equations. The device properties are studied for an insulating layer thickness of 20-90 nm, while the gate length is varied from 1 to 5 mum. The InAs NW FETs exhibit an excellent saturation behavior and best breakdown voltage values of V _BR > 3 V. The channel current divided by diameter d of an NW reaches 3 A/mm. A maximum normalized transconductance g_m /d > 2 S/mm at room temperature is routinely measured for devices with a gate length of les 2 mum and a gate dielectric layer thickness of les 30 nm.