Design for Test of Asynchronous NULL Convention Logic (NCL) Circuits

Due to the absence of a global clock and the presence of more state holding elements that synchronize the control and data paths, conventional Automatic Test Pattern Generation (ATPG) algorithms fail when applied to asynchronous circuits, leading to poor fault coverage. This paper presents a design for test (DFT) technique for a popular asynchronous design paradigm called NULL Convention Logic (NCL) aimed at making NCL designs testable using existing DFT tools with reasonable gate overhead. The proposed technique performs test points (TPs) insertion using Sandia Controllability and Observability Program (SCOAP) analysis to enhance the controllability of feedback nets and observability for fault sites that are flagged unobservable. An Automatic DFT Insertion Flow (ADIF) algorithm and a custom ATPG NCL primitive gates library are developed. The developed DFT technique has been verified on several NCL benchmark circuits

Design and characterization of NULL convention arithmetic logic units

In this paper, a number of 4-bit, 8-operation arithmetic logic units (ALUs) are designed using the delay-insensitive NULL convention logic paradigm, and are characterized in terms of speed and area. Both dual-rail and quad-rail, pipelined and non-pipelined versions are developed, and the tradeoffs and design considerations for each are discussed. Comparing the various architectures shows that the fastest dual-rail and quad-rail ALUs achieve average speedups of 1.72 and 1.59, respectively, over their non-pipelined counterparts, while requiring 133% and 119% more area, respectively. Overall, the dual-rail designs are both faster and require less area than their respective quad-rail counterparts; however, the quad-rail versions are expected to consume less power.     

Designing robust threshold gates against soft errors

In applications where issues like power efficiency, high performance, and more noise tolerance are important, asynchronous design methodology can play a significant role. However, as a result of technology shrinkage, combinational asynchronous circuits have become vulnerable in presence of particle strikes. In this paper, we design robust quasi-delay insensitive (QDI) asynchronous circuits against soft errors. Null Convention Logic (NCL) gates used as one of the basic techniques in asynchronous circuits, are redesigned to increase their robustness against Single Event Upset (SEU). We analyze our design for various NCL structures and compare them with another design in Kuang et al. (2007) [4], and show that our proposed approach is more robust against SEU. The effect of some parameters such as power consumption, delay, and the influence of transistor sizing on soft error tolerance are discussed.     

基于并行完备检测的高速异步流水线设计

为了有效地提升异步零协议逻辑(NCL)流水线的吞吐量,该文提出一种多阈值并行完备流水线。采用独特的半静态零协议阈值门建立异步组合逻辑,使数据串行传输的同时每级流水线数据处理和完备检测并行进行,以串并结合的工作方式提升吞吐量。同时新阈值门的使用降低了流水线空周期时的静态功耗。基于SMIC 0.18μm标准CMOS工艺对所提出的流水线进行了分析测试。与现有流水线比较显示,当组合逻辑为四位串行进位全加器时,新的流水线吞吐量提升62.8%,静态功耗减少40.5%,可用于高速低功耗的异步电路设计。     

FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm

This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow retiming can break the critical path of the design into finer pieces to improve the throughput of the design. The complexity of the C-slow retiming on FPGA is to find the best register allocation in the data path of the design so that by increasing the number of registers, relocation of the registers to balance the AES architecture be in the best mode, and the critical path be optimally pipelined and improved. In this paper, architecture of the AES algorithm is implemented in the gate level by high-speed and breakable structures that are desirable for the 2-slow retiming. The Mix-columns transformation is implemented based on multiplication by constants 2 and 3 modules with combinational logic circuits. This work has been successfully verified and synthesized using Xilinx ISE 11 byVirtex-5, XC5VLX85 FPGA. The proposed implementation achieves a high throughput of 86 Gb/s and high maximum operation frequency of 671.524 MHz whereas the highest throughput and the highest operation frequency reported in the literature are 73.737 Gb/s and 576.07 MHz, respectively.     

Asynchronous 2‐Phase Protocol Based on Ternary Encoding for On‐Chip Interconnect

Level‐encoded dual‐rail (LEDR) has been widely used in on‐chip asynchronous interconnects supporting a 2‐phase handshake protocol. However, it inevitably requires 2N wires for N‐bit data transfers. Encoder and decoder circuits that perform an asynchronous 2‐phase handshake protocol with only N wires for N‐bit data transfers are presented for on‐chip global interconnects. Their fundamentals are based on a ternary encoding scheme using current‐mode multiple valued logics. Using 0.25 μm CMOS technologies, the maximum reduction ratio of the proposed circuits, compared with LEDR in terms of power‐delay product, was measured as 39.5% at a wire length of 10 mm and data rate of 100 MHz.     

异步零协议算术逻辑单元的设计

异步电路在低功耗、低噪声、抗干扰、无时钟偏移、高鲁棒性和模块化设计等方面有较高的性能.设计了一个异步4位8操作码的算术逻辑单元,使用了双轨延时不敏感零协议逻辑结构,同时比较了使用流水线结构和非流水线结构以及相关的面积和速度优势.结果显示平均速度最快的结构比非流水线结构快了1.73倍,而面积需要增加了133%.     

A single-channel 8-bit 660 MS/s asynchronous SAR ADC with pre-settling procedure in 65 nm CMOS

A single-channel 8-bit low-power high-speed SAR ADC with a novel pre-settling procedure is presented in this paper. The proposed procedure relaxes the settling time significantly and improves the speed of the ADC. Moreover, the asynchronous technique avoids the high frequency internal clocks and further increases the speed of the SAR ADC. Based on SMIC 65 nm 1.2-V CMOS technology, the simulation results demonstrate that DNL and INL are −0.4/0.4 LSBs and −0.9/0.8 LSBs, respectively. At 660 MS/s sampling rate, the ADC consumes 7.6 mW from a 1.2 V supply. The proposed SAR ADC?s SNDR and SFDR are 49.5 dB and 64.2 dB, respectively.     

CMOS负阻单元逻辑电路及其发展前景

在回顾了多值逻辑(MVL)电路的优点、分析了共振隧穿器件(RTD)电路的特点和比较了各种类型负阻器件性能的基础上,提出了利用CMOS型负阻单元作为基础性器件设计并实现CMOS型逻辑电路的新概念,并指出了此研究领域的几个重点研究内容和方向。     

Graph-based STA for asynchronous controllers

We present a Graph-based Asynchronous Static Timing Analysis (ASTA) methodology for Asynchronous Control Circuits, which pessimistically computes Critical Cycle(s), instead of Critical Paths, without cycle cutting. Its additional requirement over STA is a graph-based Event Model, Marked Graph or Petri Net. We contrast STA, ASTA results for 23 asynchronous circuit benchmarks, and demonstrate significant timing differences between the ASTA critical cycle and STA critical path, with cut cycles. We also demonstrate our correlation to SPICE level simulations, for 20 of the 23 circuits. Our ASTA flow effectively upper bounds critical cycle delay over SPICE, and is orders of magnitude faster.     

MOSFET-like CNFET based logic gate library for low-power application: a comparative study

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

Computational analysis and comparison of reversible gates for design and test of logic circuits

Quantum computing is one of the most significant anticipation towards the accomplishment of interminable consumer demands of small, high speed, and low-power operable electronics devices. As reversible logic circuits have direct applicability to quantum circuits, design and synthesis of these circuits are finding grounds for emerging nano-technologies of quantum computing. Multiple Controlled Toffoli (MCT) and Multiple Controlled Fredkin (MCF) are the fundamental reversible gates that playing key role in this phase of development. A number of special reversible gates have also been presented so far, which were claimed superior for providing certain purposes like logic development and testing. This paper critically analyses a range of these gates to procure an optimal solution for design, synthesis and testing of reversible circuits. The experimentation is facilitated at three subsequent levels, i.e. gates properties, quantum cost and design & testability. MCT and MCF gates are found up to 50% more cost-effective than special gates at design level and 34.4% at testability level. Maximum reversibility depth (MRD) is included as a new measurement parameter for comparison. Special gates exhibit MRD up to 7 which ideally should be 1 for a system to be physically reversible as that of MCT and MCF gates.     

低功耗三值双边沿触发器设计

提出了几种分别采用两个锁存器和单个锁存器的三值双边沿触发器设计方案，这些方案包括动态、半静态和静态结构。双锁存器三值双边沿触发器是通过将两个透明的三值闩锁并列构成的。单个锁存器的三值双边沿触发器设计是通过时钟信号的上升沿及下降沿后分别产生的窄脉冲使锁存器瞬时导通完成取样求值。三值双边沿触发器具有对时钟信号的两个跳变均敏感的特点，因此可以抑制时钟信号的冗余跳变。较之三值单边沿触发器，在保持相同数据吞吐量的条件下，采用三值双边沿触发器可使时钟信号的频率减半，从而降低系统功耗。最后给出了采用0．25μm CMOS工艺参数的HSPICE模拟结果及其功耗比较。     

Ultra-low power 32-bit pipelined adder using subthreshold source-coupled logic with 5 fJ/stage PDP

This article presents a new approach for improving the power-delay performance of subthreshold source-couple logic (STSCL) circuits. Using a simple two-phase pipelining technique, it is possible to increase the activity rate of STSCL gates with negligible additional cost, and hence reduce the total system energy consumption per operation. In the proposed pipelined topology, each STSCL gate is followed by a simple cross-coupled differential pair operating as a state keeper with a very low power consumption and small area overhead. Measurement results on a 32-bit pipelined adder chain fabricated with CMOS technology show that the proposed approach can achieve a significant reduction in power-delay product (PDP) down to 5 fJ/stage.     

基于布尔可满足性的逻辑电路等价性验证方法

提出了基于布尔可满足性(Boolean Satisfiability,SAT)的逻辑电路等价性验证方法。这一验证方法把每个电路抽象成一个有穷自动机(FSM),为两个待验证的电路构造积机,把等价性验证问题转换成了积机的断言判定问题。改进了Tseitin变换方法,并将其用于把电路约束问题变换成(Conjunctive Normal Form,CNF)公式。之后则用先进的CNF SAT求解器zChaff判定积机所生成的布尔公式的可满足性。事例电路验证说明了该方法的有效性。     

A new low-power 10T SRAM cell with improved read SNM

This paper describes the characteristics of a new 10T structure for SRAM cell that works quite well in the sub-threshold region. This new architecture has good characteristics in write and read delay and energy compared with other new structures. This new 10T topology improves read static noise margin (SNM) and write operation speed with respect to other topologies in the same or even lower power consumption. The new topology has at least 13% lower power consumption compared with the best of recent architectures. Its write characteristics also are similar to those of 6T-SRAM, which has improved write delay and energy. The new 10T SRAM cell also consumes lower power compared with other cells. The stacking is used to suppress the standby leakage through the read path. The simulations were performed using HSPICE 2011 in a 16 nm bulk CMOS Berkeley predictive technology model (BPTM).     

Cell design methodology (CDM) for balanced Carry–InverseCarry circuits in hybrid-CMOS logic style

In this paper, we propose a systematic design methodology in the category of hybrid-CMOS logic style. A huge library of circuits appropriate for low-power and high-speed applications can be obtained by employing the proposed design methodology. The methodology is before used for designing XOR/XNOR and demonstrates the excellence of the new design features. The question of whether the method can be taken advantage to design the function of Carry and its complement (Carry and InverseCarry), as the third important module of a full adder, and what to extend the answer contributes to move towards the general systematic design. All the presented designs as before have high driving capability, balanced full-swing outputs with less glitches and small number of transistors. Also these only consist of one pass-transistor in the critical path, which causes low propagation delay and high drivability. As known, hybrid-CMOS full adders can be divided into three modules, e.g., SUM, Carry and XOR. Optimising these modules has reduced power consumption, delay and the number of transistors of full adders. Therefore by embedding the balanced full-swing circuits in carry module, it can be expected that 11 new full adder circuits will possess high performance. Simulation results show that the proposed circuits exhibit better performances compared to previously suggested circuits in the proposed realistic test bench. These circuits, outperform their counterparts, are showing 24–126% improvement in the power-delay product (PDP) and 57–82% improvement in the area. All simulations have been performed with TSMC 0.13-μm technology in new full adder test bench, using HSPISE to achieve the minimum PDP.     

由pnp双极型晶体管和PMOS构成的CMOS负阻单元

使用pnp双极型晶体管和pMOS,按照正反馈产生负阻I-V特性的原理,采用CMOS工艺,设计研制成功CMOS负阻单元,并对它进行了实际的测试与验证,效果良好,而且可以用它作为基础性器件,构成与CMOS工艺相兼容的负阻型逻辑电路,比常规CMOS电路节省大量器件。     

MODELING OF THE PRIORITY SCHEDULING INPUT—LINE GROUP OUTPUT WITH MULTI-CHANNEL IN ATM EXCHANGE SYSTEM

In this paper, an extended Kendall model for the priority scheduling input-line group output with multi-channel in Asynchronous Transfer Mode （ATM） exchange system is proposed and then the mean method is used to model mathematically the non-typical non-anticipative PRiority service （PR） model. Compared with the typical and non-anticipative PR model, it expresses the characteristics of the priority scheduling input-line group output with multi-channel in ATM exchange system. The simulation experiment shows that this model can improve the HOL block and the performance of input-queued ATM switch network dramatically. This model has a better developing prospect in ATM exchange system.     

ATM的技术优势

介绍了ATM与IP的结合技术,ATM与SDH、FR技术的优缺点,以及ATM与各兆以太网的竞争,并对发展趋势作了预测。