改进的RF-LDMOS小信号模型参数提取方法

准确地提取RF-LDMOS小信号模型参数对LDMOS大信号模型建模十分重要,而且好的小信号模型能很好地反映微波器件的性能。针对LDMOS提出了一种改进的小信号模型参数提取方法,此方法增加了测试结构的建模和参数提取,极大地方便了S参数曲线的拟合,而且对于测试版图的研究有一定的指导意义。由此方法提取的小信号模型与实验测试数据在0.1～8 GHz拟合的很好,并且准确地预测了器件的特征频率。该模型和方法能够很好的适用于LDMOS的L,S波段小信号建模和参数提取。     

一种基于神经网络的微波器件快速建模方法北大核心CSCD

随着微波器件结构复杂度的增长和产品性能要求的提高,微波器件建模不仅要能够描述其理想电磁特性,还要能快速准确反映多物理参数对器件性能的影响。虽然神经网络已经被引入到微波器件领域,但是将其应用于器件的多物理特性建模的研究还比较少。文章提出了一种基于人工神经网络的多物理参数建模方法来表示输入输出变量之间的非线性关系。提出了一种高效的神经网络多物理参数模型,并针对该模型引入了一种新的训练算法。所提出的模型可以快速准确地预测微波器件的多物理响应,如滤波器的S参数特性曲线、离子敏感场效应晶体管的输出特性曲线等。与有限元方法相比,此方法可以节省约98%的计算成本与99%的计算时间,为实现快速高效的微波器件行为级建模提供一种可行方法。     

高压LDMOS晶体管宏模型及栅电荷建模方法

针对标准MOSFET的BSIM4模型在高压LDMOS建模及已有LDMOS紧凑模型的不足,提出一种LDMOS宏模型。在本研究中,借助Spectre软件分别对宏模型与BSIM4器件模型进行仿真,并对2种LDMOS器件模型下的CV结果进行对比,验证了宏模型对LDMOS器件模拟的准确性。最后,提出利用栅电荷曲线来进一步修正模型参数的新方法,并通过仿真获得更精确的LDMOS器件模型。该宏模型及栅电荷建模方法对于高压功率集成电路设计及仿真有重要意义。     

基于模糊逻辑的射频功放建模

提出了一种基于模糊逻辑的射频功放行为模型的建模方法.利用了模糊逻辑的万能逼近能力,对射频功放电路外部端口动态特性进行了准确的建模,并将模型计算得到的稳态输出电压,功率压缩特性和增益压缩特性曲线与ADS软件仿真结果进行了比较,取得了较好的效果,证明建模方法的有效性.     

一种基于BSIM-CMG的FinFET变容管模型

提出了一种适用于FinFET变容管的建模方法.在BSIM-CMG的基础上,模型采用衬底模型和外围寄生模型来表征变容管的射频寄生效应.提出了具体的参数提取方法,将测试的S参数导入到安捷伦IC-CAP建模软件提取参数,测试结构引入高频寄生采用(open+ short)去嵌方法进行去嵌.通过调节模型参数拟合测试曲线得到FinFET变容管模型.该模型可精确表述FinFET变容管全工作区域特性,解决传统MOS变容管模型无法准确描述三维FinFET器件变容特性的问题.模型和模型参数提取方法采用20个硅鳍、16个栅指、158 nm栅长、578 nm栅宽的FinFET变容管进行建模验证,模型仿真和测试所得C-V,R-V和S参数特性吻合良好.     

一种CMOS混合信号电路衬底噪声耦合模型

利用二维器件模拟器MEDICI提取出重掺杂外延型衬底的电阻宏简化模型,所需的6个参数均可通过器件模拟得到,能够精确表征混合信号集成电路中的衬底噪声特性。基于0.25μm CMOS工艺所建立的电阻宏模型,设计了简单的混合信号电路进行应用验证,证明了该模型能够有效表征混合信号集成电路的衬底噪声。     

高鲁棒性N型沟道RF-LDMOS在TLP应力下的电学机理研究

提高射频功率器件的鲁棒性有利于增强器件的抗静电放电能力和抗失配能力.为了直观地了解器件内部发生的电学过程，本文研究了高鲁棒性N型沟道RF-LDMOS（Radio Frequency Lateral Diffusion MOS）在TLP（Transmission Line Pulse）应力下的电学机理.利用0.18μm BCD（Bipolar/CMOS/DMOS）先进制程，实现了特定尺寸器件的设计与流片.通过实测与仿真的对比，发现静电放电失效的随机性、芯片内部的热效应是导致仿真和实测差异的非理想因素.通过对TLP仿真的各阶段重要节点的分析，证明了源极下方的P型埋层有利于提高空穴电流的泄放能力，从而提高RF-LDMOS的鲁棒性.     

面向电力射频识别芯片的SPICE模型定制化开发

为了满足电力射频识别(RFID)芯片在-50～125℃的工作温区及高灵敏度的应用需求,定制化开发了芯片宽温区范围内高精度的MOSFET器件SPICE模型,该模型在RFID芯片关键模块中进行了验证。对器件尺寸设计、版图设计、电学性能测试、模型参数提取以及验证环节都进行了定制化开发。在器件模型参数提取环节采用了分块建模以及宏模型的建模方式同时提高了大尺寸和小尺寸器件的温度仿真精度。该模型在宽温度范围内阈值电压仿真与实测值差达到了10 mV以下,饱和电流精度在5%以下。环形振荡器的电路仿真精度相比通用模型提升了近50%,带隙基准源电路仿真精度提升了20 mV。     

基于射频功放非线性建模的欺骗干扰识别

针对欺骗干扰信号在时域、频域、空域与真实信号重叠,导致识别欺骗干扰的难度较大,假定真实发射机与欺骗干扰机射频前端器件除功放模块外均工作于理想状态,提出了一种基于射频功放建模的欺骗干扰识别方法。首先,利用Hammerstein模型对射频功放进行非线性建模,以模型参数作为提取的特征向量;其次,基于统计检测理论识别欺骗干扰;最后通过实验验证了方法的有效性,并与基于信号双谱特征的识别方法进行性能对比。实验结果表明,基于射频功放建模的欺骗干扰识别方法能够有效地识别欺骗干扰,且优于基于信号双谱特征的识别方法。     

基于PSO_SVM的射频功率放大器模型研究

针对神经网络和支持向量机在射频功率放大器建模领域存在的优缺点,提出一种利用PSO_SVM算法对射频功率放大器进行建模的方法.从理论上分析了支持向量机(SVM)及粒子群优化(PSO)算法的相关原理,并将PSO_SVM算法应用到功放器件建模中.仿真结果表明,基于PSO_SVM的射频功放模型在模型精度、小样本学习和逼近能力方面均优于传统SVM模型和BP神经网络(BPNN)模型.     

Modeling and characterization of an 80 V silicon LDMOSFET foremerging RFIC applications

This paper describes the design and optimization of an 80 V silicon RF LDMOSFET used in a power amplifier for base station applications. The transistor was prototyped using the doping profiles extracted from an experimental device and extensive two-dimensional (2-D) simulations were performed to characterize the DC and RF performance of the device. A good match between the measured and simulated data is reported. A simple circuit model was developed which accurately predicts the DC and RF characteristics in circuit simulators. It is shown through 2-D simulations that the LDD region in the LDMOSFET can be modeled as a JFET. A methodology for the accurate extraction of model parameters for the circuit model is discussed. It is shown that the DC and RF performances of the circuit model closely match the measured data. Advanced mixed device and circuit simulations were used to obtain S-parameters of the device which provide new insights into device physics and also the basis for statistical process control studies     

Characterization and modeling of hot carrier injection in LDMOS for L-band radar application

This paper reports a methodology to correlate Hot Carrier Injection (HCI) degradation mechanism and electrical figures of merit on Lateral-Diffused Metal-Oxide-Semiconductor (LDMOS) transistor. This method is based on RF life test in radar operating conditions coupled to a high drain voltage in order to make visible HCI degradation. We propose drain current modeling vs. time based on a simple extraction procedure. The electron density trapped in the oxide is extracted from hot carrier induced series resistance enhancement model (HISREM - i.e. ΔR_d model). From this methodology, the degradation of RF-LDMOS due to HCI is quantified and could be simulated with EDA.     

MOSFET modeling for RF IC design

High-frequency (HF) modeling of MOSFETs for radio-frequency (RF) integrated circuit (IC) design is discussed. Modeling of the intrinsic device and the extrinsic components is discussed by accounting for important physical effects at both dc and HF. The concepts of equivalent circuits representing both intrinsic and extrinsic components in a MOSFET are analyzed to obtain a physics-based RF model. The procedures of the HF model parameter extraction are also developed. A subcircuit RF model based on the discussed approaches can be developed with good model accuracy. Further, noise modeling is discussed by analyzing the theoretical and experimental results in HF noise modeling. Analytical calculation of the noise sources has been discussed to understand the noise characteristics, including induced gate noise. The distortion behavior of MOSFET and modeling are also discussed. The fact that a MOSFET has much higher "low-frequency limit" is useful for designers and modelers to validate the distortion of a MOSFET model for RF application. An RF model could well predict the distortion behavior of MOSFETs if it can accurately describe both dc and ac small-signal characteristics with proper parameter extraction.     

1.0 THz GaN IMPATT Source: Effect of Parasitic Series Resistance

The degradation of high-frequency characteristics of a 1.0-THz double-drift region (DDR) impact avalanche transit time (IMPATT) diode based on wurtzite gallium nitride (Wz-GaN), due to the influence of parasitic series resistance, has been investigated. A two-dimensional (2-D) large-signal (L-S) simulation method based on a non-sinusoidal voltage excitation (NSVE) model has been used for this purpose. A comprehensive model of series resistance has been developed by considering the influence of skin effect, and the said model has been incorporated in the 2-D L-S simulation for studying the effect of RF power output and DC to RF conversion efficiency of the device. Results indicate 24.2–35.9% reduction in power output and efficiency due to the RF power dissipation in the positive series resistance. However, the device can still deliver 191.7–202.9 mW peak RF power to the load at 1.0 THz with 8.48–6.41% conversion efficiency. GaN IMPATT diodes are capable of generating higher RF power at around 1 THz than conventional diodes, but the effect of parasitic series resistance causes havoc reduction in power output and efficiency. The nature of the parasitic resistance is studied here in the level of device fabrication and optimization, which to our knowledge is not available at present.     

Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET

In this paper, for the first time, we have analyzed DC characteristics and analog/RF performances for nanowire quadruple-gate (QuaG) gate-all-around (GAA) metal oxide semiconductor field effect transistor (MOSFET), using isomorphic polynomial function for potential distribution. The QuaG GAA MOSFET not only suppresses the short channel effects (SCEs) and offer ideal subthreshold slope (SS), but also is a good candidate for analog/RF device due to its high transconductance (g_m) and high cutoff frequency (f_T). Therefore, this work would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. For this, the developed model is based on the solution of 3D Laplace and Poisson׳s equations for subthreshold and strong inversion regions respectively. The developed potential model has been used to formulate a new model for total gate, drain and source charge. Further, the expression for different capacitance for investigating RF performance is obtained from the developed model. Finally, the developed device electrostatics for QuaG GAA MOSFET have been used for the analysis of analog/RF performance. Different capacitances and analog/RF figures of merit are extracted from small signal frequency (1 MHz) ac device simulation. Whereas technology computer-aided design (TCAD) simulations have been performed by 3D ATLAS, Silvaco International.     

Modeling and Design of RF Amplifiers for Envelope Tracking WCDMA Base-Station Applications

Wideband code division multiple access (WCDMA) base-station RF amplifiers using a variety of device technologies including GaN field-effect transistors (FETs), Si LDMOS, and GaAs high-voltage heterojunction bipolar transistors (HVHBTs) are modeled, optimized, and compared for use in wideband envelope tracking (ET) system. A quasi-static approach is employed to effectively model the supply-modulated RF amplifiers, and thus facilitate the design optimization process. A new design methodology for ET RF amplifiers is introduced including identification of optimum fundamental and harmonic terminations. The fundamental and harmonic impedances have been successfully optimized for various RF devices and good agreement has been achieved between the simulation and measurement results. Among the modeled and measured ET RF amplifiers, a GaAs HVHBT exhibits the best overall efficiency of 60% with an average output power of 33 W and a gain of 10 dB for a WCDMA signal with 3.84-MHz bandwidth and 7.7-dB peak-to-average power ratio, while meeting all linearity requirements of the WCDMA standard. Desirable device characteristics for optimum ET operation are also discussed.     

InAlAs/InGaAs调制掺杂场效应晶体管研究

从理论上和实验上对InAlAs/InGaAs调制掺杂场效应晶体管(MODFET)进行了研究。建立了简单的一维电荷控制模型,并进行二维数值模拟,得到了不同偏压下器件内部电势分布和电子浓度分布。在上述理论的指导下,设计了我们所需要的器件纵向和横向结构,并对设计器件的直流特性进行了计算机辅助分析。最后叙述了利用国产Ⅳ型MBE设备生长的材料制作出MODFET的工艺过程,并对器件的直流特性和射频特性进行了测试和分析。直流测试表明,器件的最大饱和电流密度为125mA/mm,最大非本征跨导达250mS/mm;射频测试得到器件(L_g=1.0～1.2βm,W_g=150μm)的特征频率f_T为26GHz,最高振荡频率f_(max)为43GHz。     

Deep-submicrometer DC-to-RF SOI MOSFET macro-model

We present a submicrometer RF fully depleted SOI MOSFET macro-model based on a complete extrinsic small-signal equivalent circuit and an improved CAD model for the intrinsic device. The delay propagation effects in the channel are modeled by splitting the intrinsic transistor into a series of shorter transistors, for each of which a quasistatic device model can be used. Since the intrinsic device model is charge-based, our RF SOI MOSFET model can be used in both small and large-signal analyses. The model has been validated for frequencies up to 40 GHz and effective channel lengths down to 0.16 μm