具有超高耐压(>1200V)的薄埋氧层BPL SOI LDMOS(英文)

为了在薄埋氧层SOI衬底上实现超高耐压LDMOS铺平道路,提出了一种具有P埋层(BPL)的薄埋氧层SOI LDMOS 结构,耐压1200V以上.该BPL SOI LDMOS在传统SOI LDMOS的埋氧层和N型漂移区之间引入了一个P型埋层.当器件正向截止时,N型漂移区与P埋层之间的反偏PN结将承担器件的绝大部分纵向压降.采用2维数值仿真工具Silvaco TCAD对BPL SOI LDMOS进行虚拟制造和器件仿真,结果表明该结构采用适当的参数既能实现1 280 V的耐压,将BOL减薄到几百纳米以下又可以改善其热特性.     

具有补偿埋层的槽型埋氧层SOI高压器件新结构

A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance.     

浮栅结构SOI LDMOS 器件的模拟研究

研究了一种具有浮栅结构的SOI LDMOS(FGSOI LDMOS)器件模型,并分析了该结构的耐压机理,通过Silvaco TCAD软件对该结构进行仿真优化。通过仿真验证可知,该结构通过类场板的结终端技术可以调节器件的横向电场,从而得到比普通SOI LDMOS器件更高的耐压并且降低了器件的比导通电阻。仿真结果表明,该结构与普通SOI LDMOS器件结构在相同的尺寸条件下耐压提高了41%,比导通电阻降低了21.9%。     

A new integrated SOI power device based on self-isolation technology

A new SOI LDMOS structure with buried n-islands(BNIs) on the top interface of the buried oxide(BOX) is presented in a p-SOI high voltage integrated circuits(p-SOI HVICs),which exhibits good self-isolation performance between the power device and low-voltage control circuits.Furthermore,both the donor ions of BNIs and holes collected between depleted n-islands not only enhance the electric field in BOX from 32 to 113 V/μm,but also modulate the lateral electric field distribution,resulting in an improvemen...     

薄膜SOI上大于600 V LDMOS器件的研制

针对600 V以上SOI高压器件的研制需要,分析了SOI高压器件在纵向和横向上的耐压原理。通过比较提出薄膜SOI上实现高击穿电压方案,并通过仿真预言其可行性。在埋氧层为3μm,顶层硅为1.5μm的注氧键合(Simbond)SOI衬底上开发了与CMOS工艺兼容的制备流程。为实现均一的横向电场,设计了具有线性渐变掺杂60μm漂移区的LDMOS结构。为提高纵向耐压,利用场氧技术对硅膜进行了进一步减薄。流片实验的测试结果表明,器件关态击穿电压可达600 V以上(实测832 V),开态特性正常,阈值电压提取为1.9 V,计算开态电阻为50Ω.mm2。     

New High-Voltage ( $>$ 1200 V) MOSFET With the Charge Trenches on Partial SOI

A novel silicon-on-insulator (SOI) high-voltage MOSFET structure and its breakdown mechanism are presented in this paper. The structure is characterized by oxide trenches on the top interface of the buried oxide layer on partial SOI (TPSOI). Inversion charges located in the trenches enhance the electric field of the buried layer in the high-voltage blocking state, and a silicon window makes the depletion region spread into the substrate. Both of them modulate the electric field in the drift region; therefore, the breakdown voltage (BV) for a TPSOI LDMOS is greatly enhanced. Moreover, the Si window alleviates the self-heating effect. The influences of the structure parameters on device characteristics are analyzed for the proposed device structure. The TPSOI LDMOS with BV > 1200 V and the buried-layer electric field of E_I > 700 V/ mum is obtained by the simulation on a 2-mum-thick SOI layer over 2-mum-thick buried oxide layer, and its maximal temperature reduces by 19 and 8.7 K in comparison with the conventional SOI and partial SOI devices.     

非均匀厚度漂移区SOI高压器件及其优化设计

提出非均匀厚度漂移区SOI高压器件新结构及其优化设计方法. 非均匀厚度漂移区调制SOI层的电场并增强埋层电场,从而提高器件击穿电压. 考虑到这种调制效应,提出解析模型用以优化设计该新器件的结构参数. 借助解析模型,研究了电场分布和器件击穿电压与结构参数的关系. 数值仿真证实了解析模型的正确性. 具有3阶梯的非均匀厚度漂移区SOI器件耐压为常规结构SOI器件的2倍,且保持较低的导通电阻.     

一种RESURF效应增强的高压低阻槽型SOI LDMOS

本文提出一种RESURF效应增强（Enhanced RESURF Effect）的高压低阻SOI LDMOS（ER-LDMOS）新结构,并研究其工作机理。ER-LDMOS的主要特征是：漂移区中具有氧化物槽;氧化物槽靠近体区一侧具有P条;氧化物槽下方的N型漂移区中具有埋P层。首先,从体区延伸到氧化物槽底部的P条,不仅起到纵向结终端扩展的作用,而且具有纵向RESURF效果,此二者都优化体内电场分布且提高漂移区掺杂浓度;其次,埋P层在漂移区中形成triple RESURF效果,能够进一步优化体内电场并降低导通电阻;第三,漂移区中的氧化物槽沿纵向折叠漂移区,减小了器件元胞尺寸,进一步降低比导通电阻;第四,P条、埋P层、氧化物槽和埋氧层对N型漂移区形成多维耗尽作用,实现增强的RESURF效应,可达到提高漂移区掺杂浓度与优化电场分布的目的,从而降低导通电阻且提高器件耐压。仿真结果表明,在相同的器件尺寸参数下,与常规槽型SOI LDMOS相比,ER-LDMOS击穿电压提高67%,比导通电阻降低91%。     

基于RIE技术的倾斜表面SOI功率器件制备技术

对一种具有倾斜表面漂移区SOI LDMOS的制造方法进行了研究,提出了多窗口反应离子刻蚀法来形成倾斜表面漂移区的新技术,建立了倾斜表面轮廓函数的数学模型,TCAD工具的2D工艺仿真证实了该技术的可行性,最终优化设计出了倾斜表面漂移区长度为15μm的SOI LDMOS.数值仿真结果表明,其最优结构的击穿电压可达350 V...     

High-Voltage SOI SJ-LDMOS With a Nondepletion Compensation Layer

A new superjunction LDMOS on silicon-on-insulator (SOI) with a nondepletion compensation layer (NDCL) is proposed. The NDCL can be self-adaptive to provide additional charges for compensating the charge imbalance while eliminating the substrate-assisted depletion effect. In addition, the high-density oxide interface charges at the top surface of the buried oxide layer (BOX) enhance the electric field in the BOX and improve the vertical breakdown voltage (BV). Numerical simulation results indicate that a uniform surface electric field profile is obtained and that the vertical electric field in BOX is increased to $hbox{6} times hbox{10}^{6} hbox{V/cm}$, which results in a high BV of 300 V for the proposed device with the BOX thickness of 0.5 $muhbox{m}$ and drift length of 15 $muhbox{m}$ on a thin SOI substrate.      

具有T型电荷补偿区的横向超结SOILDMOS

非平衡超结器件的电荷补偿能力在薄层SOI器件中受到限制,文中提出一种具有T型电荷补偿区的器件结构。通过漏端刻蚀的PSOI结构使硅衬底与埋氧层同时参与纵向耐压,可以提高非平衡超结n区的电荷补偿能力;在埋氧层刻蚀区增加垂直的n型补偿区,弥补埋氧层的缺失。由横向的非平衡超结n区和漏端垂直的n区共同构成T型补偿区,可以有效缓解薄层SOI超结器件中的衬底辅助耗尽效应,优化横向电场,提高器件的耐压。器件的制作可以通过改进传统的PSOI工艺实现,应用于SOI功率集成电路。三维器件仿真结果表明,新结构下的器件耐压达到290V,相对于常规的SOI超结器件和非平衡超结器件提高了267%和164%。     

非均匀厚度漂移区SOI高压器件及其优化设计

提出非均匀厚度漂移区SOl高压器件新结构及其优化设计方法.非均匀厚度漂移区调制SOI层的电场并增强埋层电场,从而 提高器件击穿电压.考虑到这种调制效应.提出解析模型用以优化设计该新器件的结构参数.借助解析模型,研究了电场分布和器件击穿电压与结构参数的关系.数值仿真'证实了解析模型的正确性.具有3阶梯的非均匀厚度漂移区SOl器件耐压为常规结构SOl器件的2倍,且保持较低的导通电阻.     

衬底偏压对硅基高压器件新结构击穿电压特性的影响

提出基于衬底偏压技术的double RESURF结构,称为Sb double RESURF LDMOS。在n型衬底和n型漂移区之间嵌入p型外延层,阻挡器件阻断状态下的纵向电流通路,改变体内电场分布。衬底偏压加强漂移区电荷共享效应,降低漏极下方纵向电场峰,该技术对提高薄漂移区横向功率器件的纵向击穿电压尤其重要。结果表明,在保持较小导通电阻下,该结构较常规LDMOS击穿电压提高97%。     

薄硅层阶梯埋氧PSOI高压器件新结构

基于介质电场增强ENDIF理论,提出了一种薄硅层阶梯埋氧型部分SOI(SBPSOI)高压器件结构。埋氧层阶梯处所引入的电荷不仅增强了埋层介质电场,而且对有源层中的电场进行调制,使电场优化分布,两者均提高器件的击穿电压。详细分析器件耐压与相关结构参数的关系,在埋氧层为2μm,耐压层为0.5μm时,其埋氧层电场提高到常规结构的1.5倍,击穿电压提高53.5%。同时,由于源极下硅窗口缓解SOI器件自热效应,使得在栅电压15V,漏电压30V时器件表面最高温度较常规SOI降低了34.76K。     

漂移区为线性掺杂的高压薄膜SOI器件的研制

给出了漂移区为线性掺杂的高压薄膜SOI器件的设计原理和方法.在Si膜厚度为0.15μm、隐埋氧化层厚度为2μm的SOI硅片上进行了LDMOS晶体管的制作.首次对薄膜SOI功率器件的击穿电压与线性掺杂漂移区的杂质浓度梯度的关系进行了实验研究.通过对漂移区掺杂剂量的优化,所制成的漂移区长度为50μm的LDMOS晶体管呈现了高达612V的击穿电压.     

SBFL结构SiGe HBT器件的击穿特性研究

对高频SiGe HBT器件的击穿特性进行了研究。借助TCAD仿真工具,对超结结构引入器件集电区后的击穿特性进行了分析,提出了一种采用分裂浮空埋层结构(SBFL)的SiGe异质结器件。这种结构改善了器件的内部电场分布,电场分布由原来的单三角形分布变成双三角形分布。仿真结果表明,该器件结构的击穿电压由原有的3.6 V提高到5.4 V,提高了50%。     

700V折叠漂移区高压器件新结构

A new high-voltage LDMOS with folded drift region(FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.     

一种抗总剂量辐照的新型PD SOI器件

提出了一种具有叠层埋氧层的新栅型绝缘体上硅(SOI)器件.针对SOI器件的抗总电离剂量(TID)加固方案,对绝缘埋氧层(BOX)采用了叠层埋氧方案,对浅沟槽隔离(STI)层采用了特殊S栅方案.利用Sentaurus TCAD软件,采用Insulator Fixed Charge模型设置固定电荷密度,基于0.18 μm ...     

一种低功耗4H-SiC IGBT的仿真研究

针对传统沟槽栅4H-SiC IGBT关断时间长且关断能量损耗高的问题,文中利用Silvaco TCAD设计并仿真了一种新型沟槽栅4H-SiC IGBT结构。通过在传统沟槽栅4H-SiC IGBT结构基础上进行改进,在N ⁺缓冲层中引入两组高掺杂浓度P区和N区,提高了N ⁺缓冲层施主浓度,折中了器件正向压降与关断能量损耗。在器件关断过程中,N ⁺缓冲层中处于反向偏置状态的PN结对N ^-漂移区中电场分布起到优化作用,加速了N ^-漂移区中电子抽取,在缩短器件关断时间和降低关断能量损耗的同时提升了击穿电压。Silvaco TCAD仿真结果显示,新型沟槽栅4H-SiC IGBT击穿电压为16 kV,在15 kV的耐压设计指标下,关断能量损耗低至4.63 mJ,相比传统结构降低了40.41%。     

A new technique in LDMOS transistors to improve the breakdown voltage and the lattice temperature

A new technique for high breakdown voltage of the LDMOS device is proposed in this paper. The main idea in the proposed technique is to insert the P⁺ silicon windows in the buried oxide at the interface of the n-drift to improve the breakdown voltage, electric field and maximum lattice temperature. The proposed structure is called as P⁺ window LDMOS (PW-LDMOS). It is shown by extending the depletion region between the P⁺ windows and the n-drift region, the breakdown voltage of PW-LDMOS increases to 405 V from 84 V of the conventional LDMOS on 1 µm silicon layer and 2 µm buried oxide layer. Also, effective values of doping, length, and depth of P⁺ window are investigated in the breakdown voltage. Moreover, a self-heating-effect is alleviated by the silicon windows in comparison with the conventional LDMOS. All the achieved results have been extracted by two-dimensional and two-carriers simulator ATLAS.