High-mobility strained SiGe-on-insulator pMOSFETs with Ge-rich surface channels fabricated by local condensation technique

A new approach to form strained SiGe-on-insulator (SGOI) channel transistors, allowing fabrication of MOSFETs with very high Ge fraction in selected areas on a silicon-on-insulator substrate, is demonstrated. This method consists of epitaxial growth of an SiGe layer with a low Ge fraction and local oxidation processes. An obtained SGOI pMOSFET with a Ge fraction of 0.93 exhibits up to a tenfold enhancement in mobility. It is also found that MOSFETs having strained SGOI channels with thicknesses of less than 5 nm exhibit hole-mobility enhancement factors of over two. These results indicate that the local SGOI channels fabricated by the proposed technique are promising for implementation of high-mobility SiGe or Ge-channel MOSFETs in system-on-chip (SoC) devices.     

High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: experiments

For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band tunneling (BTBT) leakage have been investigated. In particular, through detailed experiments and simulations, the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) have been examined. In the case of strained Ge MOSFETs on bulk Si, the resulting optimal structure obtained was a UT low-defect 2-nm fully strained Ge epi channel on relaxed Si, with a 4-nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5/spl times/ over bulk Si devices, 2/spl times/ mobility enhancement and >10/spl times/ BTBT reduction over 4-nm strained Ge, and surface channel 50% strained SiGe devices. Strained SiGe MOSFETs having UT (T/sub Ge/<3 nm) very high Ge fraction (/spl sim/ 80%) channel and Si cap (T/sub Si cap/<3 nm) have also been successfully fabricated on thin relaxed SOI substrates (T/sub SOI/=9 nm). The tradeoffs in obtaining a high-mobility (smaller bandgap) channel with low tunneling leakage on UT-SOI have been investigated in detail. The fabricated device shows very high mobility enhancements of >4/spl times/ over bulk Si devices, >2.5/spl times/ over strained silicon directly on insulator (SSDOI; strained to 20% relaxed SiGe) devices, and >1.5/spl times/ over 60% strained SiGe (on relaxed bulk Si) devices.     

High-Performance Uniaxially Strained SiGe-on-Insulator pMOSFETs Fabricated by Lateral-Strain-Relaxation Technique

Novel uniaxially strained SiGe-on-insulator (SGOI) pMOSFETs with Ge content of 20% have been successfully fabricated by utilizing lateral (uniaxial) strain-relaxation process on globally (biaxially) strained SGOI substrates. Drastic increase of drain current (80%) caused by the change of strain from biaxial to uniaxial and the mobility enhancement of about 100% against the control Si-on-insulator pMOSFETs are observed in SGOI pMOSFET. This high mobility enhancement is maintained in high vertical effective fields as well as in short-channel devices. As a result, significant I_ON enhancement of 80% is demonstrated in 40-nm gate-length uniaxially strained SGOI pMOSFET     

Electron mobility enhancement in strained-Si n-MOSFETs fabricatedon SiGe-on-insulator (SGOI) substrates

We demonstrate electron mobility enhancement in strained-Si n-MOSFETs fabricated on relaxed Si_1-xGe_x-on-insulator (SGOI) substrates with a high Ge content of 25%. The substrates were fabricated by wafer bonding and etch-back utilizing a 20% Ge layer as an etch stop. Epitaxial regrowth was used to produce the upper portion of the Si_0.75Ge_0.26 and the surface strained Si layer. Large-area strained-Si n-MOSFETs were fabricated on this SGOI substrate. The measured electron mobility shows significant enhancement over both the universal mobility and that of co-processed bulk-Si MOSFETs. This SGOI process has a low thermal budget and thus is compatible with a wide range of Ge contents in Si_1-xGe_x layer     

Mobility enhancement in surface channel SiGe PMOSFETs with HfO/sub 2/ gate dielectrics

We report for the first time drive current enhancement and higher mobilities than the universal mobility for SiO/sub 2/ on Si in compressively strained Si/sub 1-x/Ge/sub x/-on-Si surface channel PMOSFETs with HfO/sub 2/ gate dielectrics, for gate lengths (L/sub G/) down to 180 nm. Thirty six percent drive current enhancement was achieved for Si/sub 0.8/Ge/sub 0.2/ channel PMOSFETs compared to Si PMOSFETs with HfO/sub 2/ gate dielectric. We demonstrate that using Si/sub 1-x/Ge/sub x/ in the channel may be one way to recover the mobility degradation due to the use of HfO/sub 2/ on Si.     

Ultrathin-body strained-Si and SiGe heterostructure-on-insulator MOSFETs

The combination of channel mobility-enhancement techniques such as strain engineering with nonclassical MOS device architectures, such as ultrathin-body (UTB) or double-gate structures, offers the promise of maximizing current drive while maintaining the electrostatic control required for aggressive device scaling in future technology nodes. The tradeoff between transport enhancement and OFF-state leakage current is compared experimentally for UTB MOSFETs in two types of materials: 1) strained Si directly on insulator (SSDOI) and 2) strained Si/strained Si/sub 1-z/Ge/sub z/ (z=0.46-0.55)/strained Si heterostructure-on-insulator (HOI). SSDOI of moderate strain level (e.g. /spl sim/ 0.8%) yields high electron-mobility enhancements for all electron densities, while high strain levels (e.g. /spl sim/ 1.6%) are required to obtain hole-mobility enhancements at high inversion charge densities. HOI is demonstrated to have similar electron-mobility characteristics to SSDOI, while hole mobilities are improved and can be maintained at high inversion charge densities. Hole mobility in strained channels with thickness below 10 nm is studied and compared for SSDOI and HOI. As the channel thickness is reduced, mobility decreases, as in unstrained silicon-on-insulator (SOI), though hole-mobility enhancements are demonstrated into the ultrathin-channel regime. Increased OFF-state leakage currents are observed in HOI compared to SSDOI and SOI. For a 4-nm-thick buried SiGe layer, leakage is reduced relative to devices with thicker SiGe channels.     

Numerical analysis of the self-heating effect in SGOI with a double step buried oxide

To reduce the self-heating effect of strained Si grown on relaxed SiGe-on-insulator(SGOI) n-type metal-oxide-semiconductor field-effect transistors(nMOSFETs),this paper proposes a novel device called double step buried oxide(BOX) SGOI,investigates its electrical and thermal characteristics,and analyzes the effect of self-heating on its electrical parameters.During the simulation of the device,a low field mobility model for strained Si MOSFETs is established and reduced thermal conductivity resulting from phonon boundary scattering is considered.A comparative study of SGOI nMOSFETs with different BOX thicknesses under channel and different channel strains has been performed.By reducing moderately the BOX thickness under the channel,the channel temperature caused by the self-heating effect can be effectively reduced.Moreover,mobility degradation,off state current and a short-channel effect such as drain induced barrier lowering can be well suppressed.Therefore,SGOI MOSFETs with a thinner BOX under the channel can improve the overall performance and long-term reliability efficiently.     

Mobility enhancement in dual-channel P-MOSFETs

Hole mobility is characterized in P-MOSFETs with a layered substrate consisting of tensile strained Si cap on a compressively strained Si/sub 0.4/Ge/sub 0.6/ buried layer grown pseudomorphically to a relaxed Si/sub 0.7/Ge/sub 0.3/ virtual substrate. Besides the expected mobility enhancement in the strained Si cap and in the buried Si/sub 0.4/Ge/sub 0.6/ layer, a second peak in mobility versus total inversion carrier areal density curve was observed under strong inversion conditions in thin Si-cap layer samples. Qualitatively, this reversed mobility trend can be correlated to the transition of inversion conduction from the buried layer to the surface layer, but quantitative analysis reveals that the surface layer mobility in thin Si-cap samples needs to be substantially larger than that in thick-cap samples, if it can be assumed that mobility is a function of transverse field. Further analysis found that, if it is assumed that mobility is a function of inversion carrier density, measured mobility curves can be matched consistently with a single set of mobility-carrier-density relationship.     

Experimental study on superior mobility in [110]-oriented UTB SOI pMOSFETs

The superior mobility in [110]-oriented ultrathin body (UTB) pMOSFETs with silicon-on-insulator (SOI) thickness (t/sub SOI/) ranging from 32 down to 2.3 nm is experimentally examined for the first time. It is shown that the mobility in [110] UTB pMOSFETs, which is much higher than the universal curve in conventional (100) pMOSFETs, is not degraded until t/sub SOI/ is thinned to 3 nm. Scattering mechanisms in [110] UTB pMOSFETs are discussed on the basis of the temperature dependence of the mobility. The high mobility in the UTB regime in [110] pMOSFET is attributed to subband modulation by carrier confinement and heavier hole effective mass normal to the channel surface.     

Influence of surface treatment prior to ALD high-/spl kappa/ dielectrics on the performance of SiGe surface-channel pMOSFETs

Compressively strained Si/sub 0.7/Ge/sub 0.3/ surface-channel pMOSFETs with atomic layer deposition (ALD) Al/sub 2/O/sub 3//HfO/sub 2//Al/sub 2/O/sub 3/ nanolaminate and low-pressure chemical vapor deposition p/sup +/ poly-SiGe gate electrode were fabricated. Surface treatment with either hydrogen fluoride (HF) clean, or HF clean followed by water rinse was performed prior to the ALD processing. The devices with water rinse show a good control of interfacial layer and device reproducibility, while the devices without water rinse lack a clearly observable interfacial layer and show scattered electrical characteristics and distorted mobility curve. A /spl sim/20% increase in hole mobility compared to the Si universal mobility and a /spl sim/0.6-nm-thick continuous interfacial layer are obtained for the pMOSFETs with water rinse.     

Fully depleted n-MOSFETs on supercritical thickness strained SOI

Strained silicon-on-insulator (SSOI) is a new material system that combines the carrier transport advantages of strained Si with the reduced parasitic capacitance and improved MOSFET scalability of thin-film SOI. We demonstrate fabrication of highly uniform SiGe-free SSOI wafers with 20% Ge equivalent strain and report fully depleted n-MOSFET results. We show that enhanced mobility is maintained in strained Si films transferred directly to SiO/sub 2/ from relaxed Si/sub 0.8/Ge/sub 0.2/ virtual substrates, even after a generous MOSFET fabrication thermal budget. Further, we find the usable strained-Si thickness of SSOI significantly exceeds the critical thickness of strained Si/SiGe without deleterious leakage current effects typically associated with exceeding this limit.     

[110] strained-SOI n-MOSFETs with higher electron mobility

We have recently developed [110]-surface strained silicon-on-insulator (SOI) n-MOSFETs. The strained-silicon (Si) layer with the strain of about 0.6% has been fabricated on a relaxed SiGe-on-insulator (SGOI) structure with the germanium (Ge) content of 25%. The electron mobility characteristics along the various current directions have been experimentally studied and compared to those of [100]- and [110]-surface unstrained-bulk MOSFETs. We have demonstrated, for the first time, that the electron mobility of [110] strained-SOI MOSFETs is enhanced, compared to that of [110] unstrained-bulk MOSFETs. The electron mobility enhancement depends on the current-flow directions, and the maximum enhancement factor amounts to 23% along the <001> direction. As a result, the electron mobility ratio of [110] strained-SOI MOSFETs to [100] universal mobility is 81% at maximum, whereas the ratio of [110] unstrained-bulk MOSFETs is only 66%. Therefore, [110] strained-SOI devices are also promising candidates for future high-performance CMOS.     

Influence of high channel doping on the inversion layer electron mobility in strained silicon n-MOSFETs

In this letter, we investigate the dependence of electron inversion layer mobility on high-channel doping required for sub-50-nm MOSFETs in strained silicon (Si), and we compare it to co-processed unstrained Si. For high vertical effective electric field E/sub eff/, the electron mobility in strained Si displays universal behavior and shows enhancement of 1.5-1.7/spl times/ compared to unstrained Si. For low E/sub eff/, the mobility for strained Si devices decreases toward the unstrained Si data due to Coulomb scattering by channel dopants.     

Implementation of both high-hole and electron mobility in strained Si/strained Si/sub 1-y/Ge/sub y/ on relaxed Si/sub 1-x/Ge/sub x/ (x

Jongwan Jung Lee  M.L. Shaofeng Yu Fitzgerald  E.A. Antoniadis  D.A. 《Electron Device Letters, IEEE》2003,24(7):460-462

应变Si1-xGex pMOSFET反型沟道空穴低场迁移率模型

在考虑应变对SiGe合金能带结构参数影响的基础上,提出了一个半经验的应变Sil-xGex/Si pMOSFET反型沟道空穴迁移率模型.在该模型中,给出了迁移率随应变的变化,并且考虑了界面陷阱电荷对载流子的库仑散射作用.利用该模型对室温下空穴迁移率随应变的变化及影响空穴迁移率的因素进行了分析讨论.     

Oxygen segregation and Ge diffusion in annealed oxygen ion-implanted relaxed SiGe/Si heterostructures

Relaxed SiGe-on-insulator (SGOI) is a suitable material to fabricate strained Si structures. Separation-by-implantation-of-oxygen (SIMOX) is a competing method to synthesize SGOI materials. In this work, SiGe/Si samples were implanted with 3×10¹⁷ cm⁻² oxygen ions at 60 kV, followed by high-temperature annealing. Oxygen segregation and Ge diffusion during the annealing process were investigated using Rutherford backscattering spectroscopy/channeling (RBS/C), high-resolution x-ray diffraction (HRXRD), and high-resolution transmission electron microscopy (HRTEM). Our results show that the sample structure strongly depends on the thermal history and Ge diffuses mainly at the beginning stage of the high-temperature process. The process can be improved by introducing an annealing step at a medium temperature before high-temperature annealing, and sharper interfaces and good crystal quality can be obtained. Our results indicate that the SIMOX process for silicon-on-insulator (SOI) fabrication can be adopted to produce SGOI.     

High drive current NMOS with Si-SiGe heterostructure low electric field channel

A drive-current enhancement in NMOS with a compressively strained SiGe structure, which had been a difficult challenge for CMOS integration with strained SiGe high-hole-mobility PMOS, was successfully achieved using a Si-SiGe heterostructure low electric field channel of optimum thickness. A 4-nm-thick Si low-field-channel NMOS with a 4-nm-thick Si/sub 0.8/Ge/sub 0.2/ layer improved drive current by 10% with a 20% reduction in gate leakage current compared with Si-control, while suppressing threshold-voltage rolloff characteristic degradation, and demonstrated excellent I/sub on/--I/sub off/ characteristics of I/sub on/ = 1 mA//spl mu/m for I/sub off/ = 100 nA//spl mu/m. These results are the best in ever reported NMOS with a compressively strained SiGe structure and indicate that a Si-SiGe heterostructure low-field-channel NMOS integrated with a compressively strained SiGe channel PMOS is a promising candidate for high-speed CMOS in 65-nm node logic technology.     

A 90-nm logic technology featuring strained-silicon

A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%, respectively. Using selective epitaxial Si/sub 1-x/Ge/sub x/ in the source and drain regions, longitudinal uniaxial compressive stress is introduced into the p-type MOSEFT to increase hole mobility by >50%. A tensile silicon nitride-capping layer is used to introduce tensile strain into the n-type MOSFET and enhance electron mobility by 20%. Unlike all past strained-Si work, the hole mobility enhancement in this paper is present at large vertical electric fields in nanoscale transistors making this strain technique useful for advanced logic technologies. Furthermore, using piezoresistance coefficients it is shown that significantly less strain (/spl sim/5 /spl times/) is needed for a given PMOS mobility enhancement when applied via longitudinal uniaxial compression versus in-plane biaxial tension using the conventional Si/sub 1-x/Ge/sub x/ substrate approach.     

DC and RF Characteristics of Si0.8Ge0.2 pMOSFETs: Enhanced Operation Speed and Low 1/f Noise

This paper reports on our investigation of DC and RF characteristics of p‐channel metal oxide semiconductor field effect transistors (pMOSFETs) with a compressively strained Si_0.8Ge_0.2 channel. Because of enhanced hole mobility in the Si_0.8Ge_0.2 buried layer, the Si_0.8Ge_0.2 pMOSFET showed improved DC and RF characteristics. We demonstrate that the 1/f noise in the Si_0.8Ge_0.2 pMOSFET was much lower than that in the all‐Si counterpart, regardless of gate‐oxide degradation by electrical stress. These results suggest that the Si_0.8Ge_0.2 pMOSFET is suitable for RF applications that require high speed and low 1/f noise.     

Characterization of GeSn materials for future Ge pMOSFETs source/drain stressors

In order to outperform current uniaxial compressively strained Silicon channel pMOSFET technology (with embedded SiGe source/drain), switching to strained Ge channel is mandatory. GeSn materials, having larger lattice parameter than Ge, are proposed in this article as embedded source/drain stressors for Ge channels. Our simulation results indicate that a minimum of 5% Sn is required in the GeSn source/drain to build a competitive strained Ge pMOSFETs with respect to strained Si channels. Therefore the compatibility of GeSn (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation and NiGeSn formation) has been studied. A low thermal budget has been determined for those processes on GeSn alloys: temperatures must be lower than 600 °C for B activation and lower than 450 °C for NiGeSn formation.