基于SoC设计的软硬件协同验证方法学

文章介绍了软硬件协同验证方法学及其验证流程。在软件方面，采用了一套完整的软件编译调试仿真工具链，它包括处理器的仿真虚拟原型和基本的汇编、链接、调试器；在硬件方面，对软件调试好的应用程序进行RTL仿真、综合，并最终在SoC设计的硬件映像加速器（FPGA）上实现并验证。     

飞思卡尔公司的多核战略

多核（Multi—core）、很多核（Many Core）技术可以提供更高的处理器性能、更有效的电源利用率,更少的物理空间等优势,但是在软、硬件开发土颇具挑战,其中软件的挑战相对更大。本期,我们编发了一组3篇文章,探讨了多核芯片的设计难点,多核芯片的软件调试,以及多核的图形化开发方法。[编者按]     

风河与Cavium Networks合作

设备软件优化厂商风河系统公司（Wind River）与高集成化半导体产品供应商Cavium Networks公司日前共同宣布推出高级多核设备开发解决方案,把风河Workbench On-Chip Debugging和Wind River Compiler与Cavium Networks OCTEON多核处理器的整合为一体,为客户提供了一个简化的开发环境,其中包括了完整的开发环境体系、片上调试工具、编译器、全套技术支持和服务。此外,通过全新的解决方案,硬件和软件开发人员可以在尖端多核产品开发中获得更高的开发效率和更佳的用户体验,不断提高产品开发质量,缩短产品上市时间,同时减少程序错误。     

SOC验证平台的联合架构设计

随着芯片行业的不断发展,软件和硬件之间的联系日趋紧密,复杂SOC的设计难点逐渐转移到SoC的验证与调试环节。软硬件协同验证技术作为SOC仿真验证的关键技术,起着越来越重要的作用。文中研究将ARM处理器的指令软件仿真器SocDesigner和RTL硬件仿真器EVE相结合的联合仿真平台架构技术,给出了两个仿真系统通信机制和同步策略,并且以导航模块为例,给出了基于该系统的仿真环境的架构设计和仿真效率的性能测试结果。     

可扩展微处理器缩短了SOC的模拟与开发时间

硅制造工艺技术的快速进步使系统级芯片(SOC)的设计困难重重。目前硅芯片的集成度不断提高,但这些数据处理能力十分强的IC在实现时几乎都是采用寄存器传送级(RTL)硬件。加速开发百万门级SOC的方法之一是采用多个处理器芯核去执行数据处理任务,即将目前由RTL逻辑线路执行的任务转移给处理器去完成。SOC设计人员面临的问题可扩展处理器是采用固件(firmware)来取代RTL固定不能改变的硬件,来实现算法控制的功能;而对于许多嵌入式SOC,如果采用以处理器为基础的引擎来执行,与以RTL为基础的硬件相比,可以更容易、快速地进行设计与模拟验…     

基于SB3500多核处理器的软件无线电系统设计

针对基于软件无线电架构的现代移动通信手持终端设计,研究了基于SB3500国产多核多线程数字信号处理器的软件无线电设计方法,实现了基于SB3500的软件无线电硬件系统。在此基础上开发了一套适合该硬件系统的OFDM通信波形软件,用于验证该硬件系统是否满足手持终端小型化和低功耗的要求。研究表明,使用该国产多核多线程处理器进行软件无线电系统的设计开发具有广泛的应用前景。     

基于RTL8019AS的单片机网络通信接口设计

网络数据传输技术具有传输速率高、传送距离远、通讯协议完善、信息共享程度高等优点,为嵌入式设备增加网络功能有着深远的意义。介绍以太网的帧协议和以太网控制芯片RTL8019AS的结构特性以及工作原理,设计STC89C54RD 单片机控制RTL8019AS实现以太网通讯的硬件设计方案和软件流程图;采用标准C语言实现ARP协议,所有程序在Keil c51环境下编译连接。最后并进行系统的调试与验证,取得了满意的效果。     

一种基于AMBA总线的SoC硬件加速器设计

为了解决面向特定的应用场景下,嵌入式处理器处理能力不足的问题,针对片上SoC系统设计了一款硬件加速器,通过对系统算法进行深入分析,确定了硬件加速器的功能需求,并基于AMBA(Advanced Microcontroller Bus Architecture)总线架构设计了相关接口,使其符合AMBA总线协议的时序要求。在完成RTL代码之后,通过对电路进行仿真进一步验证了硬件加速器的时序功能与逻辑功能。仿真结果表明硬件加速器确实提高了系统整体的数据处理性能与算法程序的执行效率。     

RTL8019型控制器与高速数字信号处理器的接口设计及编程技巧

基于美国TI公司的高速数字信号处理器(DSP),详细描述RTL8019型以太网控制器的性能特点和引脚功能.同时给出DSP与RTL8019的硬件电路接口设计方法及DSP控制RTL8019进行网络传输的相应软件编程方法.     

一种双核SoC调试系统的设计与验证

调试系统的设计和验证是多核SoC设计中的重要环节。基于某双核SoC的设计,提出一个片上硬件调试构架,利用FPGA构建该调试系统的硬件验证平台。双核SoC调试系统验证平台利用System Verilog DPI,将RealView调试器、Keil C51及目标芯片的验证testbench集成在一起,实现了双核SoC调试系统的RTL级调试验证。利用该平台,在RTL仿真验证阶段可方便地对ARM和8051核构成的双核SoC进行调试,解决仿真中出现的问题,从而有效缩短设计周期,并提高验证效率。该双核SoC调试系统验证平台的实现对其他系统芯片设计具有一定的参考价值。     

一种32 Bit SoC软硬件协同验证环境的实现

软硬件协同验证是系统芯片设计的重要组成部分。针对基于32 Bit CPU核的某控制系统芯片的具体要求,提出了一种系统芯片软硬件协同验证策略,构建了一个软硬件协同验证环境。该环境利用处理器内核模型支持内核指令集的特性运行功能测试程序,实现SoC软硬件的同步调试,并能够快速定位软硬件的仿真错误点,有效提高了仿真效率。该SoC软硬件协同验证环境完成了设计目的,并对其他系统芯片设计具有一定的参考价值。     

Applying SMT-based verification to hardware/software partitioning in embedded systems

When performing hardware/software co-design for embedded systems, the problem of which functions of the system should be implemented in hardware (HW) or in software (SW) emerges. This problem is known as HW/SW partitioning. Over the last 10 years, a significant research effort has been carried out in this area. In this paper, we present two new approaches to solve the HW/SW partitioning problem by using verification techniques based on satisfiability modulo theories (SMT). We compare the results using the traditional technique of integer linear programming, specifically binary integer programming and a modern method of optimization by genetic algorithm. The experimental results show that SMT-based verification techniques can be effective in particular cases to solve the HW/SW partition problem optimally using a state-of-the-art model checker based on SMT solvers, when compared against traditional techniques.     

USB2．0主控器软硬件协同仿真系统设计

为了能够充分、快速验证USB2．0主控器的功能,设计了一个软硬件协同仿真平台。其中,CPU模型部分采用一种高效的SystemC模型,而不使用基于指令集的复杂CPU模型。测试用例采用抽象层次更高的C语言编写,通过调用仿真平台对外提供的API完成激励生成与响应检查。结果表明,该方式能够有效降低对仿真资源的占用,减少仿真时间;同时使软件人员能在IP的硬件验证阶段就能完成软件的设计测试工作,缩短软硬件接口整合时间,加快开发进度。     

全定制软/硬件协同设计中的硬件优化技术

提出了基于单相似系统生成的软/硬件协同设计中的硬件优化技术.介绍了一种基于子图匹配软/硬件协同设计技术的大致框架,引进通用子图群合并算法,并着重讨论了基于节点压缩优化技术的高效子图群合并算法.实验结果很好地证明了所有上述理论的正确性以及算法的有效性.     

一种面向嵌入式SoC设计的混合级硬/软件协同验证技术

SoC已经成为嵌入式系统必不可少的解决方案。验证如此复杂的嵌入式SoC是非常困难的,系统设计需要新的验证技术更快更好地完成系统功能验证任务。通过比较当前3种主要的嵌入式系统验证技术:软件仿真技术、硬件模拟技术、硬/软件协同验证仿真技术,介绍基于指令集仿真器和FPGA相结合的、面向IP核复用的混合级硬/软件协同验证环境,并提出混合级协同验证总线功能模块的构成。该技术不仅可以提高设计的可信性和验证速度,而且能够继承当前大多数硬件模拟验证方法。     

An FPGA implementation of HW/SW codesign architecture for H.263 video coding

In this paper, we present an efficient HW/SW codesign architecture for H.263 video encoder and its FPGA implementation. Each module of the encoder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portions include the Discrete Cosine Transform (DCT), inverse DCT (IDCT), quantization (Q) and inverse quantization (IQ). Remaining parts were realized in software executed by the NIOS II softcore processor. This paper also introduces efficient design methods for HW and SW modules. In hardware, an efficient architecture for the 2-D DCT/IDCT is suggested to reduce the chip size. A NIOS II Custom instruction logic is used to implement Q/IQ. Software optimization technique is also explored by using the fast block-matching algorithm for motion estimation (ME). The whole design is described in VHDL language, verified in simulations and implemented in Stratix II EP2S60 FPGA. Finally, the encoder has been tested on the Altera NIOS II development board and can work up to 120 MHz. Implementation results show that when HW/SW codesign is used, a 15.8-16.5 times improvement in coding speed is obtained compared to the software based solution.     

全定制软/硬件协同设计中的硬件优化技术

提出了基于单相似系统生成的软/硬件协同设计中的硬件优化技术.介绍了一种基于子图匹配软/硬件协同设计技术的大致框架,引进通用子图群合并算法,并着重讨论了基于节点压缩优化技术的高效子图群合并算法.实验结果很好地证明了所有上述理论的正确性以及算法的有效性.     

Unifying simulation and execution in a design environment for FPGAsystems

Field programmable gate array (FPGA)-based systems provide advantages over conventional hardware including: (1) availability of the hardware during design and debug; (2) programmability; and (3) visibility. These three advantages can greatly shorten the design and verification cycle. This paper discusses a design environment that exploits these three FPGA-specific advantages to create a unified simulation/execution debug environment implemented in the JHDL design system. The described system provides a hardware debugging environment with the functionality of a simulator but up to 10000× faster. In addition, testbenches and other typical verification software used in simulators can be used to verify running hardware     

The in-circuit approach to the development of microcomputer-based products

For years, software and hardware development for micro-computer-based products was accomplished by two segregated development efforts. This approach resulted in wasted effort and delays due to inconsistencies between hardware specifications and software implementation at the prototype level. In-circuit emulation, a major breakthrough in microcomputer development systems, has provided the ability to integrate hardware and software development during all phases of the development cycle. The software designer can now work with the prototype hardware as it is being designed by the hardware engineer. In addition, the hardware designer is now able to construct his hardware while working with the actual design software, facilitating debug as hardware development progresses. For the first time, powerful microcomputer development system debug aids can be applied in the user environment.     

VHDL-based rapid system prototyping

The Rapid Prototyping of Application-Specific Signal Processors (RASSP) [1–3] program of the US Department of Defense (ARPA and Tri-Services) targets a 4X improvement in the design, prototyping, manufacturing, and support processes (relative to current practice). Based on a current practice study (1993) [4], the prototyping time from system requirements definition to production and deployment, of multiboard signal processors, is between 37 and 73 months. Out of this time, 25–49 months is devoted to detailed hardware/software (HW/SW) design and integration (with 10–24 months devoted to the latter task of integration). With the utilization of a promising top-down hardware-less codesign methodology based on VHDL models of HW/SW components at multiple abstractions, reduction in design time has been shown especially in the area of hardware/software integration [5]. The authors describe a top-down design approach in VHDL starting with the capture of system requirements in an executable form and through successive stages of design refinement, ending with a detailed hardware design. This hardware/software codesign process is based on the RASSP program design methodology called virtual prototyping, wherein VHDL models are used throughout the design process to capture the necessary information to describe the design as it develops through successive refinement and review. Examples are presented to illustrate the information captured at each stage in the process. Links between stages are described to clarify the flow of information from requirements to hardware.