Design of high-performance compact CMOS distributed amplifiers with on-chip patterned ground shield inductors

A CMOS distributed amplifier incorporating on-chip patterned ground shield (PGS) spiral inductors has been developed using a standard low cost 0.25 μm CMOS process. Measured results show that this distributed amplifier has an average gain of 7 dB, return loss of more than 10 dB, and noise figure between 4.1-6.1 dB across DC 11 GHz. The amplifier occupies a small chip area of only 1.2 x 0.8 mm², including RF pads. These represent the best results for 0.25 μm CMOS distributed amplifiers and demonstrate that miniaturisation and high performance can be achieved for CMOS distributed amplifiers and other wideband RFICs by implementing on-chip PGS inductors.     

Spread spectrum clock generator with hybrid controlled oscillator

A spread spectrum clock generator (SSCG) with a hybrid controlled oscillator (HCO) is presented. By using the proposed HCO, the modulation ratio of an SSCG can be made insensitive to process, voltage and temperature variations without a ΣΔ fractional-N phase-locked loop. The simulated modulation ratio sensitivities are as low as -1.3%/ 100°C and 7.0%/V for temperature and V_DD, respectively. The SSCG IC, designed in a 0.18 μm 1P4M CMOS process, operates from 40 to 90 MHz and consumes 5.5 mA from a 1.8 V supply voltage.     

Highly linear and low noise differential bipolar MOSFET down-converter in CMOS process

A highly linear, low noise differential down-converter employing a new linearisation technique derived from composite transistors, i.e. nMOSFET and vertical NPN BJT, is proposed and implemented in a 0.18 μm CMOS technology. It draws 1 mA from a 2.5 V supply voltage and has a voltage gain of 13 dB, a double-sideband noise figure of 9.5 dB, an IIP2 of more than 49 dBm, and an IIP3 of 6.5 dBm.     

20-850 MHz low-distortion baseband amplifier in digital CMOS process

A CMOS baseband amplifier using an open-loop architecture is presented. The eight-stage amplifier, implemented in a standard 0.13 μm CMOS technology, shows a maximum gain of 30 dB in the broadband frequency range 20?850 MHz. Each amplification stage draws 0.8 mA from a single 1.2 V power supply. The total amplifier chain shows an output referred OIP3 of 11 dBm, which can be achieved by using active loads that compensate for the nonlinear transconductance of the input transistors.     

Cascaded voting process for flash ADC with interpolating scheme

A 3-stage cascaded voting process is proposed for flash analogue-todigital converters (ADCs) with an interpolation factor of 4 to eliminate the consecutive bubbles at the output nodes of the comparator array. Compared to the conventional 3-input voting process, the proposed process completely eliminates up to seven consecutive bubbles without hardware overhead, if the preamplifier output is assumed to have a single bubble at most. The proposed voting process is evaluated by 7-bit 1 GS/s CMOS flash ADCs with an interpolation factor of 4 which is designed by a 0.13 μm CMOS process with 1.2 V supply.     

Sigma?delta digital drive signals for switchmode power amplifiers

A novel all-digital approach to generate a pulse train to drive switchmode power amplifiers is proposed. Sigma?delta (ΣΔ) techniques are used to shape time quantisation noise away from the band of interest. The proposed architecture promises greater than 10 dB improvement in adjacent channel power over an existing scheme. The key contribution is to quantise in the polar domain while performing the ΣΔ filtering in the Cartesian domain.     

High multiplication factor capacitor multiplier for an on-chip PLL loop filter

A capacitor multiplier with a high multiplication factor and low power consumption is proposed to integrate a large capacitor of a phase-locked loop (PLL) loop filter in a small chip area. The proposed capacitor multiplier makes capacitance of 516.8 pF using an on-chip capacitor of 7.95 pF with current consumption of 100 μA. An integer-N PLL with a channel space of 1 MHz was fabricated with a 0.18 μm CMOS technology to employ the proposed capacitor multiplier.     

1 V, 0.18 μm-area and power efficient UWB LNA utilising active inductors

A low-noise amplifier (LNA) for the lower ultra wideband (UWB) communication bandwidth (3.1-4.8 GHz) utilising area and power efficient active inductor implementation is presented. A loss regulated active inductor structure is used to realise shunt peaking inductances, which enable the design to attain a tunable peak S _{of 14.85 dB with a 23 dB bandwidth of 2.75-4.9 GHz. Implemented in 0.18 μm CMOS technology with a 1 V supply voltage, the LNA core consumes 7.1 mA while occupying an area of only 0.05 mm^.}     

A WDM receiver photonic integrated circuit with net on-chip gain

We demonstrate a photonic circuit with an optical preamplifier, a WDM filter and a fast photodetector integrated on the same chip. The passive integrated filter is formed by an aspheric waveguide lens and a planar Bragg grating. This arrangements yields narrow filter response (8 Å width at -3 dB is demonstrated) and high rejection ratio of 24 dB. The optical preamplifier consisting of strained multi-quantum well layers provides sufficient amplification to overcome the passive losses. Response curves demonstrate net on-chip gain with low ripple     

A Wideband Millimeter-Wave Power Amplifier With 20 dB Linear Power Gain and +8 dBm Maximum Saturated Output Power

A millimeter-wave power amplifier fabricated in 90 nm bulk CMOS technology consists of 3 identical cascode stages and on-chip matching networks (inter-stage, input, and output) implemented with wide-gap coplanar waveguides and M6-M5 (MIM) capacitors. The amplifier realizes a linear power gain of 19.7 dB at 52.4 GHz and 10.3 dB at 60 GHz. Maximum saturated output power and output-referred compression point are and 3.1 dBm, respectively. Peak PAE is 4.2%. The 1.180.96 die consumes 75 mA when operating from a 2 V supply.     

Low power CMOS preamplifier for neural recording applications

A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extracellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1 μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.     

A 19-mW 2.6-mm/sup 2/ L1/L2 dual-band CMOS GPS receiver

This paper presents the design and implementation of an L1/L2 dual-band global positioning system (GPS) receiver. Dual-conversion with a low-IF architecture was used for dual-band operation. The receiver is composed of an RF preamplifier, down-conversion mixers, a variable-gain channel filter, a 2-bit analog-to-digital converter, and the full phase-locked-loop synthesizer including an on-chip voltage controlled oscillator. Fabricated in a 0.18-/spl mu/m CMOS technology, the receiver exhibits maximum gain of 95 dB and noise figures of 8.5 and 7.5 dB for L1 and L2, respectively. An on-chip variable-gain channel filter provides IF image rejection of 20 dB and gain control range over 60 dB. The receiver consumes 19 mW from a 1.8-V supply while occupying a 2.6-mm/sup 2/ die area including the ESD I/O pads.     

2.5 V passive CMOS mixer with 20 dBm P1 dB compression

A passive CMOS downconversion mixer with LO buffer is presented in 0.25 μm SiGe BiCMOS using a 2.5 V supply. With a 60 MHz RF signal input, measurements show that the conversion loss is 2.9 dB, the input-referred 1 dB compression point is 20 dBm and the inputreferred noise is 2146.8 dBm/Hz. Compared to conventional NMOS mixers, the 1 dB compression point is improved by 9.7 dB. The tradeoffs and the design of the LO buffer, which has a strong impact on the intermodulation distortion, are also presented.     

A 10-bit 50-MS/s reference-free low power SAR ADC in 0.18-μm SOI CMOS technology

正A 10-bit 50-MS/s reference-free low power successive approximation register(SAR) analog-to-digital converter(ADC) is presented.An energy efficient switching scheme is utilized in this design to obtain low power and high frequency operation performance without an additional analog power supply or on-chip/off-chip reference. An on-chip calibration DAC(CDAC) is implemented to cancel the offset of the latch-type sense amplifier(SA) to ensure precision whilst getting rid of the dependence on the pre-amplifier,so that the power consumption can be reduced further.The design was fabricated in IBM 0.18-μm 1P4M SOI CMOS process technology.At a 1.5-V supply and 50-MS/s with 5-MHz input,the ADC achieves an SNDR of 56.76 dB and consumes 1.72 mW,resulting in a figure of merit(FOM) of 61.1 fJ/conversion-step.     

0.5 V ultra-low power wideband LNA with forward body bias technique

An ultra-low power wideband CMOS low noise amplifier (LNA) fabricated in TSMC 0.18 μm RF CMOS process for sub 1 GHz applications is presented. The capacitive cross-coupled LNA with forwardbody- bias (FBB) technique is adopted to achieve wideband input impedance matching and low power, low noise factor. The LNA is tested in the frequency range of 400?900 MHz, and exhibits a voltage gain of 18.5?20.7 dB, and a noise figure of 2.95 dB, drawing only 0.385 mW from 0.5 V power supply.     

Lead chalcogenide VECSEL on Si emitting at 5 μm

A mid-infrared vertical external cavity surface emitting laser (VECSEL) on a Si substrate has been realised. It is optically pumped and emits around 5 μm wavelength. Maximum output power of 26 mW_p (limited by the 1.5μm wavelength pump laser) was observed at 100 K operating temperature with 3μs pulse widths. The active part is just a 1.3μm-thick PbTe layer.     

A 2.5-GHz BiCMOS transceiver for wireless LAN's

A BiCMOS transceiver intended for spread spectrum applications in the 2.4-2.5 GHz band is described. The IC contains a low-noise amplifier (LNA) with 14 dB gain and 2.2 dB NF in its high-gain mode, a downconversion mixer with 8 dB gain and 11 dB NF, and an upconversion mixer with 17 dB gain and P_{-1 dB} of +3 dBm out. An on-chip local oscillator (LO) buffer accepts LO drive of -10 dBm with a half-frequency option allowed by an on-chip frequency doubler. Power consumption from a single 3-V supply is 34 mA in transmit mode, 21 mA in receive mode, and 1 μA in sleep mode     

On-chip antenna design for UHF RFID

An on-chip antenna suitable for radio frequency identification at UHF band is presented. It is integrated with an EPC Class 1 Generation 2 compatible tag in SMIC 0.18 μm standard CMOS process. The tag achieves a 1 cm communication distance with 1 W reader output power.     

Highly linear and low noise 2.4 GHz RF front-end circuits using transformer and vertical NPN BJT

The proposed RF front-end circuits consist of a low noise amplifier using an on-chip transformer and a downconversion mixer using a parasitic vertical bipolar junction transistor and have been implemented in 0.18 mum deep n-well CMOS process. A gain of 33 dB, an IIP3 of -12 dBm, and a DSB noise figure of 4.5 dB have been achieved while consuming 5 mW from a 1.8 V supply     

A widely tunable continuous-time LPF for a direct conversion DBS tuner

A continuous-time 7th-order Butterworth Gm-C low pass filter (LPF) with on-chip automatic tuning circuit has been implemented for a direct conversion DBS tuner in 0.35μm SiGe BiCMOS technology. The filter's -3 dB cutoff frequency f0 can be tuned from 4 to 40 MHz. A novel on-chip automatic tuning scheme has been successfully realized to tune and lock the filter's cutoff frequency. Measurement results show that the filter has -0.5 dB passband gain, +/- 5% bandwidth accuracy, 30 nV/Hz1/2 input referred noise, -3 dBVrms passband IIP3, and 27 dBVrms stopband IIP3. The I/Q LPFs with the tuning circuit draw 13 mA (with f0 = 20 MHz) from 5 V supply, and occupy 0.5 mm2.