短沟道SOI MOSFET总剂量辐照效应模型

报道了一个含总剂量辐照效应的SOI MOSFET统一模型.该模型能自动计入体耗尽条件,不需要分类考虑不同膜厚时的情况.模型计算结果与实验吻合较好.该模型物理意义明确,参数提取方便,适合于抗辐照SOI器件与电路的模拟.     

全耗尽SOIMOSFET辐照导致的阈值电压漂移模型

报道了全耗尽SOI MOSFET器件阈值电压漂移与辐照剂量和辐照剂量率之间的解析关系.模型计算结果与实验吻合较好.该模型物理意义明确,参数提取方便,适合于低辐照总剂量条件下的加固SOI器件与电路的模拟.讨论了抑制阈值电压漂移的方法.结果表明,对于全耗尽SOI加固工艺,辐照导致的埋氧层(BOX)氧化物电荷对前栅的耦合是影响前栅阈值电压漂移的主要因素,但减薄埋氧层厚度并不能明显提高SOI MOSFET的抗辐照性能.     

SOIMOSFET因辐照引起的部分耗尽与全耗尽过渡区的漂移

首次报道了辐照所引起的 SOI/ MOS器件 PD (部分耗尽 )与 FD (全耗尽 )过渡区的漂移 .基于含总剂量辐照效应的 SOI MOSFET统一模型 ,模拟了 FD与 PD过渡区随辐照剂量的漂移 .讨论了辐照引起 FD与 PD器件转化的原因 ,进一步分析了 FD与 PD器件的辐照效应     

一种基于总剂量效应的SOI器件模型快速提取方法

从工程应用的角度介绍了一种基于总剂量效应的SOI器件模型参数的快速提取方法。首先,提取0 krad(Si)时器件的模型参数,然后针对总剂量敏感参数,对100 krad(Si)总辐射试验后的同种器件进行模型参数优化,并对得到的模型参数进行验证。结果表明,该方法所提取的模型参数准确有效,解决了国内目前在抗辐照SOI工艺中因采用标准SOI工艺SPICE模型(如BSIMSOI等)导致不能反映辐照效应对器件特性的影响且无法给出经过不同辐照剂量之后的器件特性的缺点,可用于评估辐射对SOI电路的影响。     

SOI MOSFET因辐照引起的部分耗尽与全耗尽过渡区的漂移

首次报道了辐照所引起的SOI/MOS器件PD(部分耗尽) 与FD(全耗尽) 过渡区的漂移．基于含总剂量辐照效应的SOI MOSFET统一模型,模拟了FD与PD过渡区随辐照剂量的漂移．讨论了辐照引起FD与PD器件转化的原因,进一步分析了FD与PD器件的辐照效应．     

SOI MOSFET器件X射线总剂量效应研究

研究了以10keV X射线为辐照源对注氧隔离(SIMOX)SOI MOSFET器件进行辐照的总剂量效应.采用ARACOR 10keV X射线对埋氧层加固样品与未加固的对比样品在开态和传输门态两种辐照偏置下进行辐照,分析了器件的特性曲线,并计算了SOI MOS器件前栅与寄生背栅晶体管辐照前后的阈值电压的漂移.实验结果表明,加固样品的抗辐射性能优越,且不同的辐照偏置对SOI MOSFET器件的辐照效应产生不同的影响.     

非规则栅结构PD CMOS/SOI器件SPICE模型参数分析

针对抗辐照设计中特殊非规则条栅栅结构的CMOS/SOI器件,分析其SPICE模型参数,对源漏电阻、电容、体接触电阻等其他模型参数作出调整,建立非标准器件的完整精确模型.设计制作了多种不同非标准栅结构的PD CMOS/SOI 晶体管,并采用新的SPICE模型参数来模拟这些器件.模拟数据和试验数据具有很好的一致性,证明所建立的模型具有较高精度,适合抗辐照电路设计应用.     

采用CoSi_2SALICIDE结构CMOS/SOI器件辐照特性的实验研究

讨论了CoSi2SALICIDE结构对CMOS/SOI器件和电路抗γ射线总剂量辐照特性的影响.通过与多晶硅栅器件对比进行的大量辐照实验表明,CoSi2SALICIDE结构不仅可以降低CMOS/SOI电路的源漏寄生串联电阻和局域互连电阻,而且对SOI器件的抗辐照特性也有明显的改进作用.与多晶硅栅器件相比,采用CoSi2SALICIDE结构的器件经过辐照以后,器件的阈值电压特性、亚阈值斜率、泄漏电流、环振的门延迟时间等均有明显改善.由此可见,CoSi2SALICIDE技术是抗辐照加固集成电路工艺的理想技术之一.     

采用CoSi2 SALICIDE结构CMOS/SOI器件辐照特性的实验研究

讨论了CoSi2SALICIDE结构对CMOS/SOI器件和电路抗γ射线总剂量辐照特性的影响.通过与多晶硅栅器件对比进行的大量辐照实验表明,CoSi2SALICIDE结构不仅可以降低CMOS/SOI电路的源漏寄生串联电阻和局域互连电阻,而且对SOI器件的抗辐照特性也有明显的改进作用.与多晶硅栅器件相比,采用CoSi2 SALICIDE结构的器件经过辐照以后,器件的阈值电压特性、亚阈值斜率、泄漏电流、环振的门延迟时间等均有明显改善.由此可见,CoSi2SALICIDE技术是抗辐照加固集成电路工艺的理想技术之一.     

SOI器件的增强短沟道效应模型

为了探索SOI器件总剂量辐照后阈值电压漂移量和沟道长度的关系,利用器件模拟软件ISE TCAD,对不同沟道长度的PDSOI NMOS管进行了总剂量辐照模拟.模拟结果表明,随着沟道长度的减小,背沟道MOS管阈值电压漂移越来越大,并且漂移量和辐照偏置密切相关,称此效应为SOI器件的增强短沟道效应.以短沟道效应理论为基础对此效应的机理进行了解释,并以短沟道效应模型为基础对此效应提出了一个简洁的阈值电压漂移模型,通过对ISE模拟结果进行曲线拟合对所提出的模型进行了验证.     

Modeling the I-V characteristics of fully depleted submicrometerSOI MOSFET's

In this paper, an analytic current-voltage model for submicrometer fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is presented. This model takes into account the source/drain series resistances which can be especially high in thin film SOI devices. The effect of drain induced conductivity enhancement is also included, which is important for submicrometer channels. The model is verified by comparison to measured SOI I-V characteristics. Good agreement is obtained for SOI film thicknesses ranging from 40 to 220 nm and effective channel lengths down to 0.25 μm     

薄膜全耗尽SOI短沟道MOSFET准二维电流模型

本文在分析薄膜全耗尽SOI器件特殊物理效应的基础上,建立了可细致处理饱和区工作特性的准二维电流模型。该模型包括了场效应载流子迁移率、速度饱和以及短沟道效应等物理效应,可以描述薄膜全耗尽SOI器件所特有的膜厚效应、正背栅耦合(背栅效应)等对器件特性的影响,并且保证了电流、电导及其导数在饱和点的连续性。将模型模拟计算结果与二维器件数值模拟结果进行了对比,在整个工作区域(不考虑载流子碰撞离化的情况下)二者吻合得很好。     

Analysis of floating body induced transient behaviors in partiallydepleted thin film SOI devices

Emphasis toward manufacturability of thin film SOI devices has prompted more attention on partially depleted devices. In this paper, drain current transients in partially depleted SOI devices due to floating-body effects are investigated quantitatively. A one-dimensional analytical model is developed to predict the transient effect and MEDICI simulation is performed to confirm the model. With the model, the amount of the turn-on current enhancement and the turn-off current suppression are calculated. The transient characteristics can be used in investigating the quality of the SOI materials by determining the carrier lifetime. The impact of the transient effect on the device parameter extraction is described     

Deep submicrometer double-gate fully-depleted SOI PMOS devices: aconcise short-channel effect threshold voltage model using a quasi-2Dapproach

This paper reports a concise short-channel effect threshold voltage model using a quasi-2D approach for deep submicrometer double-gate fully-depleted SOI PMOS devices. By considering the hole density at the front and the back channels simultaneously, the analytical threshold voltage model provides an accurate prediction of the short-channel threshold voltage behavior of the deep submicrometer double-gate fully-depleted SOI PMOS devices as verified by 2D simulation results. The analytical short-channel effect threshold voltage model can also be useful for SOI NMOS devices     

Modeling of thermal behavior in SOI structures

Several physics-based analytical steady-state heat flow models for silicon-on-insulator (SOI) devices are presented, offering approaches at different levels of accuracy and efficiency for prediction of temperature profiles induced by power dissipated in SOI MOSFETs. The approaches are verified with the rigorous device simulation based on the energy transport model coupled with the heat flow equation. The models describe the one-dimensional temperature profile in the silicon film of SOI structure and two-dimensional heat flow in FOX, accounting for heat loss to the substrate via BOX and FOX, heat loss to (or gain from) interconnects, and heat exchanges between devices. These models are applied to investigate thermal behavior in single SOI devices and two-device SOI structures.     

A New Approach for SOI Devices Small-Signal Parameters Extraction

SOI devices are frequently used nowadays in the RF and HF field. Design of complex SOI integrated circuits involves a prior detailed analog simulation, that can only be performed through accurate SOI active components models. We are interested here in linear operation modeling; we test new methods for small-signal parameters determination, suitable for a conventional MOSFET high-frequency model and somewhat inspired from methods applied to MESFET technology. In this paper, we deal mainly with extrinsic parameters, for which we obtain reliable estimation on a large frequency range. Our finally adopted extraction procedure takes closely into account the model topology, which reflects the device electrical behavior. We completely describe the procedure, from measurements to the extracted equivalent circuit simulation, without having to optimize parameters and with a straightforward extrinsic elements extraction.     

Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model

The methodology of modeling and simulation of environmentally induced faults in radiation hardened SOI/SOS CMOS IC’s is presented. It is realized at three levels: CMOS devices – typical analog or digital circuit fragments – complete IC’s. For this purpose, a universal compact SOI/SOS MOSFET model for SPICE simulation software with account for TID, dose rate and single event effects is developed. The model parameters extraction procedure is described in great depth taking into consideration radiation effects and peculiarities of novel radiation-hardened (RH) SOI/SOS MOS structures. Examples of radiation-induced fault simulation in analog and digital SOI/SOS CMOS LSI’s are presented for different types of radiation influence. The simulation results show the difference with experimental data not larger than 10–20% for all types of radiation.     

Simulation of SOI devices and circuits using BSIM3SOI

A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with L_eff below 0.2 μm     

An analytical fully-depleted SOI MOSFET model considering theeffects of self-heating and source/drain resistance

In this paper, we present a new and analytical drain current model for submicrometer SOI MOSFET's applicable for circuit simulation. The model was developed by using a two-dimensional (2-D) Poisson equation, and considering the source/drain resistance and the self-heating effect. Using the present model, we can clearly see that the reduction of drain current with the parasitic series resistance and self-heating effect for typical SOI devices. We also can evaluate the impact of series resistance and self-heating effects. The accuracy of the presented model has been verified with the experimental data of SOI MOS devices with various geometries     

Moderate inversion in SOI MOSFET's with grain boundaries

Our previous model for the effects of grain boundaries on the strong-inversion (linear region) conductance of silicon-on-insulator (SOI) MOSFET's is extended to account for moderate inversion. The extension, which is supported by measurements of laser-recrystallized devices, predicts a nearly exponential dependence for the conductance on the (front) gate voltage that is controlled by the grain boundaries.