Single-switch 3φ PWM low harmonic rectifiers

Existing 3φ AC-DC low-harmonic rectifiers are costly and require complex control schemes to minimize input current harmonics. Introduced here are two new classes of low cost 3φ AC-DC high power factor/low harmonic controlled rectifiers. These are derived from parent DC-DC converter topologies containing boost-type inputs and buck-type inputs. With a single active switch in addition to the diode bridge rectifier, the converters are capable of drawing a high-quality input current waveform naturally at nearly unity power factor. Thus, a simple 3φ AC-DC high power factor rectifier is obtained. Two algorithms are introduced in this paper for constructing a 3φ AC-DC high-quality rectifier. These algorithms depend on the simple switched-mode boost-type input converter and buck-type input converter modified by an input filter. For most known DC-DC converters which belong to these classes, there are corresponding 3φ AC-DC high power factor topologies, which use the same number of transistors and use six additional fast diodes. Analytical and simulation results are supplied to demonstrate the validity of the concept     

Robust control of power-factor-correction rectifiers with fast dynamic response

This paper proposes a new robust control technique for single-phase boost high-power-factor rectifiers. The proposed circuit significantly improves the dynamic response of the converter to load steps without the need of a high crossover frequency of the voltage loop, so that a low distortion of the input current is easily achieved. A 250-W power-factor-correction rectifier with the proposed control scheme has been designed and implemented, validating the concept both analytically and experimentally.     

A novel robust harmonic injection method for single-switchthree-phase discontinuous-conduction-mode boost rectifiers

This paper describes a new robust low-cost harmonic-injection method for single-switch three-phase discontinuous-conduction-mode (DCM) boost rectifiers. In the proposed method, a periodic voltage is injected in the control circuit to vary the duty cycle of the rectifier switch within a line cycle so that the fifth-order harmonic of the input current is reduced to meet the IEC555-2 requirement. Since the injected voltage signal, which is proportional to the inverted AC component of the rectified three-phase line-to-line input voltages, is employed, the injected duty-cycle variations are naturally synchronized with the three-phase line-to-neutral input voltages. In addition, the injected harmonic signal naturally contains desirable higher order harmonics, such as sixth, twelfth, eighteenth, etc., which are more effective in improving total harmonic distortions (THDs) than harmonic-injection methods based on the sixth-order harmonic only     

Design of digital controllers for multivariable stochastic systems

A new approach for designing controllers for randomly disturbed interactive multivariable systems is proposed. This is based on an extension of the inverse-Nyquist-array method and the minimum variance control strategy for single-input/single-output systems.     

Power factor preregulators with improved dynamic response

An improved control strategy of standard power factor preregulators (PFPs) is proposed which allows fast output voltage response while maintaining a high power factor. This is obtained by compensating for the intrinsic low-frequency output voltage ripple, thus allowing a higher bandwidth of the output voltage control loop. This method does not require additional sensing, but only a multiplier and simple analog circuitry, and works well with a universal input voltage range. Experimental tests on a boost power converter with average current control confirm the validity of the approach     

Genetic tuning of digital PID controllers

The techniques of genetic algorithms are proposed as an alternative means of tuning digital PID controllers. This use of genetic algorithms is particularly attractive because the same basic approach can always be readily used, even in the case of digital PID controllers for complex multivariable plants with highly interactive dynamics.<>     

Frequency selective digital predistortion for harmonic rejection

In recent wireless communications, spectrally flexible transmissions such as carrier aggregation and cognitive radio pose severe challenges for the high-efficient radio-frequency power amplifier (PA) design. The non-linear characteristics of PAs may yield substantial unwanted emissions that can violate the emission limits, thus interfere with other communication systems within the frequency vicinity. Furthermore, in frequency-division duplexing systems, if the unwanted emissions happen to fall into the intended receiver band, it may cause severe receiver desensitisation. In this paper, we present a novel digital predistortion (DPD) technique based on a frequency selective architecture, which is aimed at reducing the unwanted harmonic emissions at any pre-specified frequency and linearising the fundamental signal at the same time. The method can simplify the predistortion structure compared with the whole spurious suppression DPD method and thus reduce the computational complexity of the predistortion process. Furthermore, the identification of the DPD coefficients is based on a breeding particle swarm optimisation algorithm, which can enhance the calculation flexibility as well accelerate the convergence speed compared with traditional gradient methods. Both simulation and measurement results demonstrate sufficient spur suppression at the target frequency.     

Analysis of the dynamic and steady-state performance ofCockcroft-Walton cascade rectifiers

The analysis of Cockcroft-Walton cascade rectifiers for static and dynamic conditions, based on digital simulations, is presented. Steady-state and transient currents and voltages on any component can be calculated through simulation. The influence of the voltage source impedance (generally inductive), in the overall performance, is shown to be very important. Experimental results are presented to validate the analysis     

Fast current control for low harmonic distortion at low switchingfrequency

The structure of the current control loop of an induction machine drive determines decisively the dynamic performance of the overall system. Fast current control is a prerequisite for dynamic decoupling between the torque and the flux commands. Standard solutions are well established for drives in the low- and medium-power ranges. The low switching frequency of high-power pulsewidth modulation inverters calls for a tradeoff in controller design between the low harmonic losses and torque ripple in the steady state on one hand, and fast dynamic response during the transients on the other. The problem is developed in detail. A variable-structure approach is proposed as the solution     

A high-speed multiplexer-based fine-grain pipelined architecture for digital fuzzy logic controllers

Design and implementation of a high-speed multiplexer-based fine-grain pipelined architecture for a general digital fuzzy logic controller has been presented. All the operators have been designed at gate level. For the multiplication, a multiplexer-based modified Wallace tree multiplier has been designed, and for the division and addition multiplexer-based non-restoring parallel divider and multiplexer-based Manchester adder have been used, respectively. To further increase the processing speed, fine-grain pipelining technique has been employed. By using this technique, the critical path of the circuit is broken into finer pieces. Based on the proposed architecture, and by using Quartus II 9.1, a sample two-input, one-output digital fuzzy logic controller with eight rules has been successfully synthesised and implemented on Stratix II field programmable gate array. Simulations were carried out using DSP Builder in the MATLAB/Simulink tool at a maximum clock rate of 301.84 MHz.     

Dielectric response function of breakdown plasma in silicon-controlled rectifiers

The real and imaginary parts of the dielectric constant of the plasma in silicon-controlled rectifier was studied as functions of frequency from 0.3 to 30 MHz for different injection levels of the current. The relaxation time was estimated to vary from 40 to 25 ns from lower injection levels to higher injection levels. The results also exhibit a nonlinear dependence of damping constant and plasma frequency on the injection level.     

Simple method of designing suboptimal dynamic controllers for discrete linear systems

A difference equation representation for suboptimal dynamic controllers enables the use of a simple design algorithm for discrete systems.     

Active antenna for improved efficiency and reduced harmonic radiation

Harmonic suppressed active antenna integrated with power amplifier yields improved efficiency, higher output power and reduced harmonic radiation from transmitter front end. This paper presents different harmonic suppression techniques of active antenna integrated with power amplifier. This paper also proposes and demonstrates novel PBG engineered structures to suppress higher order harmonics of integrated active antenna.     

Design of digital differentiators for low frequencies

Optimal, maximally accurate digital differentiators (DDS) are derived for the low-frequency range. Exact coefficients used in the proposed DDs can be readily computed from explicit formulas, whereas the optimal (minimas RE) DDs require and optimization program to derive the coefficients. The lower the frequency of differentiation, the better is the performance of the proposed differentiators, making them suitable for many typical applications     

A maximally flat group delay recursive digital filter with improved passband magnitude response

A technique is proposed for the design of a recursive digital filter with maximally flat responses in both magnitude and group delay. In comparison to the previous designs [1]-[3], the magnitude and group delay always show smooth responses no matter what the difference is in the polynomial degrees of the numerator and denominator.     

Short seeking by multirate digital controllers for computation saving with initial value adjustment

Multirate control has been proposed to reduce the real-time computation in hard disk drive (HDD) servo systems. It has been showed that computation can be saved greatly without performance degradation by using a multirate controller for track following. This paper proposes a novel method for short seeking control based on multirate track following control and initial value adjustment. This method, which uses the same multirate controller and the same servo structure as track following, adjusts the initial values of the track following controller for short seeking. Real-time computation is greatly saved in two aspects: 1) computation is saved by multirate scheme, and 2) initial value adjustment of the feedback controller makes the use of the feed-forward controller and reference trajectory unnecessary. Simulation and experimental results verify the effectiveness of the proposed method.     

Low-voltage BiCMOS dynamic minimum circuit using a parallelcomparison algorithm for fuzzy controllers

The authors present a low-voltage BiCMOS dynamic minimum circuit using a parallel comparison algorithm for VLSI implementation of fuzzy controllers. Using low-voltage BiCMOS dynamic circuits and a parallel comparison algorithm, a four-4-bit-input minimum circuit designed, based on a 1μm BiCMOS technology, shows a 9.5ns comparison time, which is a ×2.5 improvement in speed as compared to that based on CMOS technology     

BiCMOS dynamic minimum circuit using a parallel comparison algorithm for fuzzy controllers

A BiCMOS dynamic minimum circuit using a parallel comparison algorithm for the VLSI implementation of fuzzy controllers is presented. Using BiCMOS dynamic circuits and a parallel comparison algorithm a four 4-bit-input minimum circuit, designed based on a 2 mu m BiCMOS technology shows a 7.4 ns comparison time, which is a *3 improvement in speed as compared with the CMOS circuit. In addition, this circuit has an expansion capability for realising large-scale minimum circuits.<>     

Verification of fixed-point digital controllers using direct and delta forms realizations

The extensive use of fixed-point digital controllers demands a growing effort to prevent design errors that appear in the discrete-time domain. The present article describes a novel verification methodology, which employs bounded model checking (BMC) based on satisfiability modulo theories (SMT) to verify the occurrence of the design errors, because of the finite word-length (FWL) format, in fixed-point digital controllers. Here, the performance realizations of the digital controllers realizations that use delta operators are compared to those that use traditional direct forms. The experimental results show that the delta-form realization substantially reduces the digital controllers’ fragility when compared to the direct-form realization. Additionally, the proposed methodology can be very effective and efficient to verify real-world digital controllers, where conclusive results are obtained in nearly 98 % of the benchmarks.     

一种正交数字下变频器的高效改进结构

针对传统正交数字下变频器结构计算效率低,首先介绍一种基于混频器后X的改进方法,该方法只能使得计算效果提高1/2N,接着在此基础上利用多相滤波法对混频器后置法进行进一步改进,从而大大减少了数字下变频器的运算量,使得计算效率提高了K倍.最后对上述各种正交数字下变频方法进行算法仿真和计算效率分析对比,结果表明经过混频器后置法与多相滤波法综合改进后的数字正交下变频算法计算效率高,实现效果良好.