A new technique for measuring MOSFET inversion layer mobility

An experimental technique for accurately determining both the inversion charge and the channel mobility μ of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V_DS over a wide range of voltages (V_DS=20-100 mV). The resulting μ(V_GS) curves for different V_DS show no drastic mobility roll-off at V _GS near V_TH. This suggests that the roll-off seen in the mobility data extracted using the split C- V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering     

A semi-empirical model for the field-effect mobility ofhydrogenated polycrystalline-silicon MOSFETs

The quantitative relationship between field-effect mobility (μ _FE) and grain-boundary trap-state density (N_t ) in hydrogenated polycrystalline-silicon (poly-Si) MOSFETs is investigated. The focus is on the field-effect mobility in MOSFETs with N_t 1×10² cm^-2. It is found that reducing N_t to as low as 5×10¹¹ cm^-2 has a great impact on μ_FE. MOSFETs with the N_t of 4.2×10¹¹ cm^-2 show an electron mobility of 185 cm²/V-s, despite a mean grain size of 0.5 μm. The three principal factors that determine μ_FE, namely, the low-field mobility, the mobility degradation factor, and the trap-state density N_t are clarified     

Polysilicon thin-film transistors with channel length and widthcomparable to or smaller than the grain size of the thin film

Poly-Si thin-film transistors (TFTs) with channel dimensions (width W, and length L) comparable to or smaller than the grain size of the poly-Si film were fabricated and characterized. The grain size of the poly-Si film was enhanced by Si ion implantation followed by a low-temperature anneal and was typically 1 to 3 μm in diameter. A remarkable improvement was observed in the device characteristics as the channel dimensions decreased to W=L =2 μm. On the other hand, TFTs with submicrometer channel dimensions were characterized by an extremely abrupt switching in their I_D versus V_GS characteristics. The improvement was attributed to a reduction in the effect of the grain boundaries and to the effect of the device's floating body     

Characteristics of field-induced-drain (FID) poly-Si TFTs with highon/off current ratio

The characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) with a field-induction-drain (FID) structure using an inversion layer as a drain are investigated. The FID structure not only reduces the anomalous leakage current, but also maintains a high on current. An off current of 1.5 pA/μm and an on/off current ratio of 10⁷ (V_d=10, V_g =-20 V) are successfully obtained. These characteristics result from good junction characteristics between the p channel and n⁺ inversion layer. Reducing the threshold voltage of the FID region allows a simple circuit configuration for the FID TFTs     

High performance poly-Si TFTs fabricated using pulsed laserannealing and remote plasma CVD with low temperature processing

Key technologies for fabricating polycrystalline silicon thin film transistors (poly-Si TFTs) at a low temperature are discussed. Hydrogenated amorphous silicon films were crystallized by irradiation of a 30 ns-pulsed XeCl excimer laser. Crystalline grains were smaller than 100 nm. The density of localized trap states in poly-Si films was reduced to 4×10¹⁶ cm^-3 by plasma hydrogenation only for 30 seconds. Remote plasma chemical vapor deposition (CVD) using mesh electrodes realized a good interface of SiO ₂/Si with the interface trap density of 2.0×10¹⁰ cm^-2 eV^-1 at 270°C. Poly-Si TFTs were fabricated at 270°C using laser crystallization, plasma hydrogenation and remote plasma CVD. The carrier mobility was 640 cm²/Vs for n-channel TFTs and 400 cm²/Vs for p-channel TFTs. The threshold voltage was 0.8 V for n-channel TFTs and -1.5 V for p-channel TFTs. The leakage current of n-channel poly-Si TFTs was reduced from 2×10^-10 A/μm to 3×10^-13 A/μm at the gate voltage of -5 V using an offset gate electrode with an offset length of 1 μm     

Electrical properties of Si p+-n junctions for sub-0.25μm CMOS fabricated by Ga FIB implantation

p⁺-n junction diodes for sub-0.25-μm CMOS circuits were fabricated using focused ion beam (FIB) Ga implantation into n-Si (100) substrates with background doping of N_b=(5-10)×10 ¹⁵ and N_b⁺=(1-10)×10¹⁷ cm^-3. Implant energy was varied from 2 to 50 keV at doses ranging from 1×10¹³ to 1×10¹⁵ cm^-2 with different scan speeds. Rapid thermal annealing (RTA) was performed at either 600 °C or 700°C for 30 s. Diodes fabricated on N_b⁺ with 10-keV Ga⁺ exhibited a leakage current (^I_R) 100× smaller than those fabricated with 50-keV Ga⁺. Tunneling was determined to be the major current transport mechanism for the diodes fabricated on N_b⁺ substrates. An optimal condition for I_R on N_b⁺ substrates was obtained at 15 keV/1×10¹⁵ cm^-2. Diodes annealed at 600°C were found to have an I_R 1000× smaller than those annealed at 700°C. I-V characteristics of diodes fabricated on N_b substrates with low-energy Ga⁺ showed no implant energy dependence. I-V characteristics were also measured as a function of temperature from 25 to 200°C. For diodes implanted with 15-keV Ga ⁺, the cross-over temperatures between I_diff and I_g-r occurred at 106°C for N_b ⁺ and at 91°C for N_b substrates     

Electrical properties of low-temperature pyrolytic SiO2on InP

The first application of a new technique (SiH₄+O₂ at 83-330°C and 2-12 torr) for deposition of SiO₂ on InP is reported. SiO₂ deposited at 150-330°C has breakdown strength of 8-10 MV/cm, resistivity >10¹⁵ Ωcm, and refractive index of 1.45-1.46 comparable to thermal SiO ₂ grown at 1100°C. C/V measurements on Al/SiO₂/InP MIS structures suggest that very low temperature oxides (90-100°C) have the best interfacial properties     

Circuit performance of CMOS technologies with silicon dioxide andreoxidized nitrided oxide gate dielectrics

The circuit performance of CMOS technologies with silicon dioxide (SiO₂) and reoxidized nitrided oxide (RONO) gate dielectrics over the normal regime of digital circuit operation, i.e. V_GS⩽5 V and B_DS⩽5 V, is discussed. The simulation of a simple CMOS inverter has shown that the SiO₂ inverter consistently outperforms the RONO inverter over temperatures ranging from 300 to 100 K. This can be attributed mainly to the significantly lower μ_p (hole mobility) of RONO p-channel devices. At 300 K, μ_p(RONO) is 14-8% smaller than μ_p(SiO₂) over the entire range of gate biases, while μ_n(RONO) (electron mobility of n-channel RONO devices) is also smaller than μ_n(SiO₂) and reaches only 96% of μ_n(SiO₂) at V_GS=5 V. At 100 K, μ_n(RONO)/μ_n (SiO₂) at V_GS=5 V is increased to 1.10, however, μ_p(RONO)/μ_p(SiO₂) at V_GS=5 V is degraded to 0.59. The dependence of circuit performance on the supply voltage has also been evaluated for the RONO and SiO₂ inverters     

Temperature dependence of common-emitter I-V andcollector breakdown voltage characteristics in AlGaAs/GaAs andAlInAs/GaInAs HBT's grown by MBE

Temperature-dependent measurements from 25 to 125°C have been made of the DC I-V characteristics of HBTs with GaAs and In_0.53Ga_0.47As collector regions. It was found that the GaAs HBTs have very low output conductance and high collector breakdown voltage BV_CEO>10 V at 25°C, which increases with temperature. In striking contrast, the In_0.53Ga_0.47As HBTs have very high output conductance and low BV_CEO~2.5 V at 25°C, which actually decreases with temperature. This different behavior is explained by the >10⁴ higher collector leakage current, I_CO, in In_0.53Ga_0.47As compared to GaAs due to bandgap differences. It is also shown that device self-heating plays a role in the I-V characteristics     

Si/a-Si:H heterojunction microwave bipolar transistors with cut-offfrequencies ft above 5 GHz

The fabrication of a silicon heterojunction microwave bipolar transistor with an n⁺ a-Si:H emitter is discussed, and experimental results are given. The device provides a base sheet resistance of 2 kΩ/□ a base width 0.1 μm, a maximum current gain of 21 (V_CE=6 V, I_c=15 mA), and an emitter Gummel number G _E of about 1.4×10¹⁴ Scm^-4. From the measured S parameters, a cutoff frequency f_t of 5.5 GHz and maximum oscillating frequency f_max of 7.5 GHz at V_CE=10 V, I_c=10 mA are obtained     

New hot-carrier degradation mode in PMOSFETs with W gate electrodes

Hot-carrier degradation of W gate PMOSFETs, which are surface-channel devices because of the work function of W, has been investigated in comparison with polycide (WSi_x/n⁺ poly-Si) ones. In W gate PMOSFETs, transconductance g_m and threshold voltage V_th decrease on the drain avalanche hot-carrier (DAHC) stress, and Δg_m /g_m0 and ΔV_th become minimum at V_G≅V_D/2. By using the charge-pumping technique, it is found that, after stressing at the same stress condition, the interface state density of W gate devices is about 10 times larger than that of polycide ones but the densities of trapped electrons are almost equal. These results indicate that the difference of hot-carrier degradation between W and polycide gate devices is mainly caused by the difference of the interface state density     

High-frequency InP/InGaAs double heterojunction bipolar transistorson Si substrate

Self-aligned high-frequency InP/InGaAs double heterojunction bipolar transistors (DHBTs) have been fabricated on a Si substrate. A current gain of 40 was obtained for a DHBT with an emitter dimension of 1.6 μm×19 μm. The S parameters were measured for various bias points. In the case of I_C=15 mA, f _T was 59 GHz at V_CE=1.8 V, and f _max was 69 GHz at V_CE=2.3 V. Due to the InP collector, breakdown voltage was so high that a V_CE of 3.8 V was applied for I_C=7.5 mA in the S-parameter measurements to give an f_T of 39 GHz and an f_max of 52 GHz     

Effects of localized interface defects caused by hot-carrier stressin n-channel MOSFETs at low temperature

Hot-carrier stressing was carried out on 1-μm n-type MOSFETs at 77 K with fixed drain voltage V_d=5.5 V and gate voltage V_g varying from 1.5 to 6.5 V. It was found that the maximum transconductance degradation ΔG_m and threshold voltage shift ΔV_t, do not occur at the same V_g. As well, ΔK_t is very small for the V_g <V_d stress regime, becomes significant at V_g≈V_d, and then increases rapidly with increasing V_g, whereas ΔG_m has its maximum maximum in the region of maximum substrate current. The behavior is explained by the localized nature of induced defects, which is also responsible for a distortion of the transconductance curves and even a slight temporary increase in the transconductance during stress     

Amorphous silicon/silicon carbide superlattice avalanchephotodiodes

An a-Si/SiC:H superlattice avalanche photodiode (SAPD) has been successfully fabricated on an ITO/glass substrate by plasma-enhanced chemical vapor deposition. The room-temperature electron and hole impact ionization rates, α and β, have been determined for the a-Si/SiC:H superlattice structure by photocurrent multiplication measurements. The ratio α/β is 6.5 at a maximum electric field of 2.08×10⁵ V/cm. Avalanche multiplications in the superlattice layer yields an optical gain of 184 at a reverse bias V_R=20 V and an incident light power P_in=5 μW. An LED-SAPD photocouple exhibited a switching time of 4.5 μs at a load resistance R-1.8 kΩ     

Collector-assisted operation of micromachined field-emitter triodes

The field at the tip of a field emitter triode can be expressed by E=βV_g+_γV _c, where V_g and V_c the gate and collector voltages, respectively. For small gate diameters and tips below or in the plane of the gate and/or large tip-to-collector distances, _γV_c<<βV _g. The-device is operated in the gate-induced field emission mode and the corresponding I-V_c curves are pentode-like. By increasing the gate diameter and/or recessing the gates from the tips, collector-assisted operation can be achieved at reasonable collector voltages. Results are presented for two devices with gate diameters of 3.6 and 2.0 μm. By obtaining γ at different emitter-to-collector distances, I-V_c and transconductance g_m-V_g curves are calculated and compared with experimental results. It is shown that as a consequence of collector-assisted operation, the transconductance of a device can be increased significantly     

Inverted thin-film transistors with a simple self-aligned lightlydoped drain structure

The I-V characteristics of inverted thin-film transistors (TFT) are studied. A simple lightly doped drain (LDD) structure is utilized to control the channel electric field at the drain junction and to improve the performance of the TFTs. The LDD region is self-aligned to the channel and the source/drain regions. It is created by a spacer around an oxide mask which exclusively defines the channel length L_ch. Experimental data show that the leakage current, subthreshold swing SS, saturation current, and on/off current ratio of the inverted TFTs are closed related to L_ch, L_LDD, the drain bias, gate voltage, and LDD dose. With a gate deposited at low temperature, a saturation current of ~1.25 μA at 5 V and a leakage current of ~0.03 pA per micrometer of channel width were achieved. The current ratio therefore exceeds seven orders of magnitude, with an SS of 380 mV/decade. At 3.3 V, the current ratio is ~7×10⁶     

DIBL in short-channel NMOS devices at 77 K

Detailed experimental and two-dimensional numerical simulation results on drain-induced barrier lowering (DIBL) versus channel length at 300 and 77 K in short-channel NMOS devices are presented. It is found that by decreasing the temperature from 300 to 77 K. DIBL in NMOS devices with effective channel lengths (L) from 0.5 to 2.0 μm is improved for the range of L<0.6 μm and L>1.2 μm, but is worse for L between 0.6 and 1.2 μm. The new version of the two-dimensional device numerical simulation program MINIMOS 4.0, which includes device modeling at cryogenic temperatures, was used to investigate this unique characteristic. The measured DIBL characteristics can be explained physically as the transition from surface DIBL through the subsurface DIBL to the bulk DIBL or punchthrough effect at 300 K, but almost a surface DIBL for the whole range of channel length variation at 77 K. Design considerations for the channel doping profile for low-temperature operation based on keeping the same DIBL and V_TH as required for room-temperature operation are briefly discussed     

Temperature sensitivity of phase-matched second-harmonic generationin LiIO3

Measurements were made of the temperature dependence (between 23 and 65°C) of the phase-matching angle &thetas;_pm for type I frequency doubling of 1064-nm laser light in lithium iodate (LiIO₃). The measured value of d&thetas;_pm/dT is -14.7±1 μrad/°C, which corresponds to a thermal sensitivity β_T =0.24±0.02 cm^-1/°C for this process. Also calculated is a value of d&thetas;_pm/dT using experimentally determined thermooptic data available in the literature. The calculated value of d&thetas;_pm/dT is -31±18 μrad/°C using literature values of n and dn/dT for LiIO₃. The extreme sensitivity of the calculated value of d&thetas;_pm/dT to small errors in the thermooptic coefficients may be the reason for this discrepancy     

Modeling of nonhyperbolic sine I-Vcharacteristics in poly-Si resistors

Poly-Si resistors with an unimplanted channel region (and with n-type source/drain regions) can exhibit a nonhyperbolic sine (non-sinh) I-V characteristic at low V_DS and an activation energy which is not simply decreasing monotonically with increasing V_DS. These phenomena are not explained by conventional poly-Si resistor models. To describe these characteristics, a self-consistent model which includes the effects of a reverse-biased diode at the drain end is presented. Numerical simulation results show excellent agreement with experiment in regard to the shape of the I -V characteristic and of the effective activation energy as a function of V_DS     

Polysilicon emitter p-n-p transistors

In-situ boron-doped polysilicon has been used to form the emitter in p-n-p transistors. Various polysilicon deposition conditions, interface preparation treatments prior to deposition, and post-deposition anneals were investigated. Unannealed devices lacking a deliberately grown interfacial oxide gave effective emitter Gummel numbers G_E of 7-9×10^-12s cm^-4 combined with emitter resistances R_E of approximately 8 μΩcm². Introduction of a chemically grown interfacial oxide increased G_E to 2×10 ¹⁴s cm^-4, but also raised R_E by a factor of three. Annealing at 900°C following polysilicon deposition raised G_E values for transistors lacking deliberate interfacial oxide to approximately 6×10¹³s cm^-4, but had little effect of G_E for devices with interfacial oxide. Both types of annealed devices gave R_E values in the range 1-2 μΩcm²