Process and device performance of 1 µm-channel n-well CMOS technology

The process and device performance of 1 µm-channel n-well CMOS have been characterized in terms of substrate resistivities of 40 and 10 Ω.cm, substrate materials with and without an epitaxial layer, n-well surface concentrations ranging from5 times 10^{15}to4 times 10^{16}cm^-3, n-well depths of 3, 4, and 5 µm, channel boron implantation doses from2 times 10^{11}to1.3 times 10^{12}cm^-2, and effective channel lengths down to 0.6 µm. The deeper n-well more effectively improved the short-channel effects in p-channel MOSFET's having lower n-well surface concentrations. The impact-ionization current of the 0.9 µm n-channel MOSFET started to increase at a drain voltage of 5.2 V, while that of the 0.6 µm p-channel MOSFET did not increase until the drain voltage exceeded 12 V. Minimum latchup trigger current was observed when the output terminal of an inverter was driven over the power supply voltage. This minimum latchup trigger current was improved about 25 to 35 percent by changing the n-well depth from 3 to 5 µm and was further improved about 35 to 75 percent by using a substrate resistivity of 10 Ω.cm instead of 40 Ω.cm. The epitaxial wafer with a substrate resistivity of 0.008 Ω.cm improved the minimum latchup trigger current by more than 40 mA. It was estimated from the inverter characteristics that the effective mobility ratio between surface electrons and holes is about 1.4 at effective channel lengths of 1.0 µm for p-channel MOSFET's and 1.4 µm for n-channel MOSFET's. The optimized 1 µm-channel n-well CMOS resulted in a propagation delay time of 200 ps with a power dissipation of 500 µW and attained a maximum clock frequency of 267 MHz in a static ÷ 4 counter. The deep-trench-isolated CMOS structure was demonstrated to break through the scaling effect drawback of n-well depth and surface concentration.     

Analytical model and characterization of small geometry MOSFET's

Electrical characteristics of small geometry p-channel and n-channel MOSFET's are characterized based on an analytical model that includes short-channel, narrow-channel, and carrier-velocity-saturation effects. Theoretical results on threshold voltage, threshold-voltage shift by a substrate bias voltage, and drain current are in good agreement with the experimental results over wide ranges of channel lengths from 1 to 9 µm and channel widths from 2 to 14 µm. A comparison of the electrical characteristics of MOSFET's with and without field implantation leads to the conclusion that the field implantation is the main cause of the narrow-channel-width effect on threshold-voltage increase and drain-current degradation. The carrier-velocity-saturation effect starts to appear at the 3-µm channel length for the n-channel device and at 1 µm for the p-channel device under 5-V operation. According to the theoretical analysis of a 1-µm-channel inverter circuit, a CMOS inverter has superior noise immunity with 1.4 to 2.0 times larger driving-current capability in a load MOS device and requires 9 percent less area than a 1-µm n-channel enhancement/depletion inverter.     

Comparison of characteristics of n-channel and p-channel MOSFET's for VLSI's

A comparison of device characteristics of n-channel and p-channel MOSFET's is made from the overall viewpoint of VLSI construction. Hot-carrier-related device degradation of device reliability, as well as effective mobility, is elaborately measured for devices having effective channel lengths of 0.5-5 µm. From these experiments, it is found that hot-electron injection due to impact ionization at the drain, rather than "lucky hot holes," imposes a new constraint on submicrometer p-channel device design, though p-channel devices have been reported to have much less trouble with hot-carrier effects than n-channel devices do. Additionally, p-channel devices are found to surpass n-channel devices in device reliability in that they have a highest applicable voltage BVDCthat is more than two times as high as for n-channel devices. It is also experimentally confirmed that the effective hole mobility approaches the effective electron mobility when effective channel lengthL_{eff} < 0.5µm. These significant characteristics of p-channel devices imply that p-channel devices have important advantages over n-channel devices for realization of sophisitcated VLSI's with submicrometer dimensions. It is also shown that hot holes, which may create surface states or trap centers, play an important role in such hot-carrier-induced device degradation as transconductance degradation.     

Characteristics of a 1.2-µm CMOS technology fabricated on an RF-heated zone-melting recrystallized SOI

0.7-5-µm CMOSFET's were fabricated on SOI which was recrystallized using an RF-heated zone-melting recrystallization (RFZMR) method. The leakage currents of n-channel MOSFET's having gate lengths between 5- and 0.7-µm range between 10^-14and 10^-12A/µm and show no dependence on channel length. Those of the p-channel MOSFET's were 10^-14-10^-12A/µm when the gate lengths were longer than 1.2 µm, and increased when the gate lengths were shorter than 1.0 µm. The propagation delay time of the CMOSFET inverter was 0.13 ns per stage at a supply voltage of 3.5 V.     

Flicker noise in CMOS transistors from subthreshold to stronginversion at various temperatures

Flicker noise is the dominant noise source in silicon MOSFET's. Even though considerable amount of work has been done in investigating the noise mechanism, controversy still exists as to the noise origin. In this paper, a systematic study of flicker noise in CMOS transistors from twelve different fabricators is reported under various bias conditions corresponding to the gate voltage changing from subthreshold to strong inversion, and the drain voltage changing from linear to saturation regions of operation. The measurement temperature was varied from room temperature down to 5 K. Experimental results consistently suggest that 1/f noise in n-channel devices is dominated by carrier-density fluctuation while in p-channel devices the noise is mainly due to mobility fluctuation     

CMOS-Compatible bipolar and I2L technology using three-level epitaxial layers for analog/Digital VLSI's

A high-performance bipolar/I²L/CMOS on-chip technology has been developed. To combine all devices, three-level epitaxial layers Were used. Both n-p-n and lateral p-n-p bipolar transistors, and p-channel MOSFET's were fabricated on the top level epitaxial layer. I²L and n-channel MOSFET's were fabricated on the middle and bottom levels, respectively. Using a thin epitaxial layer and simultaneously reducing the level of regions for n-channel MOSFET's and bi-polar isolation grooves, the process sequence was designed to be as simple as possible. Bipolar n-p-n transistors with a maximum cutoff frequency of 5 GHz, I²L circuits having 40-MHz maximum toggle frequency, and CMOS devices operating at a minimum propagation delay time of 300 ps/gate were developed compatibly. This technology has feasibility for application to multifunctional analog/digital VLSI's.     

Process and device performance of submicrometer-channel CMOS devices using deep-trench isolation and self-aligned TiSi2technologies

According to our scaling study, a deeper n-well allows for a lower n-well surface concentration with improved short-channel effects in submicrometer-channel PMOS-FET's. The deep n-well, however, requires a large space between n- and p-channel devices. This large space limits the integration density in scaled bulk CMOS VLSI's. The deep-trench isolation combined with an epitaxial layer resolves this drawback with significantly improved device-to-device isolation and latchup susceptibility. The 6-µm-deep with 2-µm-wide deep trench is etched in the epitaxial layer and is refilled with 1500 Å of thermal silicon-dioxide film and 2 µm of polysilicon film. The sheet resistances of N⁺and P⁺diffusion and N⁺-doped polysilicon layers were reduced to 3 to 4 Ω/□ by using the self-aligned TiSi2layer with an oxide sidewall spacer. As a result of this low sheet resistance, the saturation drain current of submicrometer n- and p-channel MOSFET's was improved approximately 33 to 37 percent compared with conventional MOSFET's without the self-aligned TiSi2layer. The 0.5-µm-channel CMOS devices using the deep-trench isolation with an epitaxial layer and the self-aligned TiSi2layer operated at a propagation delay time of 140 ps with a power dissipation of 1.1 mW per inverter and attained a maximum clock frequency of 400 MHz in a static / 4 counter without suffering from latchup even at the latchup trigger current of 200 mA.     

A derivative method to determine a MOSFET's effective channel length and width electrically

A new method is presented to determine the channel-width reduction ΔW and the channel-length reduction ΔL in CMOS transistors. By measuring the transconductance of certain sets of n-channel and p-channel MOSFET's biased at low gate and drain voltages in the linear region, a set of derived first-order linear equations is used iteratively to solve for ΔW and ΔL. The results agree with the process observations of fabricated CMOS devices.     

TaSi2gate for VLSI CMOS circuits

It is shown, that lateral shrinkage of 2-µm CMOS devices and reduction of the gate oxide thickness to about 20 nm is significantly facilitated by replacing the n⁺-poly-Si or polycide gates by TaSi2. Due to its higher work function, TaSi2allows the simultaneous reduction of the channel doping in the n-channel and the charge compensation in the p-channel without changing the threshold voltages. Thus compared with n⁺-poly-Si gate n-channel transistors substrate sensitivity and substrate current are reduced, and low-level breakdown strength is raised. In p-channel transistors, the subthreshold current behavior and UT(L)-dependence are improved. Consequently, the channel length of both n- and p-channel transistors can be reduced by about 0.5 µm without significant degradation. The MOS characteristics Nss, flatband and threshold voltage stability, and dielectric strength appear similar for TaSi2and n+-poly Si gate transistors.     

Effects of ionizing radiation on SOI/CMOS Devices fabricated in zone-melting-recrystallized Si films on SiO2

The effects of ionizing radiation on SOI/CMOS devices fabricated in zone-melting-recrystallized Si films on SiO2-coated Si substrates have been investigated as a function of the negative bias applied to the substrate during irradiation and measurement. For these devices, which have a thin gate oxide 10 nm thick, the optimum substrate bias is - 5 V. For total doses up to 10⁷rad(Si), with this bias they exhibit low subthreshold leakage currents (<0.2-pA/µm channel width), small threshold voltage shifts (<-0.18 V for n-channel devices and <-0.46 V for p-channel devices) and very little transconductance degradation (<5 percent).     

Si-gate CMOS devices on a Si/CaF2/Si structure

Si-gate CMOS inverter chains and 1/8 dynamic frequency dividers have been fabricated on a Si/CaF2/Si structure. A high-quality heteroepitaxial Si/CaF2/Si structure was formed by successive molecular-beam epitaxy of CaF2and Si. Transistors have been fabricated with an improved CMOS process that prevents crystal degradation during the fabrication process as much as possible. The maximum effective mobilities are about 570 and 240 cm²/V . s for n-channel and p-channel transistors, respectively. The inverter chain with an effective channel length of 2.0 µm has a delay time per gate of 360 ps. A maximum operating frequency of 300 MHz is obtained in the divider with an effective channel length of 2.5µm at a supply voltage of 5 V. These results indicate that the Si/CaF2/Si structure has potential for the fabrication of high-speed silicon-on-insulator devices.     

Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q_inv/L²––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V_GS and V_DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.     

Effects of ionizing radiation on short-channel thin-Oxide (200-Å) MOSFET's

The effect of ionizing radiation on n-channel MOSFET's with channel lengths ranging from 1.0 to 9.3 µm and gate oxides 200 Å thick was investigated. Irradiation to 10⁶rads(Si) resulted in an increased shift of the threshold voltage as the channel length was shortened with those devices having channel lengths 2 µm continuing to operate in the enhancement mode.     

Advanced thin-film silicon-on-sapphire technology: microwavecircuit applications

This paper reviews the prospects of thin-film silicon-on-sapphire (TFSOS) CMOS technology in microwave applications in the 1-5 GHz regime and beyond and presents the first demonstration of microwave integrated circuits based on this technology, MOSFET's optimized for microwave use, with 0.5-μm optically defined gate lengths and a T-gate structure, have f_t values of 25 GHz (14 GHz) and f_max values of 66 GHz (41 GHz) for n-channel (p-channel) devices and have noise figure values below 1 db at 2 GHz, some of the best reported performance characteristics of any silicon-based MOSFET's to date. On-chip spiral inductors exhibit quality factors above ten. Circuit performance compares favorably with that of other CMOS-based technologies and approach performance levels similar to those obtained by silicon bipolar technologies. The results demonstrate the significant potential of this technology for microwave applications     

1/f noise and radiation effects in MOS devices

An extensive comparison of the 1/f noise and radiation response of MOS devices is presented. Variations in the room-temperature 1/f noise of unirradiated transistors in the linear regime of device operation correlate strongly with variations in postirradiation threshold-voltage shifts due to oxide trap charge. A simple number fluctuation model has been developed to semi-quantitatively account for this correlation. The 1/f noise of irradiated n-channel MOS transistors increases during irradiation with increasing oxide-trap charge and decreases during postirradiation positive-bias annealing with decreasing oxide-trap charge. No such correlation is found between low-frequency 1/f noise and interface-trap charge. The noise of irradiated p-channel MOS transistors also increases during irradiation, but in contrast to the n-channel response, the p-channel transistor noise magnitude increases during positive-bias annealing with decreasing oxide-trap charge. A qualitative model involving the electrostatic charging and discharging of border traps, as well as accompanying changes in trap energy, is developed to account for this difference in n- and p-channel postirradiation annealing response. The correlation between the low-frequency 1/f noise of unirradiated devices and their postirradiation oxide-trap charge suggests noise measurements can be used as a nondestructive screen of oxide trap charge related failures in discrete MOS devices and for small scale circuits in which critical transistors can be isolated. It also suggests that process techniques developed to reduce radiation-induced-hole trapping in MOS devices can be applied to reduce the low-frequency 1/f noise of MOS circuits and devices. In particular, reducing the number of oxygen vacancies and vacancy complexes in the SiO ₂ can significantly reduce the 1/f noise of MOS devices both in and outside a radiation environment     

The impact of scaling laws on the choice of n-channel or p-channel for MOS VLSI

Circuit requirements of scaled devices based on noise margin, parameter variation, parasitic resistance and drift velocity saturation lead to non-constant field scaling, which predict a maximum in performance as devices are scaled. This maximum occurs at a smaller length for p-channel than for n-channel for a given scaling rule, and causes the performance of the two to approach each other at L<0.3µm. The p-channel devices under these conditions are shown to be 100x less effected by hot carriers induced reliability problems than n-channel devices.     

A study of noise in surface and buried channel SiGe MOSFETs with gate oxide grown by low temperature plasma anodization

A study is made of noise in p- and n-channel transistors incorporating SiGe surface and buried channels, over the frequency range f=1 Hz–100 kHz. The gate oxide is grown by low temperature plasma oxidation. Surface n-channel devices are found to exhibit two noise components namely 1/f and generation–recombination (GR) noise. It is shown that the 1/f noise component is due to fluctuations of charge in slow oxide traps whilst bulk centers located in a thin layer of the semiconductor close to the channel, give rise to the GR noise component. The analysis of the noise data gives values for the density D_ot of the oxide traps in the SiGe and Si nMOSFETs of the order 1.8×10¹² and 2.5×10¹⁰ cm⁻² (eV)⁻¹, respectively. The density D_GR of the bulk GR centres is equal to 3×10¹⁰ cm⁻² in both the SiGe and Si devices. The electron and hole capture cross-sections for these centres as well as their energy level and their depth below the oxide/semiconductor interface are also the same in the devices of both types. This suggests that those GR centers are of the same nature in all devices studied. p-Channel devices show different behaviour with only a 1/f noise component apparent in the data over the same frequency range. Buried SiGe channel and Si control devices exhibit quite low and similar slow state densities of the order low to mid 10¹⁰ cm⁻² (eV)⁻¹ whereas surface p-channel devices show even higher slow state densities than n-channel counterparts. The Hooge noise characterized by the Hooge coefficient _H=2×10⁻⁵ is also detected in some buried p-channel SiGe devices.     

Measurements of residual defects and 1/f noise in ion-implanted p-channel MOSFET's

This paper describes the measurements of excess noise and residual defects of extremely low concentrations (<1 × 10⁹cm^-2) in ion-implanted p-channel MOSFET's. The activation energy and the density of the residual defects after high-temperature annealing were measured using a transient capacitance technique. The test FET's were ion-implanted with fluences of 5 × 10¹¹to 4 × 10¹²using³¹p⁺,¹¹B⁺, or²⁸Si⁺species. A post-implant anneal was carried out in an N2or an Ar ambient for 20 min at various temperatures. For¹¹B⁺-implanted MOSFET's after annealing above 1000°C, a high residual defect concentration was observed near the conduction band edge; whereas after annealing the defect density as a result of²⁸Si⁺or³¹p⁺implantation was equal to that of control MOSFET's. The density-of-state data agree with the equilibrium measurements of excess (1/f) noise power. The excess noise was measured as a function of the drain current. The distribution of1/fnoise power versus potential minimum of holes in the equilibrium condition is similar to that of interface state density. In nonequilibrium operation, a reduction of excess noise was achieved owing to the presence of buried channel created by ion implant.     

Low-frequency noise in near-fully-depleted TFSOI MOSFETs

Low-frequency (1/f) noise in near-fully-depleted Thin-Film Silicon-On-Insulator (TFSOI) CMOS transistors designed for sub-l-V applications is investigated in the subthreshold region, linear region, and saturation region of operation for the first time. The noise in these surface-channel devices is composed of a bias invariant 1/f component and a bias dependent generation-recombination (G/R) component that becomes enhanced in the subthreshold region of operation for both n- and p-channel MOSFETs. Results presented in this letter are consistent with the noise being dominated by a number fluctuation model. These results demonstrate that the bias independent 1/f noise spectrum of the n-channel TFSOI MOSFET is comparable to the 1/f noise level found in conventional bulk silicon submicron CMOS fabrication processes     

Submicrometer poly-Si CMOS fabrication with low-temperature laserdoping

The laser doping process for submicrometer CMOS devices with leakage currents as low as 10^-12 A/μm for both n-channel and p-channel devices is discussed. The I-V characteristics are comparable to those of poly-Si devices fabricated using ion implantation and high-temperature annealing processes. The laser-induced melting of predeposited impurity doping (LIMPID) process was used to fabricate submicrometer polycrystalline-Si CMOS devices. This process uses a very low temperature, so no dopant atom can diffuse along the grain boundaries in the solid region. The use of stacked Al/SiO₂ films as a protection layer made it possible to reduce the leakage current from several tens of picoamperes per micrometer to 1 pA/μm