15-GHz fully integrated nMOS switches in a 0.13-/spl mu/m CMOS process

Two fully integrated nMOS switches have been demonstrated at 15 GHz in a 0.13-/spl mu/m CMOS foundry process. One incorporates on-chip LC impedance transformation networks (ITNs) while the second one does not. The switches with and without ITNs achieve the same 1.8-dB insertion loss at 15 GHz, but 21.5 and 15 dBm input P/sub 1dB/, respectively. The degradation of insertion loss due to use of ITNs is compensated by reducing the mismatch loss caused by the bond pad parasitics. The switch without ITNs is suitable for 3.1-10.6 GHz ultra-wide-band (UWB) applications. The switch with ITNs has /spl sim/5 dB worse isolation than the switch without. The difference is due to the larger transistor size of the switch with ITNs, which introduces lower parasitic impedance path between Tx/Rx ports and antenna port.     

A High Power CMOS Switch Using Substrate Body Switching in Multistack Structure

A novel high power CMOS RF switch using the substrate body switching technique in a multistack structure is designed, implemented, and characterized in a standard 0.18- triple-well CMOS process. One of the stacked devices in the receive side has a body switch at the bulk port in order to provide high power handling capability to the transmit switch side without compromising insertion loss to the receiver switch. The body switch connected to the bulk port at one of the receiver switches turns on in mode to minimize leakage current into path. In the meanwhile, that switch turns off in mode so that the bulk port can have body floating to reduce leakage current to substrates. Experimental data show that the switch using the body-switching technique has 1 dB of 31.5 dBm that is 2.5 dB higher than the one using the body floating technique. Insertion loss is 1.5 dB at 1.9 GHz in the transmit switch and 1.8 dB in the receiver switch. Isolation is less than 30 dB for switch and 20 dB for switch at 1.9 GHz.     

Ultra-Compact High-Linearity High-Power Fully Integrated DC–20-GHz 0.18-μm CMOS T/R Switch

A fully integrated ultra-broadband transmit/receive (T/R) switch has been developed using nMOS transistors with a deep n-well in a standard 0.18-mum CMOS process, and demonstrates unprecedented insertion loss, isolation, power handling, and linearity. The new CMOS T/R switch exploits patterned-ground-shield on-chip inductors together with MOSFET's parasitic capacitances to synthesize artificial transmission lines, which result in low insertion loss over an extremely wide bandwidth. Negative bias to the bulk or positive bias to the drain of the MOSFET devices with floating bulk is used to reduce effects of the parasitic diodes, leading to enhanced linearity and power handling for the switch. Within dc-10, 10-18, and 18-20 GHz, the developed CMOS T/R switch exhibits insertion loss of less than 0.7, 1.0, and 2.5 dB and isolation between 32-60, 25-32, and 25-27 dB, respectively. The measured 1-dB power compression point and input third-order intercept point reach as high as 26.2 and 41 dBm, respectively. The new CMOS T/R switch has a die area of only 230 mumtimes250 mum. The achieved ultra-broadband performance and high power-handling capability, approaching those achieved in GaAs-based T/R switches, along with the full-integration ability confirm the usefulness of switches in CMOS technology, and demonstrate their great potential for many broadband CMOS radar and communication applications     

A 0.13 μm CMOS UWB RF Transmitter with an On‐Chip T/R Switch

This paper presents a fully integrated 0.13 μm CMOS MB‐OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low‐pass filter, a variable gain amplifier, a voltage‐to‐current converter, an I/Q up‐mixer, a differential‐to‐single‐ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 μm CMOS technology. The fabricated transmitter shows a ?3 dB bandwidth of 550 MHz at each sub‐band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.     

A 900 MHz Zero‐IF RF Transceiver for IEEE 802.15.4g SUN OFDM Systems

This paper presents a 900 MHz zero‐IF RF transceiver for IEEE 802.15.4g Smart Utility Networks OFDM systems. The proposed RF transceiver comprises an RF front end, a Tx baseband analog circuit, an Rx baseband analog circuit, and a ΔΣ fractional‐N frequency synthesizer. In the RF front end, re‐use of a matching network reduces the chip size of the RF transceiver. Since a T/Rx switch is implemented only at the input of the low‐noise amplifier, the driver amplifier can deliver its output power to an antenna without any signal loss; thus, leading to a low dc power consumption. The proposed current‐driven passive mixer in Rx and voltage‐mode passive mixer in Tx can mitigate the IQ crosstalk problem, while maintaining 50% duty‐cycle in local oscillator clocks. The overall Rx‐baseband circuits can provide a voltage gain of 70 dB with a 1 dB gain control step. The proposed RF transceiver is implemented in a 0.18 μm CMOS technology and consumes 37 mA in Tx mode and 38 mA in Rx mode from a 1.8 V supply voltage. The fabricated chip shows a Tx average power of ?2 dBm, a sensitivity level of ?103 dBm at 100 Kbps with , an Rx input P_1dB of ?11 dBm, and an Rx input IP3 of ?2.3 dBm.     

A wide locking range and low Voltage CMOS direct injection-locked frequency divider

A low voltage and wide locking range injection-locked frequency divider using a standard 0.18-/spl mu/m complementary metal oxide semiconductor (CMOS) process is presented. The wide locking range and the low-voltage operation are performed by adding an injection nMOS between the differential outputs of the divider that contains on-chip transformers which result in positive feedback loops to swing the output signals above the supply and below the ground potential. This dual-swing capability maximizes the carrier power and achieves low-voltage performance. The measurement results show that at the supply voltage of 0.75-V, the divider free-running frequency is 2.02 GHz, and at the incident power of 0 dBm the locking range is about 1.49 GHz (36.88%), from the incident frequency 3.27 to 4.64GHz.     

21.5-dBm power-handling 5-GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs)

This paper reports a 21.5-dBm power-handling 5-GHz transmit/receive CMOS switch utilizing the depletion-layer-extended transistor (DET), which possesses high effective substrate resistance and enables the voltage division effect of the stacked transistor configuration to work in the CMOS switch. Furthermore, low insertion losses of 0.95 and 1.44 dB are accomplished at 5 GHz in the transmit and receive modes, respectively, with the benefit of the insertion-loss improvement effects in the DET. At the same time, high isolations of more than 22 dB were obtained at 5 GHz in the transmit and receive modes with the adoption of the shunt/series type circuit.     

$Ka$-Band Low-Loss and High-Isolation Switch Design in 0.13-$mu{hbox {m}}$ CMOS

This paper presents designs and measurements of Ka-band single-pole single-throw (SPST) and single-pole double-throw (SPDT) 0.13-CMOS switches. Designs based on series and shunt switches on low and high substrate resistance networks are presented. It is found that the shunt switch and the series switch with a high substrate resistance network have a lower insertion loss than a standard designs. The shunt SPST switch shows an insertion loss of 1.0 dB and an isolation of 26 dB at >35 GHz. The series SPDT switch with a high substrate resistance network shows excellent performance with 2.2-dB insertion loss and isolation at 35 GHz, and this is achieved using two parallel resonant networks. The series-shunt SPDT switch using deep n-well nMOS transistors for a high substrate resistance network results in an insertion loss and isolation of 2.6 and 27 dB, respectively, at 35 GHz. For series switches, the input 1-dB compression point (1P₁) can be significantly increased to with the use of a high substrate resistance design. In contrast, of shunt switches is limited by the self-biasing effect to 12 dBm independent of the substrate resistance network. The paper shows that, with good design, several 0.13- CMOS designs can be used for state-of-the-art switches at 26-40 GHz.     

Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance

A low insertion-loss single-pole double-throw switch in a standard 0.18-/spl mu/m complementary metal-oxide semiconductor (CMOS) process was developed for 2.4- and 5.8-GHz wireless local area network applications. In order to increase the P/sub 1dB/, the body-floating circuit topology is implemented. A nonlinear CMOS model to predict the switch power performance is also developed. The series-shunt switch achieves a measured P/sub 1dB/ of 21.3 dBm, an insertion loss of 0.7 dB, and an isolation of 35 dB at 2.4 GHz, while at 5.8 GHz, the switch attains a measured P/sub 1dB/ of 20 dBm, an insertion loss of 1.1 dB, and an isolation of 27 dB. The effective chip size is only 0.03 mm/sup 2/. The measured data agree with the simulation results well, including the power-handling capability. To our knowledge, this study presents low insertion loss, high isolation, and good power performance with the smallest chip size among the previously reported 2.4- and 5.8-GHz CMOS switches.     

Novel high-isolation FET switches

This paper describes novel high-isolation monolithic microwave/millimeter-wave integrated circuit (MMIC) field-effect transistor (FET) switches that have higher isolation characteristics than conventional switches without much insertion loss degradation. The newly developed switches consist of series/shunt FETs and T-shaped R-C-R circuit. Each FET switch utilizes the parasitic capacitive component of the FETs in the off-state to produce a band-rejection filter at the operating frequency. The design method of the newly proposed switches and their characteristics are described herein. With this method, the isolation characteristics are improved by more than 15 dB between 5.4 GHz and 6.4 GHz and more than 20 dB between 5.5 GHz and 6.1 GHz over conventional values     

2.06GHz～3.43GHz自校准频率综合器设计

提出了一种自校准频率综合器,通过采用开关电容阵列使该设计具有较低的相位噪声和较宽的调谐范围.自校准 控制回路的引入,使该综合器能根据输入参考频率,温度,分频比等参数自动调整开关阵列中开关的开启和关断,达到快速锁 定的目的.采用SMIC 0.18 μm CMOS工艺进行仿真,结果显示,频率综合器输出频率范围从2.06 G...     

A 0.8-dB insertion-loss, 17.4-dBm power-handling, 5-GHz transmit/receive switch with DETs in a 0.18-/spl mu/m CMOS process

An optimized single-pole double-throw (SPDT) transmit/receive (T/R) switch has been fabricated using depletion-layer-extended transistors (DETs) in a 0.18 /spl mu/m CMOS process. The switch features the highest performance to date of any switch using a CMOS process, of a 0.8 dB insertion-loss, 23 dB isolation and 17.4 dBm power-handling capability at 5 GHz. The low insertion-loss has been achieved with the effects of junction capacitance decrease and substrate resistance increase in the DET, the adoption of low-loss shielded-pads, and several layout optimizations. The high power-handling capability is owing to the combined effect of the adoption of the source/drain dc biasing scheme and the high substrate resistance in the DET.     

应用于高速信号传输系统的多路选择器

提出了一种能够传输高速信号的多路选择器,并为其设计了一种低失真、宽带模拟开关.所提出开关的栅源过驱动电压由nMOS和pMOS的开启电压之和决定,并能够确保输入变化时,开关的栅源电压与阈值电压之差(VGST)保持恒定,从而基本消除了体效应的影响.采用TSMC 0.18μm CMOS工艺,HSPICE仿真结果表明,输入信号在0.3～1.7V之间变化时,开关的VGST基本保持恒定,其-3dB带宽大于10GHz,当输入频率为1GHz时,其无杂散动态范围为67.11dB;开关的开启时间为2.98ns,关断时间为1.35ns,确保了多路选择器的break-before-make特性.该结构可应用于高速信号传输系统中.     

A low-voltage CMOS switch with a novel clock boosting scheme

There is a strong demand for an input switch in switched-capacitor circuits, covering rail-to-rail signal swing when low power-supply voltages are used. This brief proposes a novel clock-boosting scheme. The generated clock voltages of this new circuit are applied to a regular CMOS transmission gate to implement a simple and robust sampling switch when the supply voltages are very low. In this new approach, during the sampling phase, the gate-voltage of an nMOS switch is boosted up to V/sub dd/+k/spl middot/V/sub dd/, and the gate voltage of a pMOS switch is lowered to V/sub gnd/-k/spl middot/V/sub dd/, where k can be made programmable, and is usually smaller than 1. This allows sampling of the full signal swing, even when supply voltages are lower than |V/sub th/,p|+V/sub th/,n without applying extreme stress to the gate oxide of a transistor.     

A V-band front-end with 3-D integrated cavity filters/duplexers and antenna in LTCC technologies

This paper presents a compact system-on-package-based front-end solution for 60-GHz-band wireless communication/sensor applications that consists of fully integrated three-dimensional (3-D) cavity filters/duplexers and antenna. The presented concept is applied to the design, fabrication, and testing of V-band (receiver (Rx): 59-61.5 GHz, transmitter (Tx): 61.5-64 GHz) transceiver front-end module using multilayer low-temperature co-fired ceramic technology. Vertically stacked 3-D low-loss cavity bandpass filters are developed for Rx and Tx channels to realize a fully integrated compact duplexer. Each filter exhibits excellent performance (Rx: IL<2.37 dB, 3-dB bandwidth (BW) /spl sim/3.5%, Tx: IL<2.39 dB, 3-dB BW /spl sim/3.33%). The fabrication tolerances contributing to the resonant frequency experimental downshift were investigated and taken into account in the simulations of the rest devices. The developed cavity filters are utilized to realize the compact duplexers by using microstrip T-junctions. This integrated duplexer shows Rx/Tx BW of 4.20% and 2.66% and insertion loss of 2.22 and 2.48 dB, respectively. The different experimental results of the duplexer compared to the individual filters above are attributed to the fabrication tolerance, especially on microstrip T-junctions. The measured channel-to-channel isolation is better than 35.2 dB across the Rx band (56-58.4 GHz) and better than 38.4 dB across the Tx band (59.3-60.9 GHz). The reported fully integrated Rx and Tx filters and the dual-polarized cross-shaped patch antenna functions demonstrate a novel 3-D deployment of embedded components equipped with an air cavity on the top. The excellent overall performance of the full integrated module is verified through the 10-dB BW of 2.4 GHz (/spl sim/4.18%) at 57.45 and 2.3 GHz (/spl sim/3.84%) at 59.85 GHz and the measured isolation better than 49 dB across the Rx band and better than 51.9 dB across the Tx band.     

单刀双掷RF MEMS开关的研究与设计

介绍了一种基于横向金属接触的DC-5GHz单刀双掷RF MEMS开关的研究与设计．横向金属接触开关包括了一套有限的共面波导（FGCPW）传输线和左右摆动的悬臂梁．为了降低开启电压,设计了一种曲折型的折叠梁结构,通过理论分析与仿真实验验证了该结构的可行性,并利用MetalMUMPs工艺加以实现．测试结果显示,该开关在5GHz处的插入损耗为0．8dB,回波损耗大于20dB,隔离度为40dB．测得最低开启电压为33V．     

A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.     

Microwave switching with parallel-resonated GaAs FETS

The use of GaAs FETs as microwave switches is discussed, and the feasibility of such devices for applications requiring ultra low dc power consumption, low insertion loss, and bidirectionality is demonstrated. A discrete SPST switch consisting of two parallel-resonated single-gate GaAs FETs exhibited 0.5 db insertion loss with 25 db isolation at 8.5 GHz. The first monolithic SPDT switch incorporating parallel-resonated GaAs FETs is also reported.     

A Ring-Oscillator-Based Wide Locking Range Frequency Divider

This letter proposes a wide locking range injection locked frequency divider (ILFD) and describes the operation principle of the ILFD. The circuit is made of a dual band two-stage differential complementery metal–oxide–semiconductor (CMOS) ring oscillator and is based on MOS switches directly coupled to the differential outputs of the ring oscillator. The divide-by-two ILFD can provide wide locking range and the measurement results show that at the supply voltage of 1.8-V, the divider free-running frequencies are 1.36GHz and 2.3GHz, and at the incident power of 0dBm, the locking range is about 1.75GHz from the incident frequency 1.9GHz to 3.65GHz at low band and 2.55GHz from 2.95GHz to 5.5GHz at high band.     

High power DPDT antenna switch MMIC for digital cellular systems

In this paper, we propose two new types of dual-pole double-throw (DPDT) switch GaAs JFET monolithic microwave integrated circuits (MMICs) for digital cellular handsets. These ICs have the excellent characteristics of low insertion loss and high power handling capability, even with a low control voltage by stacking three JFETs with shallow V_p and using a novel bias circuit using p-n junction diodes. One DPDT switch IC has two shunt FET blocks and can achieve high isolation without external parts. An insertion loss less than 0.6 dB and isolation over 25 dB up to 2 GHz were achieved. P_1dB was about 35 dBm even with a control voltage of 0/3 V. Another DPDT switch IC utilizes parallel resonance of external inductors and parasitic capacitance between the drain and the source of the OFF-state FETs. By attaching 15 nH inductors, for example, the IC exhibited an insertion loss as low as 0.4 dB, an isolation of better than 40 dB at 1.5 GHz, a bandwidth of about 400 MHz for 20 dB isolation, and P_1dB of about 34 dBm with the 0/3 V control