Low-voltage and low-power circuit design for mixed analog/digitalsystems in portable equipment

This paper describes low-voltage and low-power (LV/LP) circuit design for both analog LSI's and digital LSI's which are used in mixed analog/digital systems in portable equipment. We review some LV/LP circuits used in digital LSI's, such as general logic gate, DSP, and DRAM, and others used in analog LSI's, such as operational amplifiers, video-signal processing circuits, A/D and D/A converters, filters, and RF circuits, along with a wide range of items used in recently developed LSI's. Since analog circuits have fundamental difficulties in reducing the operating voltage and the power consumption, in spite of recent progress in LV/LP circuit techniques, these difficulties will be a major issue for decreasing the total power consumption of some mixed analog/digital systems used in portable equipment     

An adjustment-free single-chip video signal processing LSI for VHSVCR's

The authors have developed an adjustment-free single-chip video signal processing large scale integration (LSI) for VHS VCR's. This LSI's adjustment-free system was realized by using automatic feedback loop circuits. The complementary high-speed switch circuits play an important role in this system. It was possible to realize the complementary high-speed switch circuits, because this LSI has been fabricated with 2 μm bipolar process. This paper describes how the LSI has succeeded in being adjustment-free on frequency modulation (FM) carrier frequency/deviation and output video signal amplitude     

1 V power supply, low-power consumption A/D conversion techniquewith swing-suppression noise shaping

A 1 V power supply and low-power consumption A/D conversion technique using swing-suppression noise shaping is proposed. This technique makes it possible to power the on chip A/D converter in digital LSI's directly by a one-cell battery, without a dc-dc converter. Experimental results indicated good performance for the RF-to-baseband analog interface of a digital cordless phone. The A/D converter, fabricated with a 0.5 μm CMOS process, operates on a 1 V power supply, has a 10 bit dynamic-range with a 384 ksps sampling speed and consumes only 1.56 mW     

An all-analog expandable neural network LSI with on-chipbackpropagation learning

This paper proposes an all-analog neural network LSI architecture and a new learning procedure called contrastive backpropagation learning. In analog neural LSI's with on-chip backpropagation learning, inevitable offset errors that arise in the learning circuits seriously degrade the learning performance. Using the learning procedure proposed here, offset errors are canceled to a large extent and the effect of offset errors on the learning performance is minimized. This paper also describes a prototype LSI with 9 neurons and 81 synapses based on the proposed architecture which is capable of continuous neuron-state and continuous-time operation because of its fully analog and fully parallel property. Therefore, an analog neural system made by combining LSI's with feedback connections is promising for implementing continuous-time models of recurrent networks with real-time learning     

3.5-Gb/s×4-ch Si bipolar LSI's for optical interconnections

The 3.5-Gb/s, 4-ch transmitter and receiver LSI's described here include a 5-to-1 multiplexer, a 1-to-5 demultiplexer, and analog PLL circuits that can generate high-speed clock (3.5 GHz) and retimed data. The chips make it possible to connect twenty pairs of 700-Mb/s electrical ports (14-Gb/s throughput) without any external elements even for the PLL. Both the transmitter and receiver LSI are 4.5-mm-square and are fabricated by a 40-GHz 0.5-μm Si bipolar process. The transmitter LSI dissipates 2.5 W, and the receiver LSI dissipates 3.6 W. Both have -4.5- and -2-V supply voltages     

A new polysilicon process for a bipolar device—PSA technology

A new polysilicon process has been developed to obtain high packing density, high speed, and low-power LSI's. The new process, called the polysilicon self-aligned (PSA) method is based on a new fabrication concept for dimensional reduction and does not require fine patterning and accurate mask alignment. For an application example of this new method, an emitter-coupled logic (ECL) gate with 0.6 ns delay time, 0.5 pJ power-delay product, and 6400 µm²gate area has been achieved. Futhermore, by introducing a polysilicon diode (PSD) and Schottky barrier diode (SBD) to the PSA method, a low-power Schottky-diode-transistor-logic (SDTL) gate with 1.6 ns delay time, 0.8 pJ power-delay product, and 2000-µm²gate area has been successfully developed.     

GaAs DCFL 2.5 Gbps 16-bit Multiplexer/Demultiplexer LSI's

GaAs 2.5 Gbps 16 bit MUX/DEMUX LSI's have been successfully developed. DCFL is employed as a basic gate in order to reduce the power dissipation. To avoid the speed degradation caused by using DCFL, various technologies such as 8×2(MUX)/2×8(DEMUX) data conversion processes, a Selector Merged Shift Register, clock overlapping, and a 0.7-μm BPLDD MESFET, have been introduced. Moreover the ECL I/O level interface and single power supply features make it easy to use MUX/DEMUX in optical communication systems. The maximum operating data rate is 3.2 Gbps for both LSI's, and the power dissipation of chips which operates with 2.5 Gbps are as low as 1.3 W for each MUX/DEMUX     

Process and device optimization of an analog complementary bipolarIC technology with 5.5-GHz fT pnp transistors

An analog complementary bipolar IC process has been developed featuring 9.0-GHz f_T npn and 5.5-GHz f_T pnp transistors. Process conditions for emitter, base, and collector of pnp transistors are optimized in order to achieve the best performance tradeoff between current gain, Early voltage, and cutoff frequency. With the optimized process conditions, the H_FE×V_A of pnp transistors is 350 V with f_T of 5.5 GHz and f_max of 8.5 GHz. These high performance pnp transistors have been integrated into an existing 9.0-GHz f_T npn bipolar process without introducing excessive additional process complexity and manufacturing costs. In addition, Schottky diodes, p-channel junction FET's and laser wafer trimmable precision NiCr resistors have been integrated into the process to enhance analog circuit design capability     

Schottky diode for bipolar LSI's consisting of an impurity-controlled Si substrate and Al(2%Si) electrode

Circuit design conditions of Schottky diodes have been investigated and the fabrication method for diodes suitable for the conditions has been proposed for applications to bipolar LSI's, such as ECL RAM and Schottky TTL. It has been found that the desired Schottky diode for bipolar LSI's is not an ideal device from the theoretical point of view. Desired built-in voltage, ideal factor, series resistance, and junction capacitance for the Schottky diode have been estimated, respectively, for the bipolar RAM and Schottky TTL. A proposed Schottky diode consists of an impurity-concentration-controlled     

GaAs LSI-directed MESFET's with self-aligned implantation for n+-layer technology (SAINT)

Self-aligned implantation for n⁺-layer technology (SAINT) has been developed for improvement in normally-off GaAs MESFET's to be used in LSI's. This technology has made it possible to arbitrarily control the spacing between the n⁺-implanted layer and gate contact by a dielectric lift-off process utilizing a multilayer resist with an undercut wall shape. SAINT FET's with a 1-µm gate length have above 200 mS/ mm transconductance in the normally-off region. The K value along the square-lawI - Vfitting has been improved by a factor of 3.4, compared to conventional FET's without the n⁺-layer. Thermal emission for carriers from the source n⁺-layer in the subthreshold region has been experimentally formulated. Threshold-voltage shift due to gate shortening for [011] gate FET's is definitely smaller than that for [011] gate FET's. The threshold-voltage standard deviations for [011] gate FET's with 2- and 1-µm gate lengths, obtained from a 6-mm × 9-mm area, are 9 and 34 mV, respectively. An E/D direct-coupled FET logics (DCFL) 15-stage ring oscillator with a 1-µm gate length shows a high switching speed of 45 ps/gate at a low supply voltage of 0.91 V.     

LSI's for digital signal processing

This paper describes high-performance CMOS LSI's for digital signal-processing (DSP) technology, such as digital filter, fast Fourier transform (FFT), discrete Fourier transform (DFT), and digital phase-locked loop (DPLL). First, DSP functions for communication use, functional blocks to compose DSP functions, and the types of arithmetic for LSI are discussed. It is explained that multiplier (MPL), variable-length shift register (VSR), and linear arithmetic processor (LAP) have been chosen as the most useful DSP LSI's. Device design for high-speed and low-power CMOS is described and its feasibility is shown as characteristics of propagation delay time at 430 ps and power delay product at 0.073 pJ. The 3-µm effective channel-length CMOS technology has been selected for the DSP LSI because of the high speed, 5 ns, in the case of two input NAND gates and high yield technology. The multiplier architecture is pipeline and uses the Two's-complement representative, the variable-length shift register uses the binary-select method, and the linear arithmetic processor uses the method of changing the outside connections for realization of DSP functions. Maximum operating frequency of these LSI's is more than 23 MHz at the 5-V source voltage. Power dissipation of a VSR, which has been lossy, is less than 250 mW in the 8-MHz operation. They have wider application to communication systems. High-speed CMOS technology is applied to the digital system equipment up to the second level of the PCM hierarchy.     

An 0.3-μm Si epitaxial base BiCMOS technology with 37-GHzfmax and 10-V BVceo for RF telecommunication

In this paper, a 0.3-μm BiCMOS technology for mixed analog/digital application is presented. A typical emitter area of this technology is 0.3 μm×1.0 μm. This technology includes high f _max of 37 GHz at the low collector current of 300 μA and high BV_ceo of 10 V NPN transistor, CMOS with L_eff=0.3 μm, and passive elements. By using the shallow and deep trench isolation technology and nonselective epitaxial intrinsic base, the C_jc can be reduced to 1.6 fF, which is the lowest value reported so far. As a results, we have managed to obtain the high f_max at the low current region and high BV _ceo concurrently. These features will contribute to the development of high-performance BiCMOS LSI's for various mixed analog/digital applications     

A complementary bipolar technology family with a VerticallyIntegrated PNP for high-frequency analog applications

Silicon complementary bipolar processes offer the possibility of realizing high-performance circuits for a variety of analog applications. This paper presents a summary of silicon complementary bipolar process technology reported in recent years. Specifically, an overview of a family of silicon complementary bipolar process technologies, called Vertically Integrated PNP (VIP^TMI) which have been used for the realization of high-frequency analog circuits is presented. Three process technologies, termed VIP-3, VIP-3H, and VIP-4H offer device breakdowns of 40, 85, and 170 V, respectively. These processes feature optimized vertically integrated bipolar junction transistors (PNPs) along with high performance NPN transistors with polycrystalline silicon emitters, low parasitic polycrystalline silicon resistors, and metal-insulator-polycrystalline silicon capacitors. Key issues and aspects of the processes are described. These issues include the polycrystalline silicon emitter optimization and vertical and lateral device isolation in the transistors. Circuit design examples are also described which have been implemented in these technologies     

A VLSI analog computer/digital computer accelerator

The design of a single-chip VLSI analog computer fabricated in a 0.25-/spl mu/m CMOS process is described. It contains 80 integrators, 336 other linear and nonlinear analog functional blocks, switches for their interconnection, and circuitry to enable the system's programing and control. The IC is controlled, programmed and measured by a PC via a data acquisition card. This arrangement has been used to simulate ordinary differential equations (ODEs), partial differential equations, and stochastic differential equations with moderate accuracy, significantly faster than a modern workstation. Techniques for using the digital computer to refine the solution from the analog computer are presented. Solutions from the analog computer have been used to accelerate a digital computer's solution of the periodic steady state of an ODE by more than 10/spl times/. The IC occupies 1 cm/sup 2/ and consumes 300 mW. An analysis has been done showing that the analog computer dissipates 0.02% to 1% of the energy of a general purpose digital microprocessor and about 2% to 20% of the energy of a digital signal processor, when solving the same differential equation.     

FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI's

Processing steps of FIPOS (Full Isolation by Porous Oxidized Silicon) technology and its application to LSI's are presented, FIPOS technology realizes a silicon-on-insulator structure, utilizing thick porous oxidized silicon and donors produced by proton implantation. New processing steps are proposed which provides small surface step and are suitable for LSI fabrication. Formation conditions of thick porous oxidized silicon are established by density control technique for porous silicon using a newly developed anodization system. CMOS devices are fabricated in isolated silicon layers and it is shown that the characteristics of n-channel and p-channel MOSFETS's are sufficient for application to CMOS LSI's. A FIPOS/CMOS logic array with 1.3K gate is successfully fabricated, which shows a higher speed and lower power dissipation than the gates fabricated by bulk CMOS technology. These results indicate that FIPOS technology is very useful for realizing high-performance CMOS LSI's.     

A Line Termination Circuit for Burst-Mode Digital Subscriber Loop Transmission

This paper describes a line termination circuit for burst-mode bidirectional digital subscriber loop transmission. It incorporates the most advanced LSI technology to obtain compactness, low cost, and high reliability. Two CMOS LSI's have been developed; one is a line termination LSI (LT) and another is a circuit termination LSI (CT). LT LSI adopts a novelRCactive filter-type equalizer and decision feedback bridged tap equalizer suitable for incorporation in LSI and provides high performance. By using these LSI's, a line termination circuit realizes a reach of over 5 km at 88 kbit/s bidirectional digital transmission. This paper describes each LSI and shows total performance characteristics in detail.     

A novel on-chip electrostatic discharge (ESD) protection withcommon discharge line for high-speed CMOS LSIs

A novel on-chip electrostatic discharge (ESD) protection for high-speed CMOS LSI's that operate at higher than 500 MHz has been developed. Introduction of a newly developed common discharge line (CDL) can completely eliminate the protection device influence on the inner circuit operation. This enables minimization of the I/O capacitance by shrinking the dimension of the output transistor, which also serves as a protection device in conventional devices. This new protection (CDL protection) was applied to a high-speed DRAM of which I/O pin capacitance specification is 2 pF. As a result, the ESD tolerance of 4 kV for the charged device model test, 4 kV for the human body model test, and 700 V for the machine model test were obtained. In addition, the DRAM data rate higher than 660 MHz at room temperature was achieved. The results show significant improvement for both ESD and the I/O capacitance, compared with the conventional structure     

Data-dependent logic swing internal bus architecture forultralow-power LSI's

A reduced-swing internal bus scheme is proposed for achieving ultralow-power LSI's. The proposed data-dependent logic swing bus (DDL bus) uses charge sharing between bus wires and an additional bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed bus is reduced to 1/16 that of a conventional bus when used for a 16-b-wide bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-μm CMOS process verify the low-power operation of the proposed bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V     

0.2-μm fully-self-aligned Y-shaped gate HJFET's with reducedgate-fringing capacitance fabricated using collimated sputtering andelectroless Au-plating

This paper reports on new fully-self-aligned gate technology for 0.2-μm, high-aspect-ratio, Y-shaped-gate heterojunction-FET's (HJFET's) with about half the external gate-fringing capacitance (C_f^rext) of conventional Y-shaped gate HJFET's. The 0.2-μm Y-shaped gate openings are realized by anisotropic dry-etching with stepper lithography and SiO₂ sidewall techniques instead of electron beam lithography. By introducing WSi-collimated sputtering and electroless gold-plating techniques for the first time, we have developed a high-aspect-ratio, voidless and refractory Y-shaped gate-electrode without the need for mask alignments. A fabricated 0.2-μm gate n-Al_0.2Ga_0.8As/In_0.2Ga_0.8As HJFET shows very small current saturation voltage of 0.25 V, marked gm _max of 631 mS/mm with 6-V gate-reverse breakdown voltage, and excellent threshold voltage uniformity of 9 mV. Also, the improved rf-performance such as f_T=71 GHz and f_max=120 GHz is realized even with the passivation for the high-aspect-ratio gate-structure with reduced C_f^rext. The developed technology based upon a fully-self-aligned and an all-dry-etching process provides higher performance and uniformity, thus it is very promising for high-speed and low-power-consumption digital and/or analog IC's/LSI's     

A 16×16 nonvolatile programmable analog vector-matrixmultiplier

In this paper, we present a 16×16 analog vector-matrix multiplier with analog electrically erasable and programmable read-only memories (EEPROMs) used as nonvolatile storage for the weight matrix values. Each weight matrix value is stored in an EEPROM transistor as a change of the threshold voltage, and the same EEPROM transistor is used for the multiplication by utilizing the square-law characteristic of the metal-oxide-semiconductor field-effect transistor. This allows a very simple circuit for the multiplier array with a size of about 1×1 mm². The vector-matrix multiplier has been fabricated in a 1,5-μm single-poly complementary metal-oxide-semiconductor/EEPROM technology and successfully tested