Reliability Modeling and Analysis of Fault-Tolerant Memories

A memory array reliability model is developed that can be applied to a wide range of memory organizations including random-access memories (RAM) and read-only memories (ROM). The model is particularly useful for computing the reliability of fault-tolerant memories that employ techniques such as hardware redundancy, error-correcting codes, and software error-correcting algorithms. The model accommodates the effect of faults masked by data. Reliability models that incorporate the array model are given for a simplex RAM, an N-modular-redundant RAM, a spared RAM, a single-error-correcting RAM, a multiple-error-correcting RAM, and a ROM. Reliability characteristics of these memories are compared. The results suggest that memories with error-correcting capability and spare bit-planes provide the best reliability. Memories with sparing at the array level are next best followed by NMR and simplex organizations. ROM reliability is shown to be more optimistic when masked faults are considered.     

Error Correction Schemes with Erasure Information for Fast Memories

Two error correction schemes are proposed for word-oriented binary memories that can be affected by erasures, i.e. errors with known location but unknown value. The erasures considered here are due to the drifting of the electrical parameter used to encode information outside the normal ranges associated to a logic 0 or a logic 1 value. For example, a dielectric breakdown in a magnetic memory cell may reduce its electrical resistance sensibly below the levels which correspond to logic 0 and logic 1 values stored in healthy memory cells. Such deviations can be sensed during memory read operations and the acquired information can be used to boost the correction capability of an error-correcting code (ECC). The proposed schemes enable the correction of double-bit errors based on the combination of erasure information with single-bit error correction and double-bit error detection (SEC-DED) codes or shortened (SEC) codes. The correction of single-bit errors is always guaranteed. Ways to increase the number of double-bit and triple-bit errors that can be detected by shortened SEC and SEC-DED codes are considered in order to augment the error correction capability of the proposed solutions.     

Comparison of Memory Chip Organizations vs Reliability in Virtual Memories

Random access memory organizations typically are chosen for maximum reliability, based on the operation of the memory box itself without concern for the remainder of the computing system. This had led to widespread use of the 1-bit-per-chip, or related organization which uses error correcting codes to minimize the effects of failures occurring in some basic unit such as a word or double word (32 to 64 bits). Such memory boxes are used quite commonly in paged virtual memory systems where the unit for protection is really a page (4K bytes), or in a cache where the unit for protection is a block (32 to 128 bytes), not a double word. With typical high density memory chips and typical ranges of failure rates, the 1-bit-per-chip organization can often maximize page failures in a virtual memory system. For typical cases, a paged virtual memory using a page-per-chip organization can substantially improve reliability, and is potentially far superior to other organizations. This paper first describes the fundamental considerations of organization for memory systems and demonstrates the underlying problems with a simplified case. Then the reliability in terms of lost pages per megabyte due to hard failures over any time period is analyzed for a paged virtual memory organized in both ways. Normalized curves give the lost pages per Mbyte as a function of failure rate and accumulated time. Assuming reasonable failure rates can be achieved, the page-per-chip organization can be 10 to 20 times more reliable than a 1-bit-per-chip scheme.     

用于低开销容错设计的存储部件可靠性评估研究

低开销容错技术是当前软错误研究领域的热点。为了对微处理器进行低开销容错保护,首先就需要对微处理器可靠性(即体系结构弱点因子AVF (Architectural Vulnerability Factor))进行准确评估。然而,现有的AVF评估工具的精确性和适用范围都受到不同程度的限制。该文以微处理器上的核心部件(即存储部件)作为研究对象,对AVF评估方法进行改进,提出了一种访存操作分析和指令分析相结合的AVF评估策略HAES (Hybrid AVF Evaluation Strategy)。该文将HAES融入到通用的模拟器中,实现了更精确和更通用的AVF评估框架。实验结果表明相比其它AVF评估工具,利用该文提出的评估框架得到的AVF平均降低22.6%。基于该评估框架计算得到的AVF更加精确地反映了不同应用程序运行时存储部件的可靠性,对设计人员对微处理器进行低开销的容错设计具有重要指导意义。     

Fault Leveling Techniques for Yield and Reliability Enhancement of NAND Flash Memories

Novel fault leveling techniques based on address remapping (AR) are proposed in this paper. We can change the logical-to-physical address mapping of the page buffer such that faulty cells within a flash page can be evenly distributed into different codewords. Therefore, the adopted ECC scheme can correct them effectively. Based on the production test or on-line BIST results, the fault bitmap can be used for executing the heuristic fault leveling analysis (FLA) algorithm and evaluating control words used to steer fault leveling. A new page buffer architecture suitable for address remapping is also proposed. According to experimental results, repair rate, yield, and reliability can be improved significantly with negligible hardware overhead.     

Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes

In this paper we propose memory protection architectures based on nonlinear single-error-correcting, double-error-detecting (SEC-DED) codes. Linear SEC-DED codes widely used for design of reliable memories cannot detect and can miscorrect lots of errors with large Hamming weights. This may be a serious disadvantage for many modern technologies when error distributions are hard to estimate and multi-bit errors are highly probable. The proposed protection architectures have fewer undetectable errors and fewer errors that are miscorrected by all codewords than architectures based on linear codes with the same dimension at the cost of a small increase in the latency penalty, the area overhead and the power consumption. The nonlinear SEC-DED codes are generalized from the existing perfect nonlinear codes (Vasil’ev codes, Probl Kibern 8:375–378, 1962; Phelps codes, SIAM J Algebr Discrete Methods 4:398–403, 1983; and the codes based on one switching constructions, Etzion and Vardy, IEEE Trans Inf Theory 40:754–763, 1994). We present the error correcting algorithms, investigate and compare the error detection and correction capabilities of the proposed nonlinear SEC-DED codes to linear extended Hamming codes and show that replacing linear extended Hamming codes by the proposed nonlinear SEC-DED codes results in a drastic improvement in the reliability of the memory systems in the case of repeating errors or high multi-bit error rate. The proposed approach can be applied to RAM, ROM, FLASH and disk memories.     

Detection?Correction Decoding for System Reliability

Error-correcting codes can be used in digital communication and storage for error control. A two-step decoding procedure is proposed for improving system performance when error correction is used. When applicable it should reduce the average decoding time or logic required for realization. Possible applications to faulty memory arrays and unit-to-unit data transmission are given.     

Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding

NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can be classified into data retention (DR) errors and program interference (PI) errors. DR errors are dominant if the data storage time is longer than 1 day and these errors can be reduced by refreshing the data. PI errors are dominant if the data storage time is less than 1 day and these errors can be handled by error control coding (ECC). In this paper we propose a combination of data refresh policies and low cost ECC schemes that are cognizant of application characteristics to address the errors in MLC NAND Flash memories. First, we use Gray code based encoding to reduce the error rates in the four subpages (MSB-even, LSB-even, MSB-odd, LSB-odd) of a 2-bit MLC NAND Flash memory. Next, we apply data refresh techniques where the refresh interval is a function of the program/erase (P/E) frequency of the application. We show that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint.     

Memories of light

The author briefly discusses both optical disc and magnetic media for recording data pointing out that they are complementary to each other. The author then describes the technology involved in write-once optical media and erasable optical recording     

Memories of tomorrow

With the promise of nonvolatility, practically infinite write endurance, and short read and write times, magnetic tunnel junction magnetic random access memory could become a future mainstream memory technology.     

Priority Based Error Correction Code (ECC) for the Embedded SRAM Memories in H.264 System

With aggressive supply voltage scaling, SRAM bit-cell failures in the embedded memory of the H.264 system result in significant degradation to video quality. Error Correction Coding (ECC) has been widely used in the embedded memories in order to correct these failures, however, the conventional ECC approach does not consider the differences in the importance of the data stored in the memory. This paper presents a priority based ECC (PB-ECC) approach, where the more important higher order bits (HOBs) are protected with higher priority than the less important lower order bits (LOBs) since the human visual system is less sensitive to LOB errors. The mathematical analysis regarding the error correction capability of the PB-ECC scheme and its resulting peak signal-to-noise ratio(PSNR) degradation in H.264 system are also presented to help the designers to determine the bit-allocation of the higher and lower priority segments of the embedded memory. We designed and implemented three PB-ECC cases (Hamming only, BCH only, and Hybrid PB-ECC) using 90 nm CMOS technology. With the supply voltage at 900 mV or below, the experiment results delivers up to 6.0 dB PSNR improvement with a smaller circuit area compared to the conventional ECC approach.     

Surface-Acoustic-Wave Random-Access Memories

An acoustic tapped-delay line (TDL) undermultiplexer control exhibits random-access-memory (RAM) capability; programmable time compression/expansion is achieved by controlling the difference between tap switching interval and intertap delay. A serial-in/parallel-out configuration can perform spectral compression of high input bandwidths, while requiring a single sampling operation to be performed, at the output data rate; dual properties are demonstrated by a parallel-in/serial-out organized RAM used for time compression. A new powerful N-phase configuration is discussed, which allows the intrinsic switching capability of multiplexers employed to be increased by N, while offering high dynamic range capability. The basic operation of the new technique is discussed, some theoretical aspects are investigated, and various effective configurations are described. In particular, the natural format of the time contracted/segmented output from a nonlinear convolver, asynchronously operated, is recovered; a clock-programmable bandpass filter is demonstrated, based on complementary time compression expansion. Extension to read-only memory (ROM) is briefly outlighted, with reference to frequency synthesis. Finally, processing of signals in basel and format is demonstrated using acoustic TDL's, via a simple modulation technique, which increases flexibility and the potential attraction of the new technique.     

一台DC，两种回忆

在数字化不断发展的今天，人们有更多的理由去关注生活本身的品质。如同我们用手中的相机去记录下家庭温馨生活的点滴，在拍摄的过程当中为家庭成员们带来更多的乐趣，彼此之间的关系更加亲密，而且可以让大家以后再回过头来，一起回忆过往的甜蜜，感悟与感恩生活的美好。     

几种新型非易失性存储器

本文简单介绍了铁电存储器、磁性随机存储器和相变存储器这三种比较有发展潜力存储器的原理、研究进展及存在的问题等.     

Optical Ring-Resonator Random-Access Memories

This paper examines the properties of optical resonator memory cells, in which a data bit is stored in a high- optical resonator. It is shown that resonator-based optical memories are ultimately limited by losses in the resonators, by the extinction ratio and chirp of the variable coupling medium that injects and extracts data into and out of the resonators, and by chirp on the input signal. Using a simple analytical model and accurate field-based simulations, we analyze the performance of a ring-resonator optical memory cell and compare this with the performance of slow light delay line buffer memories and complementary metal-oxide-semiconductor embedded dynamic random-access memory.     

半导体存储器走出阴霾,春光可待

半导体存储器一般是配置在ＰＣ内部的一种半导体芯 片,用于存储处理器运行时所需的指令和信息。它和硬盘的不同点之一,是大多半导体存储器易于挥发而丢失信息,需要电源不断充电以保持数据。它在半导体产品中占有重要地位,据世界半导体贸易统计协会（ＷＳＴＳ）统计,１９９９年是仅次于微芯片的第二大产品市场。 １．ＤＲＡＭ 需求强势,价格反弹 １９９５年存储器曾占ＩＣ市场份额的４２％,１９９９年降到２４．８％,２０００年预计可回升到２８．１％,而ＤＲＡＭ又占整个存储器市场的６０～７０％,因此,ＤＲＡＭ的兴衰对整个存储…