并行测试的测试调度及其控制

本文首先从理上比较严格的证明了测试调度问题是多项式可解的，提出了一种Ｏ（ｎ＾２）的最优测试调度策略。最后，阐述了一种测试调度的控制策略，使得多路转换器控制输入最少。     

分布式系统中的动态测试调度

本文提出了一种在分布式环境下电路的并行测试调度算法。文中采用了动态调度的策略,最大限度地提高了测试的并行度。这种动态测试调度不同于静态调度在测试以前对各处理机分配任务,而是在测试过程中逐步形成测试方案,充分利用了处理机的空闲时间。     

一种改进的基于遗传算法的测试调度方法

提出了一种改进的基于遗传算法的So C测试调度方法,通过该方法可以有效地优化测试总线的划分,合理调度各个IP核以实现并发测试,能够有效地缩短芯核测试时间。该算法把测试调度问题的可行解集用种群表示,逐代演化产生出越来越好的近似解。详细分析了该算法过程,对2002年国际测试会议(ITC’02)所提供的So C国际基准电路进行测试调度实验,实验结果表明,此算法比传统的整数线性规划(ILP)和遗传算法的结果要好。     

3D NoC测试规划研究与实现

针对3D NoC资源内核的测试,采用NoC重用测试访问机制和XYZ路由方式,建立功耗模型,并通过云进化算法将IP核的测试数据划分到各TAM上进行并行测试,从而降低了测试时间。实验以ITC 02标准电路作为测试对象,其结果表明,文中方法可以有效地减少测试时间,提高了测试效率。     

测试生成算法

集成电路技术的迅速发展,测试生成变得越来越困难。往往测试代价比电路设计,生产代价还要高。扫描设计技术将时序电路的测试生成转换成组合电路来处理。组合电路的测试码生成就显得很重要了。D-算法第一次引入了多路径敏化的思想,因而是第一个完全的算法。但由于D-算法对故障校验电路处理所存在的缺陷,使得D-算法在测试码搜索过程中所存在的盲目性逐步表现得非常突出。PO-DEM算法第一次将测试生成问题归结为一个多维空间解的搜索问题。该算法采用隐枚举的方法来处理测试生成,并第一次引入了回退技术,使得测试码生成效率大大提高。FAN算法对PODEM算法作较大的改进。该算法引入了唯一敏化,唯一蕴含及多路回退等技术将测试码生成效率大大提高。不同于PODEM算法的是,FAN算法搜索测试码的回溯不是针对原始输入,而是对头线和扇出。SOCR-ATES算法在FAN算法的基础上,引入了全局蕴含的思想及一系列改进的唯一敏化和改进的多路回退策略。SOCRATES进而将全局蕴含及唯一敏化扩展到动态的策略,进一步提高了测试码生成效率。EST算法第一次提出了测试码搜索状态的概念,并采用E-前沿来描述测试码搜索的不同状态。通过引入状态等价的概念,大大缩小了测试码搜索空间。DST算法将测试码搜索空间的状态等价概念扩展到状态控制的概念,在EST算法的基础上,进一步大大缩小了搜索空间。     

测试生成算法

4 SOCRATES算法 SOCRATES在FAN算法的基础上提出一种全局的蕴含策略,改进的唯一敏化策略及改进的多路回退策略。这些策略有助于降低回溯次数,尽早地发现信号冲突,识别冗余故障。     

一种并行内建自诊断测试嵌入式SRAM方案

本文提出了具有自诊断功能的位定向MARCH-TB算法和字定向MARCH-TBW算法，并且在这两个算法的基础上提出并行测试结构来实现了嵌入式内存的测试和诊断。实验结果表明，此测试算法具有故障覆盖率高，诊断故障能力强，测试需要的时间少等优点。     

基于云进化算法的NoC测试规划

针对NoC测试时,如何在功耗限制下利用有限的片上资源最大化并行测试,以优化NoC测试时间的问题,文中提出一种利用云进化算法进行测试规划的方法,可以有效提高测试效率。该方法复用NoC的片上资源作为TAM,采用非抢占式测试和XY路由方式,通过云进化算法优化待测IP核在各条TAM上的分配方式寻找最佳方案。在ITC'02标准电路上的实验结果表明,该方法有效降低了测试时间,提高了测试效率。     

实现测试复用的SOC设计中的测试结构

在系统芯片SOC(system on a chip)设计中实现IP核测试复用的芯片测试结构一般包含两个部分：1)用于传送测试激励和测试响应的片上测试访问机制TAM;2)实现测试控制的芯片测试控制器。文章分析了基于测试总线的芯片测试结构,详细阐述了SOC设计中测试调度的概念,给出了一种能够灵活实现各种测试调度结果的芯片测试控制器的设计。     

引脚约束的数字微流控生物芯片在线并行测试

随着数字微流控生物芯片在生化领域中的广泛应用,对芯片可靠性和制造成本的要求也越来越高,在线测试对于确保微流控生物芯片正常工作异常重要。该文针对引脚约束的数字微流控生物芯片,提出一种基于改进最大最小蚁群算法的在线并行测试方案,在满足各种约束条件的情况下,采用伪随机比例原则,建立禁忌判断策略,自适应地改变信息素的残留系数,实现引脚约束数字微流控生物芯片的在线并行测试。实验结果表明,该方法可以同时用于离线和在线测试,相对于单液滴离线和在线测试,可有效减少芯片的测试时间,提高了测试工作效率。     

基于分区调度模型的IMA时间分区测试设计

针对综合模块化航空电子(IMA)时间分区测试问题,建立了IMA分区调度仿真模型。在该模型的基础上,提出一种可用于IMA时间分区测试的方法。该方法通过激励驻留在各个分区中的测试应用行为,增强了IMA各分区运行状态的可观测性。使用IMA分区调度模型生成了该测试方法可能产生的测试结果,针对模拟测试结果,分析并总结了该测试方法的时序特性。     

A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays

This paper addresses the partitioning and scheduling problems in mapping multi-stage regular iterative algorithms onto fixed size distributed memory processor arrays. We first propose a versatile partitioning model which provides a unified framework to integrate various partitioning schemes such as locally sequential globally parallel, locally parallel globally sequential and multi-projection. To alleviate the run time data migration overhead—a crucial problem to the mapping of multi-stage algorithms, we further relax the widely adopted atomic partitioning constraint in our model such that a more flexible partitioning scheme can be achieved. Based on this unified partitioning model, a novel hierarchical scheduling scheme which applies separate schedules at different processor hierarchies is then developed. The scheduling problem is then formulated into a set of ILP problem and solved by the existing software package for optimal solutions. Examples indicate that our partitioning model is a superset of the existing schemes and the proposed hierarchical scheduling scheme can outperform the conventional one-level linear schedule.     

Dynamic frame partitioning scheme for IEEE 802.16 mesh networks

The IEEE 802.16 mesh network is a promising next generation wireless backbone network. In the network, the allocation of minislots is handled by centralized scheduling and distributed scheduling, which are independently exercised. However, the standard does not specify how the frame can be partitioned among its centralized and distributed schedulers. Through efficient partitioning that dynamically adapts the partitioning based on demand, network can support more user applications. Although a dynamic frame partitioning scheme to use Markov model has been studied, the dynamic frame partitioning method has not been fully investigated. This paper proposes two novel and general dynamic frame partitioning scheme for IEEE 802.16 mesh networks so that the minislot allocation can be more flexible and the utilization is increased. The two schemes respectively use GM(1,1)‐Markov model and Grey–Verhulst–Markov model to predict efficient partitions for future frames according to the minislot utilization in current frames. Our study indicates that the two proposed schemes outperform the scheme of using Markov model. Copyright © 2012 John Wiley & Sons, Ltd.     

A Graph Route-Based Superframe Scheduling Scheme in WirelessHART Mesh Networks for High Robustness

WirelessHART is considered to be one of the most promising wireless network protocols for its high robustness comparing to other similar wireless networks. The high robustness comes from its unique routing protocol and redundant superframe scheduling scheme. This paper focuses on the time-slot scheduling and channel assignment of WirelessHART and a graph route-based superframe scheduling scheme is proposed. In order to improve the communication reliability, our scheme applies hop-level retransmission mechanism in a multi-hop and multi-channel circumstance. Moreover, time-slot conflict and channel interference are considered and an effective solution strategy is proposed. To meet the real-time communication requirements, time-slots are assigned in the order of actual communication sequence which can effectively reduce the retransmission delay. Further more, we propose the implementation algorithm of our scheme. The performance analysis shows that our scheduling scheme has a higher robustness than the traditional non-redundancy scheme.     

Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs

This paper presents a unique scheme for testing and locating multiple stuck at faults in the embedded RAM modules of SRAM-based FPGAs. The RAM modules are tested using the MATS++ algorithm. The interconnection scheme makes it possible to test all the cells within the RAM modules in the FPGA in just one test configuration. We also develop a diagnosis scheme capable of locating the faulty RAM cells and the CLB in which it is located. In this research, emphasis is also laid on reducing the testing time, which is achieved by partitioning the FPGA into two halves.     

Resource partitioning for real-time communication

For real-time communication services to achieve widespread usage, it is important that network managers be allowed to control the services effectively. An important management capability concerns resource partitioning. Resource partitioning is useful for a number of applications, including the creation of virtual private subnetworks and of mechanisms for advance reservation of real-time network services, fast establishment of real-time connections, and mobile computing with real-time communication. In previous work, the authors presented a scheme for resource partitioning in a guaranteed performance networking environment with EDD-based packet scheduling disciplines. The present paper gives the results of research in resource partitioning, with admission control tests for resource partitioned servers for four representative scheduling disciplines, FIFO, WFQ, RCSP and EDD. The simulations confirm the intuition that resource fragmentation losses due to resource partitioning are small and that resource partitioning reduces the admission control computation overhead. An interesting result from the simulation experiments is that, under circumstances that arise naturally in multi-party communication scenarios, resource partitioning results in higher overall connection acceptance rate. The authors also present experiences with implementing resource partitioning in the second generation of Tenet real-time protocols; this implementation, with resource partitioned servers, runs on multiple platforms, including Sun workstations under SunOS, DEC workstations under Ultrix, and PCs under BSDI Unix     

Distributed two‐hop proportional fair resource allocation in Long Term Evolution Advanced networks

In Long Term Evolution Advanced networks with Type I in‐band half‐duplex decode‐and‐forward relay nodes, proportional fair (PF) resource allocation is aiming at guaranteeing two‐hop match and optimising global proportional fairness. The two‐hop match is defined as equal data rates in the access links and the corresponding backhaul links. The global proportional fairness is between all the user equipments served by the evolved nodes B and the relay nodes. Existing centralised schemes achieve these targets at the cost of enormous channel state information (CSI) exchange. Existing distributed schemes focus on resource partitioning and employ a traditional single‐hop PF scheduling algorithm in access links, with less CSI exchange. The traditional PF scheduling algorithm maximises single‐hop proportional fairness between the data rates in the access links rather than two‐hop proportional fairness between the end‐to‐end data rates in the two hops. In order to reduce CSI exchange and at the same time to maximise the two‐hop proportional fairness, a distributed two‐hop PF resource allocation scheme is proposed. The proposed scheme includes two‐hop PF resource scheduling algorithms and adaptive resource partitioning algorithms, applied in different two‐hop transmission protocols. Simulation results demonstrate the proposed scheme is better than the existing distributed schemes in obtaining better proportional fairness and larger cell‐edge user equipment throughputs. Copyright © 2014 John Wiley & Sons, Ltd.