A comparison of three‐dimensional electromagnetic and RC parasitic extraction analysis of mm‐wave on‐chip passives in SiGe BiCMOS low‐noise amplifiers

Layout parasitics significantly impact the performance of mm‐wave microelectronic circuits. These effects may be estimated by including foundry‐qualified pcell interconnect models in schematic with or without additional RC parasitics extraction (RCPE), or by generating an EM simulation (FEM and MoM) of the layout and cosimulating with active device models. In this paper, these methods are compared at by simulating the compression (P1db), gain (S₂₁), and noise figure (NF) of a V‐band LNA in 130 nm SiGe BiCMOS and comparing the results of different simulation approaches to measurements. It is found that the FEM cosimulated results agree better with the measurements than the other methods, providing a maximum error of 0.8 dB in gain, 0.18 dB in NF, and 0.6 dB in P1dB. This is a significant improvement over the errors obtained with pcell‐based schematic (2.6 dB in gain, 0.1 dB in NF, and 2.2 dB in P1db), schematic simulation with RCPE (1.55 dB in gain, 1.15 dB in NF, and 0.8 dB in P1db), and MoM cosimulation (0.67 dB in gain, 0.72 in NF, and 0.67 in P1db). This experiment validates the preference to FEM cosimulation in mm‐wave microelectronic circuits yet would indicate that reasonably accurate first‐iteration results may be obtained through a combined pcell‐RCPE approach with significantly shorter simulation time.     

Alternative approach to low‐noise amplifier design for ultra‐wideband applications

Conventional ultra‐wideband low‐noise amplifiers require a flat gain over the entire 3.1–10.6 GHz bandwidth, which severely restraints the trade‐off spaces in low noise amplifier design. This article proposes a relaxed gain‐flatness requirement based on system level investigations. Considering the wireless transceiver front‐end with antenna and propagation channel, the unflat‐gain low‐noise amplifier with an incremental gain characteristic does not degrade the performance of overall system. As an alternative to its flat‐gain counterpart, the proposed unflat gain requirement tolerates gain ripple as large as 10 dB, which greatly eases the design challenges to low‐noise amplifier for ultra‐wideband wireless receivers. Two low‐noise amplifier examples are given to demonstrate the feasibility and design flexibility under the proposed gain‐flatness requirement. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

Analysis and design of a fully integrated CMOS low‐noise amplifier for concurrent dual‐band receivers

This article thoroughly analyzes a concurrent dual‐band low‐noise amplifier (LNA) and carefully examines the effects of both active and passive elements on the performance of the dual‐band LNA. As an example of the analysis, a fully integrated dual‐band LNA is designed in a standard 0.18‐μm 6M1P CMOS technology from the system viewpoint for the first time to provide a higher gain at the high band in order to compensate the high‐band signal's extra loss over the air transmission. The LNA drains 6.21 mA of current from a 1.5‐V supply voltage and achieves voltage gains of 14 and 22 dB, input S₁₁ of 15 and 18 dB, and noise figures of 2.45 and 2.51 dB at 2.4 and 5.2 GHz, respectively. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

Design and implementation of a dual‐band concurrent fully‐integrated LNA for WLAN IEEE 802.11a/b/g applications

This article presents a dual‐band concurrent fully‐integrated low‐noise amplifier (LNA) targeted to WLAN IEEE 802.11a/b/g standards. The use of a concurrent topology enables saving die area and power consumption compared with the parallel solution that employs two separated LNAs. An original design methodology that helps in the selection of input/output matching network element values is also presented. The LNA die area is 1.0 × 0.9 mm² and it consumes 9 mW (5 mA at 1.8 V). © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

Hybrid Ku‐band low‐noise amplifier for mobile DBS active phased‐array antennas

In this article we present a two‐stage Ku‐band low‐noise amplifier (LNA) using discrete pHEMT transistors on non‐PTFE substrates for low‐cost direct broadcast satellite (DBS) phased‐array systems (patent pending). The vertical input configuration of the LNA lends itself to direct integration with input port of antenna modules of the phased array, which minimizes preamplification losses. DC decoupling between LNA stages is realized using interdigital microstrip capacitors such that the implementation reduces the number of discrete microwave components and thereby not only reduces the component and assembly costs but also decreases the standard deviation of such crucial parameters of phased‐array systems as the end‐to‐end phase shift of the amplifier and the amplifier gain. Using the proposed printed decoupling capacitors, a cost reduction better than 30% of the original costs has been achieved. Additionally, we present a hybrid design procedure for the complete LNA, including its input and output connectors as well as packaging effects. This method is not based on parameter extraction, but encompasses electromagnetic (EM) field simulator results which are further combined using a high‐level circuit simulator. According to the presented measurement results, the implemented Ku‐band LNA has a noise figure better than 0.9 dB and a gain higher than 20 dB with a gain flatness of 0.3 dB over a 5% bandwidth. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

A miniature low‐power ultra‐wideband low noise amplifier in 0.18 μm CMOS

A 0.18‐μm CMOS low‐noise amplifier (LNA) operating over the entire ultra‐wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of ?8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from ?8 to ?1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm² without RF and DC pads. The design uses only two on‐chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

Closed‐form approach to design distributed matching networks for high‐frequency amplifiers

Based on the use of distributed lossless elements, a closed‐form synthesis for double‐frequency‐matching networks is introduced with an emphasis on the design of high‐frequency amplifiers. Three different circuit conditions are considered and design relationships are provided and discussed. Finally, the proposed approach, which uses the circle method, is successfully employed to design a Ka‐band (26–32 GHz) linear amplifier with gain equal to 8 dB and return loss greater than 10 dB for the considered band. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

A backstepping‐based low‐and‐high gain design for marine vehicles

A backstepping control design for marine vehicles was described in (Marine Control Systems: Guidance, Navigation and Control of Ships, Rigs, and Underwater Vehicles. Marine Cybernetics AS: Trondheim, Norway, 2002). Under a backstepping feedback law, global asymptotic stability of the closed‐loop system can be shown under the assumption of unlimited actuation. This paper addresses the issues that arise in the implementation of a backstepping feedback law by saturating actuators. First, for a given backstepping feedback law, an estimate of the domain of attraction is given for the resulting closed‐loop system under actuator saturation. A high gain component is then constructed and augmented to the original backstepping feedback law. This additional high gain component is shown not to shrink the estimate of the domain of attraction but to possess the ability to improve the closed‐loop response and to reject disturbance. Copyright © 2008 John Wiley & Sons, Ltd.     

A low‐profile,low‐cost antenna system with improved gain for DSRC vehicle‐to‐vehicle communications

A novel wire antenna for future dedicated short range communications vehicle‐to‐vehicle communications is introduced. The proposed antenna carries low‐profile and low‐cost features, and possesses an improved gain performance. This article also includes a specific feed network design for the proposed antenna to meet the mechanical and manufacturing requirements. Two different numerical techniques using CST Microwave Studio and HFSS have been applied for evaluating the performance of the proposed antenna. The whole system including the feed network and the antenna elements is integrated, and its performance is also assessed. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.     

Three‐stage multi‐innovation parameter estimation for an exponential autoregressive time‐series model with moving average noise by using the data filtering technique

This paper studies the data filtering‐based identification algorithms for an exponential autoregressive time‐series model with moving average noise. By means of the data filtering technique and the hierarchical identification principle, the identification model is transformed into three sub‐identification (Sub‐ID) models, and a filtering‐based three‐stage extended stochastic gradient algorithm is derived for identifying these Sub‐ID models. In order to improve the parameter estimation accuracy, a filtering‐based three‐stage multi‐innovation extended stochastic gradient (F‐3S‐MIESG) algorithm is developed by using the multi‐innovation identification theory. The simulation results indicate that the proposed F‐3S‐MIESG algorithm can work well.     

A 1.4‐Gbps intra‐panel interface with low‐power and low‐EMI schemes for Tablet PC applications

An intra‐panel interface addressing all of the high‐speed, low‐power, and low‐electromagnetic interference (EMI) requirements for tablet personal computer applications is presented. This work proposes an adaptive clock window scheme to achieve 1.4‐Gbps data‐rate. For EMI suppression, data scrambling, horizontal blank period pattern scrambling, and novel clock and data recovery circuit are introduced. Lastly, for power‐saving, the proposed interface dynamically biases source driver's output buffers and employs early charge sharing by controlling the configuration data. For verification, a WQXGA thin‐film transistor liquid crystal display system is implemented with the timing controller and source driver ICs that are fabricated using 65‐nm and 180‐nm complementary metal‐oxide semiconductor (CMOS) processes, respectively. The liquid crystal display system demonstrates maximum operation speed of 1.4 Gbps and suppression of EMI noise in LTE Band‐20 and GSM 850 bands. The proposed power‐saving schemes achieve 4.3% reduction in total power consumption by source driver IC, which reaches about 85% of power consumption by enhanced reduced‐voltage differential signaling interface circuit.     

A combined technique for amplifier oriented small‐signal noise model extraction

Based on the earlier experimental investigation of the existing GaAs pHEMT small‐signal modeling approaches and their applicability to different manufacturing processes, a combined automatic small‐signal noise model extraction technique, suitable for design of low‐noise and buffer amplifiers is proposed. The technique is based on the usage of measured S‐parameters of passive test structures and S‐parameters of the transistor in cold modes. Expressions are given for extraction of the intrinsic parameters of an equivalent circuit using linear regression. It is shown that the application of the proposed method allows extracting a small‐signal GaAs pHEMT model both in the probe‐tip reference planes and at on‐wafer calibration planes. The moving average algorithm was applied for preprocessing the results of measurements of the 50 Ohm noise figure during extraction of the noise model. The results of S‐parameters and noise figure simulation agree well with the measurements. The new technique was implemented as a plugin in a commercial EDA tool and enables to derive a ready‐to use small‐signal noise model from measured S‐parameters and 50 Ohm noise figure of a 0.15 μm GaAs pHEMT.     

A 3.4 dB NF k‐band LNA with a tapped capacitor matching network in 65 nm CMOS technology

This article proposes a tapped capacitor network for low‐noise amplifier (LNA) input matching which can provide much broader bandwidth than traditional ones. According to the design, the implemented LNA can realize noise match and power match simultaneously, which will broaden LNA's bandwidth without introducing larger noise than traditional ones. In addition, input pad parasitic capacitance can be absorbed by the network. Then a k‐band LNA with the matching network designed in 65 nm CMOS technology is shown to demonstrate the performance of the matching network. The tested results show that frequency band of S₁₁ less than ?10 dB is about 17 GHz and minimum NF is about 3.4 dB. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:146–153, 2015.     

A systematic design of 1.5–9 GHz high power–high efficiency two‐stage GaAs PHEMT power amplifier

In this article, a systematic design approach for a Class‐A operated wideband power amplifier is presented. The power amplifier structure comprises of two transistors in the cascaded single stage traveling wave amplifier topology. A power amplifier was designed by using the systematic approach and fabricated with 0.25 μm GaAs PHEMT MMIC process. The amplifier has an area of 3.4 × 1.4 mm². Measurement results show that almost flat gain performance is obtained around 15 dB over 1.5–9 GHz operating bandwidth. In most of the band, with the help of a wideband load‐pull matching technique, the amplifier delivers P_o,sat and P_o,1dB of around 30 dBm and 28 dBm where the corresponding power added efficiencies are >50% and >36%, respectively. It is shown that the proposed design approach has the advantage of simple and systematic design flow and it helps to realize step‐by‐step design for the designers. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 24:615–622, 2014.     

A low‐cost high‐gain dual polarized antenna design from cuboids and shorting strips for base stations

This article presents a novel low‐cost high‐gain dual‐polarized antenna using suspended cuboid and ground connected cuboid geometry. The design structure of the antenna is simple and it's all components are fabricated by a copper sheet of thickness 0.5 mm. The prototype is fabricated and measured and has ?15 dB impedance bandwidths of 33.33%(2.5‐3.5 GHz) with broadside gain of 9.2 ± 0.3 dBi and 32.25%(2.6‐3.6 GHz) with broadside gain 9 ± 0.3 dBi over bandwidths when measured from port 1 and port 2, respectively. The isolation between the ports is enhanced by shorting suspended cuboid from the ground plane and measured one more than 17 dB from 2.45 to 3.7 GHz. The proposed dual polarized antenna can be used for base stations such as Wireless Local Area Network (WLAN), Long Term Evolution (LTE), and Worldwide Interoperability for Microwave Access (WiMAX) applications. The antenna is designed and simulated and there are good agreements between simulated and measured results are obtained.     

A small‐area and low‐power data driver IC using two‐stage DAC with a capacitor array for active matrix flat‐panel displays

A small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/?0.52 least significant bit and +0.62/?0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one.     

A low‐profile wideband dual‐polarized antenna with gain enhancement,low gain variations,and low cross polarization for 5G indoor communications

A low‐profile wideband dual‐polarized antenna with high gain, low gain variations, and low cross‐polarization for the fifth generation (5G) indoor distribution system is proposed. By using circular‐thread vase‐shaped structure, a low profile of 0.23λ₀ (λ₀ is the free‐space wavelength at the starting frequency) as well as low gain variation feature can be achieved by the vertically polarized (VP) radiating element. An eight‐way power divider network is employed to feed the horizontally polarized (HP) dipoles so that wideband performance is obtained. Here, eight pairs of arc‐shaped parasitic strips are used to broaden the bandwidth, and eight pairs of director elements are introduced to enhance the gain and reduce the gain variations. In addition, the protruded stubs that are extended from the circular ground plane will help to reduce the cross polarization in the VP direction. Measured results show that a bandwidth of 46.5% (3.3‐5.3 GHz) (S₁₁ < ?10 dB) with a gain of 0.85 ± 0.35 dBi, and another bandwidth of 85.0% (2.5‐6.2 GHz) with a gain of 4.75 ± 1.75 dBi can be realized in the HP and VP directions, respectively. Furthermore, high isolation (>27 dB) and low cross polarization (<?24 dB) can also be attained. Therefore, the proposed antenna is a good candidate for 5G indoor distributed system.     

A frame‐based EM‐simulation for design of LC oscillator with MoM capacitor banks

This article presents a simulation method for the design of a digitally controlled oscillator (DCO). Electromagnetic (EM) simulations are essential and inevitable for modern LC oscillator design. Although EM‐simulators provide high accuracy, the EM‐simulation time is very long when metal‐oxide‐metal (MoM) capacitors are present. The proposed frame‐based EM‐simulation can significantly reduce the EM‐simulation time even in the presence of MoM capacitors without influencing the accuracy. To verify the proposed method, a DCO was fabricated using a 55‐nm CMOS process. Measurements of the DCO are in good agreement with the frame‐based post‐layout simulation results. In addition, the DCO has good performances with a low power consumption of approximately 0.68 mW.