X波段GaN基微波功率放大器的设计

给出了一种X波段GaN基功率放大器的设计方法。研究了相关的偏置电路、匹配网络以及稳定性网络,实现了6个GaNHEMT器件的功率合成。该方法在偏置VGS=-3.2V,VDS=6V,IDS=200mA,频率为8GHz时,可以仿真得到的放大器增益为20.380dB,饱和输出功率可以达到35.268dBm(约为3.36W)。     

基于噪声消除技术的超宽带CMOS低噪声放大器设计

为满足3.5 GHz单载波超宽带无线接收机的射频需求,设计了一种工作在3～4 GHz的超宽带低噪声放大器。电路采用差分输入的CMOS共栅级结构,利用MOS管跨导实现宽带输入匹配,利用电容交叉耦合结构和噪声消除技术降低噪声系数,同时提高电压增益。分析了该电路的设计原理和噪声系数,并在基于SMIC 0.18μm CMOS射频工艺进行了设计仿真。仿真结果表明:在3～4GHz频段内,S11和S22均小于-10 dB,S21大于14dB,带内起伏小于0.5dB,噪声系数小于3dB;1.8V电源电压下,静态功耗7.8mW。满足超宽带无线接收机技术指标。     

Investigation on harmonic spur characteristics of hybrid integrated LDMOS and AlGaN/GaN power amplifiers at different temperatures

The harmonic spur characteristics of a hybrid integrated S‐band power amplifier (PA), consisting of both stages of LDMOSFET and AlGaN/GaN HEMT, are studied at different temperatures. The PA offers a peak output power of 50 dBm (100 W) with power added efficiency higher than 50%, and adjacent channel power ratio performance is less than ?30 dBc. A temperature test chamber is employed for measuring the harmonic spur of PA from 233 to 393 K, and its linear response to temperature is captured at high output power level.     

A 200 W broadband high power amplifier using hybrid power combining network and digital level control

In this article, a 2 to 6 GHz solid‐state power amplifier with 53 dBm output power has been analyzed, designed, and fabricated. To achieve a wideband high output power, we introduce a 16‐way hybrid power combiner based on microstrip planar binary and parallel structures. The simulation and measurement results of the proposed hybrid power combining network (PCN) show that the maximum power combining efficiency is around 86% with the insertion loss of around 0.6 to 1.5 dB and an isolation of 20 dB between the ports. Also, to compensate the output power variations due to the thermal and operating frequency changes across the bandwidth, a digital level control (DLC) unit utilizing an agile control algorithm is proposed which decreases the output power variations to 2% of the desired output power. A cooling heatsink fan system has been also designed in order to transfer the heat generated power to the air. The measured output power for the applied input continuous wave is higher than 52.5 dBm. In addition, the power added efficiency (PAE) is better than 15% across the wide portion of the bandwidth and the measured third‐order intermodulation is about 20 dBc (average).     

A miniature low‐power ultra‐wideband low noise amplifier in 0.18 μm CMOS

A 0.18‐μm CMOS low‐noise amplifier (LNA) operating over the entire ultra‐wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of ?8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from ?8 to ?1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm² without RF and DC pads. The design uses only two on‐chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

Alternative approach to low‐noise amplifier design for ultra‐wideband applications

Conventional ultra‐wideband low‐noise amplifiers require a flat gain over the entire 3.1–10.6 GHz bandwidth, which severely restraints the trade‐off spaces in low noise amplifier design. This article proposes a relaxed gain‐flatness requirement based on system level investigations. Considering the wireless transceiver front‐end with antenna and propagation channel, the unflat‐gain low‐noise amplifier with an incremental gain characteristic does not degrade the performance of overall system. As an alternative to its flat‐gain counterpart, the proposed unflat gain requirement tolerates gain ripple as large as 10 dB, which greatly eases the design challenges to low‐noise amplifier for ultra‐wideband wireless receivers. Two low‐noise amplifier examples are given to demonstrate the feasibility and design flexibility under the proposed gain‐flatness requirement. © 2007 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2007.     

Hybrid Ku‐band low‐noise amplifier for mobile DBS active phased‐array antennas

In this article we present a two‐stage Ku‐band low‐noise amplifier (LNA) using discrete pHEMT transistors on non‐PTFE substrates for low‐cost direct broadcast satellite (DBS) phased‐array systems (patent pending). The vertical input configuration of the LNA lends itself to direct integration with input port of antenna modules of the phased array, which minimizes preamplification losses. DC decoupling between LNA stages is realized using interdigital microstrip capacitors such that the implementation reduces the number of discrete microwave components and thereby not only reduces the component and assembly costs but also decreases the standard deviation of such crucial parameters of phased‐array systems as the end‐to‐end phase shift of the amplifier and the amplifier gain. Using the proposed printed decoupling capacitors, a cost reduction better than 30% of the original costs has been achieved. Additionally, we present a hybrid design procedure for the complete LNA, including its input and output connectors as well as packaging effects. This method is not based on parameter extraction, but encompasses electromagnetic (EM) field simulator results which are further combined using a high‐level circuit simulator. According to the presented measurement results, the implemented Ku‐band LNA has a noise figure better than 0.9 dB and a gain higher than 20 dB with a gain flatness of 0.3 dB over a 5% bandwidth. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

Efficiency enhancement by employing the transistor nonlinear capacitors effects in a 6W hybrid X‐band Class‐J power amplifier

This article presents the design and fabrication of a 6 W X‐band hybrid Class‐J power amplifier (PA) based on a bare die GaN on SiC HEMT by accurate implementing the transistor nonlinear capacitor effects. The transistor input capacitor is precisely modelled and its nonlinearity effects on Class‐J performance is studied for the first time. It is shown that the harmonic generation property of the nonlinear input capacitor, especially at the second harmonic, can be of benefit to shape the transistor gate voltage as a quasi‐half wave sinusoidal waveform and consequently, it can improve the power added efficiency (PAE). A complete 3D thermal model of the power transistor is developed using ANSYS software and it is calibrated based on the thermal measured data. The PA achieves 13 dB average power gain over the frequency range of 8.8‐9.6 GHz. The drain efficiency and PAE are about 67% and 58% at 9.2 GHz, respectively.     

A low offset chopper amplifier with three-stage nested Miller configuration

A low offset,low noise chopper amplifier for sensor system application is presented.Low 1/f noise is achieved by employing chopper technique,and low offset is achieved by employing residual offset suppression circuit.The open-loop gain is extended using three-stage nested Miller configuration.The chip was implemented in 0.5μm 2P3M CMOS process.The amplifier is featured by an open-loop gain of 135 dB and a GBW of3 MHz.The measured offset voltage is 3μV,and the equivalent input noise power spectrum density at 1 Hz is96 nV/√Hz.     

Analysis and design of a fully integrated CMOS low‐noise amplifier for concurrent dual‐band receivers

This article thoroughly analyzes a concurrent dual‐band low‐noise amplifier (LNA) and carefully examines the effects of both active and passive elements on the performance of the dual‐band LNA. As an example of the analysis, a fully integrated dual‐band LNA is designed in a standard 0.18‐μm 6M1P CMOS technology from the system viewpoint for the first time to provide a higher gain at the high band in order to compensate the high‐band signal's extra loss over the air transmission. The LNA drains 6.21 mA of current from a 1.5‐V supply voltage and achieves voltage gains of 14 and 22 dB, input S₁₁ of 15 and 18 dB, and noise figures of 2.45 and 2.51 dB at 2.4 and 5.2 GHz, respectively. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

A low-noise fully-differential CMOS preamplifier for neural recording applications

A fully-differential bandpass CMOS preamplifier for extracellular neural recording is presented in this paper.The capacitive-coupled and capacitive-feedback topology is adopted.We describe the main noise sources of the proposed preamplifier and discuss the methods for achieving the lowest input-referred noise.The preamplifier has a midband gain of 43 dB and a DC gain of 0.The-3 dB upper cut-off frequency of the preamplifier is 6.8 kHz.The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands.It has an input-referred noise of 3.36 μVrms integrated from 1 Hz to 6.8 kHz for recording the local field potentials(LFPs)and the mixed neural spikes with a power dissipation of 24.75 μW from 3.3 V supply.When the passband is configured as 100 Hz-6.8 kHz for only recording spikes,the noise is measured to be 3.01 μVrms.The 0.115 mm2 prototype chip is designed and fabricated in 0.35-μm N-well CMOS(complementary metal oxide semiconductor)2P4M process.     

Large‐signal modeling methodology for GaN HEMTs for RF switching‐mode power amplifiers design

A large‐signal model for GaN HEMT transistor suitable for designing radio frequency power amplifiers (PAs) is presented along with its parameters extraction procedure. This model is relatively easy to construct and implement in CAD software since it requires only DC and S‐parameter measurements. The modeling procedure was applied to a 4‐W packaged GaN‐on‐Si HEMT, and the developed model is validated by comparing its small‐ and large‐signal simulation to measured data. The model has been employed for designing a switching‐mode inverse class‐F PA. Very good agreement between the amplifier simulation and measurement shows the validity of the model. © 2010 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011.     

采用噪声抵消技术的高增益CMOS宽带LNA设计

设计了一种面向多频段应用的CMOS宽带低噪声放大器。采用噪声抵消技术以及局部负反馈结构,引入栅极电感补偿高频的增益损失,电路具有高增益、低噪声的特点,并且具有平坦的通带增益。设计采用UMC 0.18μm工艺,后仿真显示:在1.8 V供电电压下,LNA的直流功耗约为9.45 mW,电路的最大增益约为23 dB,3 dB频带范围为0.1 GHz¹.35 GHz,3 dB带宽内的噪声约为1.7 dB1.35 GHz,3 dB带宽内的噪声约为1.7 dB⁵ dB;在1 V供电电压下,电路依然能够保持较高的性能。     

一款低噪声八相位锁相环设计

基于宽频率范围数字系统的需求,在0.13μm工艺下设计了一款宽输出范围、低抖动八相位锁相环。首先通过数学建模优化环路带宽,在系统级减小环路噪声;在振荡器中引入了前馈传输管单元以提高振荡频率并降低振荡器相位噪声;最后利用具有伪静态结构的D触发器来降低鉴相器和分频器的功耗并提高其抗噪声能力。仿真结果表明,VCO输出频率在1.2 GHz时相位噪声为-95dBc/Hz@1MHz,FOM功耗为4.5PJ@2GHz。     

Design of low noise airfoil with high aerodynamic performance for use on small wind turbines

Wind power is one of the most reliable renewable energy sources and internationally installed capacity is increasing radically every year.Although wind power has been favored by the public in general,the problem with the impact of wind turbine noise on people living in the vicinity of the turbines has been increased.Low noise wind turbine design is becoming more and more important as noise is spreading more adverse effect of wind turbine to public.This paper demonstrates the design of 10 kW class wind turbi...     

Design and implementation of a dual‐band concurrent fully‐integrated LNA for WLAN IEEE 802.11a/b/g applications

This article presents a dual‐band concurrent fully‐integrated low‐noise amplifier (LNA) targeted to WLAN IEEE 802.11a/b/g standards. The use of a concurrent topology enables saving die area and power consumption compared with the parallel solution that employs two separated LNAs. An original design methodology that helps in the selection of input/output matching network element values is also presented. The LNA die area is 1.0 × 0.9 mm² and it consumes 9 mW (5 mA at 1.8 V). © 2008 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2009.     

A 3.4 dB NF k‐band LNA with a tapped capacitor matching network in 65 nm CMOS technology

This article proposes a tapped capacitor network for low‐noise amplifier (LNA) input matching which can provide much broader bandwidth than traditional ones. According to the design, the implemented LNA can realize noise match and power match simultaneously, which will broaden LNA's bandwidth without introducing larger noise than traditional ones. In addition, input pad parasitic capacitance can be absorbed by the network. Then a k‐band LNA with the matching network designed in 65 nm CMOS technology is shown to demonstrate the performance of the matching network. The tested results show that frequency band of S₁₁ less than ?10 dB is about 17 GHz and minimum NF is about 3.4 dB. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:146–153, 2015.     

A straightforward design technique for narrowband multi‐stage low‐noise amplifiers with I/O conjugate match

Low‐noise amplifier (LNA) designers often struggle to simultaneously satisfy gain, noise, stability, and I/O matching requirements. In this article, a novel design technique, tailored for two‐stage low‐noise amplifiers, is presented. The proposed design method is completely deterministic and exploits inductive source degeneration to obtain a two‐stage LNA featuring perfect input and output match together with low noise figure (NF) and a pre‐determined gain, including stability analysis. A novel flowchart is provided together with the corresponding design chart that contains gain, matching, and stability information, therefore addressing all key figures‐of‐merit of a linear amplifier. The design chart is easily implementable in commercial Electronic Design Automation software, to aid designers in the difficult task of selecting the appropriate source degeneration inductor value. The noise performance, on the other hand, is the best possible since the matching networks are designed to provide the input of the two Field Effect Transistors with the optimum termination for noise. The design method is validated with two separate test vehicles operating respectively at Ka‐band (26.5‐31.5 GHz) and K‐band (20.0‐24.0 GHz). The realized Monolithic Microwave Integrated Circuits exhibit 18 dB gain for both versions, NF of 1.5 and 1.2 dB, respectively for the Ka‐band and K‐band version. Input and output matching are typically better than 12 and 15 dB.     

A hybrid prediction method for low-subsonic turbulent flow noise

A hybrid method is proposed for prediction of low-subsonic, turbulent flow noise. In this method, the noise sources in the near wall turbulences or in the wake are computed by the incompressible large eddy simulation (LES), while the generation and propagation of the acoustic waves are solved by the linearized perturbed compressible equations (LPCE), with acoustic sources represented by a material derivative of the hydrodynamic pressure, DP/Dt. The accuracy of the present method is critically assessed for two experiments conducted at the Ecole Centrale de Lyon and the University Erlangen, where aeroacoustic measurements were taken for (i) the flat plate self-noise at zero angle of attack and (ii) the forward-facing step noise , respectively. The noise sources are identified and analyzed further to determine their spectral-dependent, spanwise coherence functions, γ_ij of the wall pressure fluctuations, in order to quantify the sizes of the noise sources. The far-field sound pressure level (SPL) spectra predicted by the present method are found in excellent agreement with the experimental measurements.