Submicrometer electron-beam direct writing technology for 1-Mbit DRAM fabrication

A 1-Mbit DRAM with 0.5-µm minimum linewidth is fabricated using variable shaped e-beam direct writing technology. A simple linewidth control technique using newly developed submicrometer resists is developed to achieve high resolution and better linewidth accuracy. In addition, a highly accurate registration technique is developed to ensure required overlay. These techniques are successfully used to achieve overlay accuracy of 0.04 µm(σ) and linewidth deviation of 0.018 µm(σ) in the fabrication.     

1 /spl mu/m MOSFET VLSI technology. VI. Electron-beam lithography

For pt.V see ibid., vol.SC14, no.2, p.275 (1979). The authors discuss the fabrication of 1 /spl mu/m minimum linewidth FET polysilicon-gate devices and circuits, with emphasis on vector-scan electron-beam technology and processing. Different types of 1 /spl mu/m MOSFET chips were written on 57 mm Si wafers using a totally automated electron-beam system. The pattern data were prepared by batch processing which includes proximity correction as well as sorting of shapes to achieve data compaction and minimal distance between shapes. A novel two-layer positive resist system has been developed to achieve reproducible liftoff profiles over topography and better linewidth control. The final results presented here demonstrate that there are no fundamental barriers to the extension of this work to small dimensions.     

Linewidth of InP-based 1.55 /spl mu/m VCSELs with buried tunnel junction

Spectral linewidth measurements of 1.55 /spl mu/m InGaAlAs/InP vertical-cavity surface-emitting lasers (VCSELs) employing a buried tunnel junction are reported. A narrow linewidth around 28 MHz was obtained at a power level of 0.5 mW using the self-heterodyne method, and an estimation for the linewidth enhancement factor is given.     

On-chip timing measurement architecture with femtosecond resolution

A new timing measurement architecture based on the time-to-digital conversion technique is presented. The architecture occupies a small silicon area (200/spl times/185 /spl mu/m) in a 0.12 /spl mu/m CMOS process and can achieve tens of femtoseconds timing resolution, which is the highest reported to date.     

Damping-limited modulation bandwidths up to 40 GHz in undoped short-cavity In/sub 0.35/Ga/sub 0.65/As-GaAs multiple-quantum-well lasers

We demonstrate record direct modulation bandwidths from MBE-grown In/sub 0.35/Ga/sub 0.65/As-GaAs multiple-quantum-well lasers with undoped active regions and with the upper and lower cladding layers grown at different growth temperatures. Short-cavity ridge waveguide lasers achieve CW direct modulation bandwidths up to 40 GHz for 6/spl times/130 /spl mu/m/sup 2/ devices at a bias current of 155 mA, which is the damping limit for this structure. We further demonstrate large-signal digital modulation up to 20 Gb/s (limited by the measurement setup) and linewidth enhancement factors of 1.4 at the lasing wavelength at threshold of /spl sim/1.1 /spl mu/m for these devices.     

Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 /spl mu/m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element selection and precise measurement are achieved with low parasitic resistance measurement buses and leakage-controlled switching circuits, which allow the measurement accuracy for a transistor, resistor, or capacitor of 90 pA, 11 m/spl Omega/, and 23 aF, respectively, in the 3/spl sigma/ range. The ability to obtain 29 008 samples from a chip enables statistical analysis of the variation in 148 elements of each chip with 240-/spl mu/m spatial resolution. This high resolution and large sample number allows us to precisely decompose the data into systematic and random variation parts with newly developed fourth-order polynomial fitting. Our methodology has been verified using a test chip fabricated by a 130-nm CMOS process with a 100-nm physical gate length and five Cu interconnect layers. In MOSFETs, the random part was dominant and indicated a certain /spl sigma/ value in every chip. In the case of the interconnect layers, the random and systematic parts of the resistance and the capacitance indicated variance fluctuations. By chip, by item, by size, by structure, random or systematic, the /spl sigma/ values of each variation show inconsistency which we believe is attributable to the Cu process. The correlation coefficients of systematic part between device element and ring oscillator frequency shown very high value (0.87-0.98), and those of a random part were low enough (-0.10-0.22) to prove the accuracy of decomposition.     

A pipelined temporal difference imager

A 189/spl times/182 active pixel sensor (APS) for temporal difference computation is presented. The temporal difference imager (TDI), fabricated in 0.5-/spl mu/m CMOS process, contains in-pixel storage elements for a previous image frame. Difference double-sampling circuits are used to suppress the fixed pattern noise in both images and to compute the difference between the corrected images. The pixel area occupies 25 /spl mu/m by 25 /spl mu/m (using 0.7-/spl mu/m scalable rules), with fill factor of 30%. A novel pipelined readout technique is described, which is used to improve the accuracy of the temporal difference computation. With this pipelined readout architecture, >8-bit precision for the difference image and low spatial droop across the difference image is achieved. The chip consumes 30 mW at 50 fps from a 5-V power supply.     

Low-noise metamorphic HEMTs with reflowed 0.1-/spl mu/m T-gate

A 0.1-/spl mu/m T-gate fabricated using e-beam lithography and thermally reflow process was developed and applied to the manufacture of the low-noise metamorphic high electron-mobility transistors (MHEMTs). The T-gate developed using the thermally reflowed e-beam resist technique had a gate length of 0.1 /spl mu/m and compatible with the MHEMT fabrication process. The MHEMT manufactured demonstrates a cutoff frequency f/sub T/ of 154 GHz and a maximum frequency f/sub max/ of 300 GHz. The noise figure for the 160 /spl mu/m gate-width device is less than 1 dB and the associated gain is up to 14 dB at 18 GHz. This is the first report of a 0.1 /spl mu/m MHEMT device manufactured using the reflowed e-beam resist process for T-gate formation.     

InGaAsP thin-film microdisk resonators fabricated by polymer wafer bonding for wavelength add-drop filters

10-/spl mu/m-diameter InGaAsP thin-film microdisk resonators have been fabricated using polymer-wafer bonding with benzocylobutene. This wafer bonding process is to provide strong two-dimensional mode confinement in the waveguide and reduce the optical propagation loss. The measured resonance linewidth at wavelength 1.55 /spl mu/m is about 0.22 nm with a free-spectral range of 20 nm. The narrow linewidth and large free-spectral range make these devices conducive to the applications in dense wavelength division multiplexed systems.     

Highly coherent electronically tunable waveguide extended cavity diode laser

A frequency agile extended cavity diode laser using an integrated Bragg reflector in a Ti : Fe : LiNbO/sub 3/ waveguide is developed and characterized. The laser emits up to 7 mW in the 1.5-/spl mu/m telecommunication window. The emission spectrum exhibits a 18-kHz linewidth, >40-dB sidemode suppression ratio, and a wavelength stability of /spl plusmn/1 pm over hours. Very fast mode hop-free frequency tuning is achieved through the electrooptic effect, with a tuning slope of 55.5 MHz/V.     

Highly stable low-noise Brillouin fiber laser with ultranarrow spectral linewidth

We demonstrate an all-fiber high-power single-frequency Brillouin fiber ring laser with maximum power of 100 mW at 1.55 /spl mu/m, which is actively stabilized by using the Pound-Drever-Hall frequency-locking scheme. Significant reduction (/spl sim/20dB) of both relative intensity noise and frequency noise was observed in the Brillouin Stokes radiation as compared with those noises of its pump source, a narrow-linewidth Er-doped fiber laser. Ultranarrow spectral linewidth of the Brillouin fiber lasers was investigated by both delayed self-heterodyne technique and heterodyne beat technique between two independent Brillouin fiber lasers.     

A fully integratable 1.55-/spl mu/m wavelength continuously tunable asymmetric twin-waveguide distributed Bragg reflector laser

We demonstrate a single-frequency continuously tunable three-section distributed Bragg reflector laser operating at a center wavelength of /spl lambda//sub 0/=1.548 /spl mu/m using a fully integratable asymmetric twin-waveguide structure. A low-loss tapered mode transformer couples the light between the active waveguide, or gain region, and the passive ridge waveguide where the phase and grating tuning sections are located. The device has a threshold current of 50 mA and output power of nearly 13 mW, with a slope efficiency of 0.12 W/A and a tuning range of 4.8 nm under pulsed operation. An independent phase section is used to continuously tune the wavelength, thus avoiding mode hops. Using a delayed self-heterodyne technique, we determine the linewidth to be (146/spl plusmn/2) kHz.     

A 34-ns 1-Mbit CMOS SRAM using triple polysilicon

A 128-kb word/spl times/8-b CMOS SRAM with an access time of 3 ns and a standby current of 2 /spl mu/A is described. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-/spl mu/m minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transition detection (ATD) are used. This RAM has a flash-clear function in which logical zeros are written into all memory cells in less than 1 /spl mu/s.     

High-voltage regulation and process considerations for high-density 5 V-only E/SUP 2/PROM's

A high density 5-V-only HMOS 1 FLOTOX E/SUP 2/PROM technology has been developed using stepper lithography and dry etching techniques. A 1.5-/spl mu/m minimum feature size and 0.5-/spl mu/m registration result in a FLOTOX cell with an area of 270 /spl mu/m/SUP 2/. This represents a 50% reduction of the original cell size. Equivalent endurance (10K cycles) and data retention (10 years) have been obtained. Improved critical dimension control has increased the uniformity of the new cell within the array. Junction leakage has been reduced by using an extended low-temperature anneal cycle. Circuit techniques have been developed to ensure full temperature range (-55-125/spl deg/C) operation. A capacitive voltage divider in a feedback loop, an E/SUP 2/ trimmable voltage reference, and a switched-capacitor RC network are employed to produce a temperature-stable programming pulse with a rising edge time constant of ~ 600 /spl mu/s. The programming voltage can be trimmed with an accuracy of /spl plusmn/ 0.5 V over a typical range of 19-24 V in order to match the requirements of the array. 16K and 64K 5-V-only E/SUP 2/PROMs with die sizes of 128 /spl times/ 182 mil and 223 X 278 mil have been fabricated.     

An analog GFSK modulator in 0.35-/spl mu/m CMOS

An analog Gaussian frequency shift keying (GFSK) modulator designed in 0.35-/spl mu/m CMOS consumes 600 /spl mu/A from a 3-V supply and realizes an analog implementation of the FM differential equation. The modulator operates at baseband and is intended for use in a direct-conversion Bluetooth transmitter. It achieves a frequency deviation of 160 kHz with better than /spl plusmn/3% accuracy. The modulator implements an amplitude control loop to achieve a well-defined output swing. The total output harmonic distortion is less than 1%.     

A 10-Gb/s receiver with series equalizer and on-chip ISI monitor in 0.11-/spl mu/m CMOS

A 10-Gb/s receiver is presented that consists of an equalizer, an intersymbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The equalizer uses the Cherry-Hooper topology to achieve high-bandwidth with small area and low power consumption, without using on-chip inductors. The ISI monitor measures the channel response including the wire and the equalizer on the fly by calculating the correlation between the error in the input signal and the past decision data. A switched capacitor correlator enables a compact and low power implementation of the ISI monitor. The receiver test chip was fabricated by using a standard 0.11-/spl mu/m CMOS technology. The receiver active area is 0.8 mm/sup 2/ and it consumes 133 mW with a 1.2-V power supply. The equalizer compensates for high-frequency losses ranging from 0 dB to 20 dB with a bit error rate of less than 10/sup -12/. The areas and power consumptions are 47 /spl mu/m /spl times/ 85 /spl mu/m and 13.2 mW for the equalizer, and 145 /spl mu/m /spl times/ 80 /spl mu/m and 10 mW for the ISI monitor.     

Linewidth study of InAs-InGaAs quantum dot distributed feedback lasers

The linewidth of laterally loss-coupled distributed feedback (DFB) lasers based on InAs quantum dots (QDs) embedded in an InGaAs quantum well (QW) is investigated. Narrow linewidth operation of QD devices is demonstrated. A linewidth-power product less than 1.2 MHz /spl middot/ mW is achieved in a device of 300-/spl mu/m cavity length for an output power up to 2 mW. Depending on the gain offset of the DFB modes from the QD ground state gain peak, linewidth rebroadening or a floor is observed at a cavity photon density of about 1.2-2.4/spl times/10/sup 15/ cm/sup -3/, which is much lower than in QW lasers. This phenomenon is attributed to the enhanced gain compression observed in QDs.     

A 6.5-GHz energy-efficient BFSK modulator for wireless sensor applications

A 6.5-GHz FSK modulator suitable for low power wireless sensor network is presented. The energy efficient modulator employs closed-loop direct VCO modulation to achieve high data rate, multistage variable loop bandwidth technique for fast startup time and /spl Sigma/-/spl Delta/ for reduced power consumption in the synthesizer with fine resolution in frequency channel selection. The modulator, implemented using 0.25-/spl mu/m CMOS, achieves 20-/spl mu/s startup time with an effective data rate of 2.5 Mb/s while consuming 22 mW.     

A CMOS smart temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.5/spl deg/C from -50/spl deg/C to 120/spl deg/C

A low-cost temperature sensor with on-chip sigma-delta ADC and digital bus interface was realized in a 0.5 /spl mu/m CMOS process. Substrate PNP transistors are used for temperature sensing and for generating the ADC's reference voltage. To obtain a high initial accuracy in the readout circuitry, chopper amplifiers and dynamic element matching are used. High linearity is obtained by using second-order curvature correction. With these measures, the sensor's temperature error is dominated by spread on the base-emitter voltage of the PNP transistors. This is trimmed after packaging by comparing the sensor's output with the die temperature measured using an extra on-chip calibration transistor. Compared to traditional calibration techniques, this procedure is much faster and therefore reduces production costs. The sensor is accurate to within /spl plusmn/0.5/spl deg/C (3/spl sigma/) from -50/spl deg/C to 120/spl deg/C.     

Electroabsorption modulator using intersubband transitions in GaN-AlGaN-AlN step quantum wells

We calculate the high-speed modulation properties of an electroabsorption modulator for /spl lambda/=1.55 /spl mu/m based on Stark shifting an intersubband resonance in GaN-AlGaN-AlN step quantum wells. In a realistic simulation assuming an absorption linewidth /spl Gamma/=100 meV we obtain an RC-limited electrical f/sub 3dB//spl sim/60 GHz at an applied voltage swing V/sub pp/=2.8 V. We also show that a small negative effective chirp parameter suitable for standard single-mode fiber is obtained and that the absorption is virtually unsaturable. The waveguide is proposed to be based on the plasma effect in order to simultaneously achieve a strong confinement of the optical mode, a low series resistance, and lattice-matched cladding and core waveguide layers. Extrapolated results reflecting the decisive dependence of the high-speed performance on the intersubband absorption linewidth /spl Gamma/ are also given. At the assumed linewidth the modulation speed versus signal power ratio is on a par with existing lumped interband modulators based on the quantum confined Stark effect.