Trench transistor DRAM cell

A new one-transistor DRAM cell with both the transistor and the capacitor fabricated on the trench sidewalls is described. With the signal stored on the polysilicon node surrounded by oxide, the cell is expected to have a high alpha particle immunity. The cell occupies only 9 µm²using 1-µm design rules. This cell size is sufficiently small to enable a 4-Mbit DRAM of reasonable chip size with these design rules, and possesses further scalability for 16-Mbit DRAM's.     

A capacitorless double-gate DRAM cell

A capacitorless double-gate DRAM (DG-DRAM) cell is proposed in this study. Its dual gates and thin body reduce off state leakage and. disturb problems. Dopant fluctuations, which can be particularly important in high-density arrays, are avoided by using a thin, lightly doped body. The cell's large body coefficient ((dV_T)/(dV_BD) transforms small gains of body potential into increased drain current. MEDICI simulations for 85°C show that a DG-DRAM cell may sustain a measurable change in drain current several hundred milliseconds after programming. These characteristics suggest that a thin body, double-gate cell is an interesting candidate for high density DRAM technologies     

A 64-Mb DRAM with meshed power line

A 64-Mb dynamic RAM (DRAM) has been developed with a meshed power line (MPL) and a quasi-distributed sense-amplifier driver (qDSAD) scheme. It realizes high speed, t_RAS=50 ns (typical) at V_cc=3.3 V, and 16-b input/output (I/O). This MPL+qDSAD scheme can reduce sensing delay caused by the metal layer resistance. Furthermore, to suppress crosstalk noise, a V_SS shield peripheral layout scheme has been introduced, which also widens power line widths. This 64-Mb DRAM was fabricated with 0.4-μm CMOS technology using KrF excimer laser lithography. A newly developed memory cell structure, the tunnel-shaped stacked-capacitor cell (TSSC), was adapted to this 64-Mb DRAM     

A 512 Mb Two-Channel Mobile DRAM (OneDRAM) With Shared Memory Array

A 512 Mb two-channel mobile DRAM (OneDRAM) is developed with 90 nm technology. It can operate on a 1.8 V power supply as two separate mobile DDR or SDR DRAMs through each channel with maximum data rate of 333 Mbps/pin because of its exclusive accessibility from each channel to memory arrays. Data exchange between two channels is also possible by sharing one common memory array, and a new control scheme of DRAM for this sharing is proposed. The new control scheme is based on direct addressing mode to achieve compatibility with normal DRAM interface together with fast data transfer speed between two channels.      

An experimental DRAM with a NAND-structured cell

An experimental 256-Mb dynamic random access memory using a NAND-structured cell (NAND DRAM) has been fabricated. The NAND-structured cell has four memory cells connected in series, which reduces the area of isolation between the adjacent cells and also reduces the bit-line contact area. The cell area per bit measures 0.962 μm², using 0.4-μm CMOS technology, which is 63% in comparison with the conventional cell. In order to reduce the die size, time division multiplex sense-amplifier (TMS) architecture, in which a sense amplifier is shared by four bit lines, has been newly introduced. The chip area is 464 mm², which is 68% compared with the DRAM using the current cell structure. The data can be accessed by a fast-block-access mode up to 512 bytes as well as a random access mode. Typical 112-ns access time of the first data in a block and 30-ns serial cycle time are achieved     

A ferroelectric DRAM cell for high-density NVRAMs

The operation of a ferroelectric DRAM (dynamic random access memory) cell for nonvolatile RAM (NVRAM) applications is described. Because polarization reversal only occurs during nonvolatile store/recall operations and not during read/write operations, ferroelectric fatigue is not a serious endurance problem. For a 3-V power supply, the worst-case effective silicon dioxide thickness of the unoptimized lead zirconate titanate film studied is less than 17 Å. The resistivity and endurance properties of ferroelectric films can be optimized by modifying the composition of the film. This cell can be the basis of a very-high-density NVRAM with practically no read/write cycle limit and at least 10¹⁰ nonvolatile store/recall cycles     

A cell transistor scalable DRAM array architecture

Presents a new DRAM array architecture for scaled DRAMs. This scheme suppresses the stress bias for memory cell transistors and enables memory cell transistor scaling. In this scheme, the data "1" and data "0" are written to the memory cell in different timing. First, for all selected cells, data "1" is written by boosting wordline (WL) voltage. Second, after pulling down WL voltage to a lowered value, data "0" is written only for data "0" cells. This scheme reduces stress bias for the cell transistor to half of that of the conventional operation. The time loss for data "1" write is eliminated by parallel processing of data "1" write and sense amplifier activation. This scheme realizes fast cycle time of 50 ns. By adopting the proposed scheme, the gate-oxide thickness of the cell transistor is reduced from 5.5 to 3 nm, and the memory cell size is reduced to 87% in 0.13-μm DRAM generation. Moreover, the application of the oxide-stress relaxation technique to all row-path circuits as well as the proposed scheme enables high-performance DRAM with only a thin gate-oxide transistor     

A 4-Mbit DRAM with trench-transistor cell

An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.     

Leakage mechanisms in the trench transistor DRAM cell

The authors discuss a band-to-band tunneling mechanism in the trench transistor cell (TTC), which is used in Texas Instruments' 4-Mbit DRAM. This effect should be operative in the class of trench cells in which the charge is stored inside the trench and the substrate forms a capacitor plate. This effect does not compromise the functionality of the cell; in fact, it has the potential of improving the long-term reliability of the cell by preventing electrical overstress of the trench capacitor oxide     

A video codec LSI for high-definition TV systems withone-transistor DRAM line memories

A video codec LSI for high-definition television (HDTV) systems has been developed. By using a time-compressed integration encoding technique, it converts a 20.0-MHz bandwidth luminance signal and two 5.0-MHz chrominance signals into a compressed image signal at 48.6-MHz sampling frequency. It is useful in many HDTV application systems, such as 400-Mb/s digital transmission system, a video disk player system, or an analog transmission system. Over 288000 elements, including a 52-kb one-transistor DRAM (dynamic random access memory) line memory specially developed for this LSI, were integrated on a 12.16×12.10-mm² chip. A standard cell layout method and a 1.2-μm CMOS logic LSI process were used     

A sub-100 ns 256K DRAM with open bit line scheme

A 256K DRAM with a 34.1 mm/SUP 2/ die size and a typical access time of 70 ns has been fabricated by using a newly designed boosted high-level clock generator circuit and triple poly-Si processing. For two-cell array configurations and sensing schemes, the available signal and uncommon mode noise levels at the input terminal of the sense amplifiers were studied. It was concluded that the open bit line configuration was the better one for a high-speed 256 kbit DRAM with a small die size, and the device characteristics obtained confirmed this approach. The device can operate in the nibble mode with a 15-ns access time from a CAS clock and can be refreshed with CAS before RAS automatic refresh mode. The yield has been enhanced with optimized redundancy.     

DRAM reliability

Dynamic random access memory (DRAM) reliability is investigated for future DRAMs where small geometrical devices are used together with new materials and novel process technologies. Among the several items of DRAM reliability, the most important aspect to consider for DRAM reliability is infant mortality which is caused by process-induced defects including random defects. Since the process-induced defects are strongly dependent on process technology, it is inevitable to minimize process-induced defects by developing new process technology. However, whenever new process technology is introduced, new screening techniques or methods are necessary for suppressing infant mortality. The degradation of pMOSFET due to buried-channel pMOSFET during burn-in stress and soft error rate due to α-particle and cosmic ray irradiation become concerns as device dimension shrinks. However, it cannot be limitations of DRAM reliability because pMOSFET degradation due to hot electron induced puchthrough can be suppressed by new layout of pMOSFET, and the soft error events can be overcome by soft error resistant device structure and proper material choices. From these considerations, it can be expected that the advances of DRAM technology generation not only improve the device performance but also enhance the reliability.     

A block-oriented RAM with half-sized DRAM cell and quasi-foldeddata-line architecture

The authors describe a block-oriented random-access memory (BORAM) based on a series-connected cell concept and a quasi-folded data-line architecture. The series-connected cell concept allows a nearly half-sized DRAM cell even when using the same fabrication process as for conventional DRAMs. The low-noise quasi-folded data-line architecture allows the data-line capacitance to be one eighth the conventional value at the minimum, or the number of cells per amplifier to be 64 times the conventional number at the maximum. In addition, this architecture provides a more relaxed layout for the READ/WRITE circuits. The operation of four series-connected cells is observed successfully through a test device which includes a voltage-to-current conversion circuit, a current-mirror amplifier, and a 0.76-μm² crown-shaped stack-capacitor (STC) cell     

A new soft-error-immune DRAM cell using a stacked CMOS structure

A new VLSI memory cell is proposed that offers high immunity to alpha-particle-induced soft errors and a cell area comparable to a one-transistor memory cell. This memory cell consists of a pair of complementary MOSFET's and one capacitor. The PMOSFET is formed in an SOI film over the NMOSFET. Since both storage capacitor nodes are kept electrically floating in retention periods and one storage capacitor node is formed in a thin SOI film, an alpha-particle hit does not destroy the stored charge of this memory cell. It is sufficient for an SOI-PMOSFET to provide only three orders of magnitude ON/OFF current ratio. Experimental memory cells were fabricated using polysilicon film as an SOI film. Measuring them confirmed the main effectiveness of this memory cell.     

An experimental high-density DRAM cell with a built-in gain stage

A new high-density DRAM cell concept is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor, generates a large bit line signal with a small cell capacitance during the read cycle. Since it does not need a large storage capacitance and one transistor is stacked on the top of the other transistor, the cell size is small and can be easily scaled down for future generations of memory devices. The unit cell size fabricated using a 4 M SRAM process without any process modification is 1.8 μm×2.85 μm. The proposed cell can be adopted to store multi-bit information. The fabricated prototype cell shows a resolution of about 3.5 bit     

Partial SOI type isolation for improvement of DRAM cell transistor characteristics

A new DRAM cell transistor using an isotropic etching under the storage node is proposed, and it is shown that the structure gives improvement both in the short-channel effect and in the body-bias control. The asymmetrical characteristics of the structure are analyzed by experiments and simulation, and the feasibility of utilizing the asymmetric characteristics is reported.     

A vertically integrated GaAs bipolar/FET DRAM cell with internalgain

The authors describe a novel dynamic memory cell incorporating a p-n junction storage capacitor, bipolar write-access transistor (BJT), and a junction field-effect transistor (JFET) for nondestructive readout with internal gain. The bipolar transistor is vertically integrated over the storage capacitor and the JFET is formed from the base region of the BJT. Internal gain improves the signal-to-noise ratio and eliminates the requirement that a specific number of electrons be stored in the cell for reliable readout     

DRAM价格不稳

据iSuppli公司追踪报道,美国DRAM现货价格经过表1 美国DRAM现货价格走势 (单位:美元)连续6周的下跌后,终于从5月26日开始的5月最后一周出现回升。128MbDDR266SDRAM价格增长近3%,达到每块1.73美元,256Mb的333产品也增长1.6%,达3.15美元。但供应商还不能就比轻松起来。6月的DRAM价格历史上一向不好。自1991年以来,6月DRAM按bit计算,尽管出货量增长14%,而价格则平均下降8%。因此iSuppli预计,6月需求将呈呆滞局面,加之6月是大多公司的会计季度,希望多销产品以完成营收计划,从而导致…     

16兆位DRAM

<正> 据日本《JEE》杂心1983年3月号报道,松下、日立和东芝公司宣布制成16兆位DRAM样机,在一块芯片上可集成约3400万只晶体管。 松下公司采用线宽0.5μm技术及开型位线方法,形成1.5×2.2μm的存储单元,以位线和字线相交处形成的沟道环绕之。为了实现这一结构,该公司在每256条实字线处采用赝字线用以消除耦合噪音,为有较高的密度,在每两条位线上排列一个读出放大器。它采用包括水溶性聚合物和γ射线步进机的4层保护膜。松下公司宣布了16兆字×1位和4兆字×4位结构的器件,这两种芯片的尺寸为5.4×17.38mm,存取时间为65毫微秒。     

A 1-Gb SDRAM with ground-level precharged bit line and nonboosted2.1-V word line

This paper describes the key technologies used in a 1-Gb synchronous DRAM. This DRAM was developed according to a new cell-operating concept in which a ground-level (V_ss) precharged bit line with a negative word-line reset scheme enables a nonboosted 2.1-V word-line architecture. Total power consumption is less than that of the conventional half-V_cc precharged bit-line scheme. We also propose a vernier-type, high-accuracy delay-locked-loop circuit realizing ±20-ps quantization errors for clock recovery and skew elimination