A Micropower Chopper-Stabilized Operational Amplifier Using a SC Notch Filter With Synchronous Integration Inside the Continuous-Time Signal Path

A micropower chopper stabilized opamp is presented. The new topology incorporates a switched capacitor filter with synchronous integration inside the continuous time signal path virtually eliminating chopping noise. A three-stage amplifier with multipath nested Miller compensation is modified to incorporate chopping of the input stage, sinc filtering to notch any chopping ripple, and a compensation scheme to maintain an undistorted high-speed signal path. Characteristics of the amplifier presented include rail to rail input and output operating on supplies of 1.8 to 5.5 V over -40degC to 125degC. Quiescent supply current is 17 muA, input offset is 3 muV, input offset drift is 0.02 muV/degC, GBW is 350 kHz, and the chopping frequency is 125 kHz. Die area is 0.7 mm² using a precision analog mixed-signal CMOS process combining low-noise 0.6-mum analog transistors with 0.3-mum digital CMOS capability     

A Programmable 210-μV Offset Rail-to-Rail Gm –C Filter

Low input-referred offset performance and linearity in analog filters are critical design parameters, yet transistor mismatch limitations are a severe hindrance. Programmability is also a feature of growing significance because high performance state-of-the-art systems must adapt on-the-fly to various operating conditions, as is the case in battery-operated electronics where systems traverse through idle, alert, and high performance modes in an effort to conserve energy and extend battery life. This paper presents a continuous and programmable first-order G_m-C filter with sub-millivolt offset performance. Low offset is achieved by auto-zeroing and continuity by ping-ponging between two transconductors, all under the construct of a compact and bandwidth-efficient circuit topology. The proposed G_m-C circuit was fabricated with AMI's 0.5-mum CMOS process technology and achieved an input-referred offset of less than 210 muV, hand-over glitches of less than 40 mV, and 57 dB of linearity over the rail-to-rail input span for a lithium-ion battery supply range of 3 to 4.2 V. The bandwidth and gain of the filter were programmable from 1.1 to 6.5 kHz and 1.27 to 29.1 V/V, respectively, both with better than 3.2% resolution.     

A Precision CMOS Amplifier Using Floating-Gate Transistors for Offset Cancellation

A long-term offset cancellation scheme that enables continuous-time amplifier operation is described. Offset cancellation is achieved by programming floating-gate transistors that form an integral part of the amplifier's architecture. The offset voltage of a single-stage folded cascode amplifier has been programmed to a minimum of plusmn25 muV in a 0.5 mum digital CMOS process. The long-term offset voltage drift has been calculated to be less than 0.5 muV over a period of 10 years at 55degC from a thermionic emission model for floating-gate charge loss. The offset voltage varies by a maximum of 130 muV over a temperature range of 170degC, thereby making this a viable approach to offset cancellation     

A Readout Channel Optimized for Minimum NEP of a FET-Based THz Pixel

This paper presents a high-gain, noise-efficient readout interface for a FET-based direct THz detector fabricated in 0.15 μm standard CMOS technology. The pixel, conceived to be used in array configuration for an imaging application, consists of an on-chip antenna, a FET device for THz signal detection and a chopper-stabilized readout interface performing in-pixel filtering and amplification. The switched-capacitor multistage design achieves a closed-loop gain of 70 dB and a system bandwidth of 1 kHz, thereby improving the SNR and limiting the total integrated input referred noise of the channel to less than the minimum detectable signal limit defined by the FET detector. The measurement results show that the pixel is able to achieve a maximum voltage responsivity of 470 kV/W and a minimum NEP value of 480 pW/√Hz at the antenna frequency of 370 GHz. The pixel consumes 200 μW power, and it occupies an area of 0.375mm².     

Frequency division multiplexed microwave and baseband digitaloptical fiber link for phased array antennas

A frequency-division multiplexed optical fiber link is described in which microwave (1-8 GHz) and baseband digital (1-10 Mb/s) signals are combined electrically and transmitted through a direct-modulation microwave optical link. The microwave signal does not affect bit error rate (BER) performance of the Manchester-coded baseband digital data link. The baseband digital signal affects microwave signal quality by generating second-order intermodulation noise. The intermodulation noise power density is found to be proportional to both the microwave input power and the digital input power, enabling the system to be modeled as a mixer (AM modulator). The conversion loss for the digital signal is approximately 68 dB for a 1-GHz microwave signal and is highly dependent on the microwave frequency, reaching a minimum value of 41 dB at 4.5 GHz corresponding to the laser diode relaxation oscillation frequency. It is shown that Manchester coding on the digital link places the intermodulation noise peak away from microwave signal, preventing degradation of close-carrier phase noise (<1 kHz offset). A direct trade-off between intermodulation noise and digital link margin is developed to project system performance     

Chopper Stabilization of Analog Multipliers, Variable Gain Amplifiers, and Mixers

We describe a general offset-canceling architecture for analog multiplication using chopper stabilization. Chopping is used to modulate the offset away from the output signal where it can be easily filtered out, providing continuous offset reduction which is insensitive to drift. Both square wave chopping and chopping with orthogonal spreading codes are tested and shown to reduce the offset down to the microvolt level. In addition, we apply the nested chopping technique to an analog multiplier which employs two levels of chopping to reduce the offset even further. We discuss the limits on the performance of the various chopping methods in detail, and present a detailed analysis of the residual offset due to charge injection spikes. An illustrative CMOS prototype in a 0.18 mum process is presented which achieves a worst-case offset of 1.5 muV. This is the lowest measured offset reported in the DC analog multiplier literature by a margin of two orders of magnitude. The prototype multiplier is also tested with AC inputs as a squarer, variable gain amplifier, and direct-conversion mixer, demonstrating that chopper stabilization is effective for both DC and AC multiplication. The AC measurements show that chopping removes not only offset, but also 1/f noise and second-order harmonic distortion.     

S-band erbium-doped fiber amplifiers with a multistage configuration /sub e/sign, characterization, and gain tilt compensation

We report an S-band erbium-doped fiber amplifier (EDFA) with a multistage configuration in terms of its design, gain, and noise characteristics for various pump powers and input signal powers, the temperature dependence of the gain spectra, and gain tilt compensation for changes in input signal power and temperature change. We show that there is a tradeoff between low noise and efficiency in the S-band EDFA and describe the development of an S-band EDFA with a flattened gain of more than 21 dB and a noise figure of less than 6.7 dB. We also show that there is a change in the gain spectra with changes in the pump power and input signal power that is different from that observed in C- and L-band EDFAs, and that our EDFA has a temperature-insensitive wavelength. Furthermore, we develop a gain tilt compensated S-band EDFA that can cope with changes in input signal power and temperature.     

10 GHz full-rate clock and data recovery circuit in 0.18 /spl mu/m CMOS without external reference clock

The design of a fully monolithic integrated 10 GHz full-rate clock and data recovery (CDR) circuit in 0.18 /spl mu/m digital CMOS technology, which employs an injection phase-locked loop (PLL) technique is presented. The CDR operating without the external reference exhibits a capture range of 200 MHz while consuming 205 mA current from 1.8 V supply including the output buffer. The recovered clock signal with 250 mV/sub pp/ pseudorandom bit Sequence input data of length 2/sup 31/-1 exhibits 7.9 ps of peak-to-peak (p-p) and 1.1 ps of root-mean-square (RMS) jitter. The measured clock phase noise at 1 MHz offset is approximately -109 dBc/Hz.     

Performance analysis of optimised CMOS comparator

A high-speed low-power latched CMOS comparator circuit is presented. Demonstrated is a circuit optimisation technique to obtain minimum offset error at 500 MHz sampling speed. Also, a mathematical model representing the noise in the device is developed. After optimisation, the comparator achieved 10-bit resolution on a 1 V differential input at 500 MHz speed and had a noise figure of 4.747 dB at this frequency.     

A floating-gate comparator with automatic offset adaptation for 10-bit data conversion

We present a novel voltage comparator that uses nonvolatile floating-gate charge storage for either offset ing or automatic programming of a desired offset. We exploit the negative feedback mechanism of pFET hot-electron injection to achieve fully automatic offset cancellation. The adaptation guarantees an input offset less than the input-referred noise level regardless of initial device offset for a typical 8.3% observed injection mismatch. In addition, we demonstrate the ability to accurately program a desired offset. The design has been fabricated in a commercially available 0.35-/spl mu/m process. Experimental results confirm the ability to reduce the variance of the initial offset by two orders of magnitude and to accurately program a desired offset with maximum observed deviation 728 /spl mu/V and typical deviation 109 /spl mu/V. The mean offset is reduced by a factor of 416 relative to fabricated chips directly from the foundry and by a factor of 202 relative to UV-irradiated chips. Adaptation is fast, with settling time typically under 50 ms and scaling inversely with the exponential of the injection voltage. We achieve controlled injection to accurately program the input offset to voltages uniformly distributed from -1 to 1 V. The comparator exhibits a 5 ns propagation delay and consumes 270 /spl mu/W.     

A frequency multiplier for reference frequency in frequency synthesizer systems

A low jitter frequency multiplier, which requires less power, area, and design complexity than reference multiplying PLL or DLL circuits can be used to generate the reference frequency for a low phase noise frequency synthesizer. This paper proposes a mixed signal solution based on the fact that the average DC value of a signal is proportional to its duty cycle. The solution uses a feedback loop with coarse and fine delay resolution to generate a \(90^{\circ }\) phase shifted clock that is used to produce a doubled frequency signal with 50% duty cycle. This method can be used to multiply the input frequency of 40 MHz by multiples of 2, up to 16. The design is implemented in 65 nm UMC CMOS process. Operating from 1.2-V supply, it dissipates 0.46 to 1.2 mA at output frequencies 80–640 MHz, achieving ? 162.3 and ? 139 dBc/Hz phase noise at 1 MHz offset, respectively.     

A High-Speed Low-Noise CMOS Image Sensor With 13-b Column-Parallel Single-Ended Cyclic ADCs

A high-performance CMOS image sensor (CIS) with 13-b column-parallel single-ended cyclic ADCs is presented. The simplified single-ended circuits for the cyclic ADC are squeezed into a 5.6-mum-pitch single-side column. The proposed internal reference generation and return-to-zero digital signal feedback techniques enhance the ADC to have low read noise, a high resolution of 13 b, and a resulting dynamic range of 71 dB. An ultralow vertical fixed pattern noise of 0.1 e_rms ^- is attained by a digital CDS technique, which performs A/D conversion twice in a horizontal scan period (6 mus). The implemented CIS with 0.18-mum technology operates at 390 frames/s and has 7.07-V/lx middots sensitivity, 61- muV/e^- conversion gain, 4.9-e_rms ^- read noise, and less than 0.4 LSB differential nonlinearity.     

Criteria for setting the width of CCD front end transistor to reachminimum pixel noise

The paper gives the criteria to calculate the width of the front end transistor integrated next to the charge sensing electrode of CCDs or, in general, of semiconductor detectors, in order to reach the minimum noise in the readout of the signal charge. It accounts for white, series and parallel, and 1/f noise contributions. In addition, it points out two different design criteria depending whether a JFET or a MOSFET is used. The attention given to the JFET is due to a lower 1/f noise component, which makes these transistors more appealing as input devices in very high resolution detectors. The paper shows that there is a characteristic width of the FET gate that practically does not depend on the noise sources but depends only on the capacitance seen by the charge sensing electrode of the detector, making possible the optimum design of the transistor prior to knowledge of the real values of the spectral density of the noise sources, which are usually precisely known only at the end of the fabrication process. The paper shows that the pixel noise raises sharply as the transistor gate width departs from its optimum value     

A MOS switched-capacitor instrumentation amplifier

Describes a precision switched-capacitor sampled-data instrumentation amplifier using NMOS polysilicon gate technology. It is intended for use as a sample-and-hold amplifier for low level signals in data acquisition systems. The use of double correlated sampling technique achieves high power supply rejection, low DC offset, and low 1/f noise voltage. Matched circuit components in a differential configuration minimize errors from switch channel charge injection. Very high common mode rejection (120 dB) is obtained by a new sampling technique which prevents the common mode signal from entering the amplifier. This amplifier achieves 1 mV typical input offset voltage, greater than 95 dB PSRR, 0.15 percent gain accuracy, 0.01 percent gain linearity, and an RMS input referred noise voltage of 30 /spl mu/V/input sample.     

A high-speed multimodulus HBT prescaler for frequency synthesizerapplications

A high-speed variable modulus prescaler that divides the input clock frequency by 128 up to 255 with unit step increment has been implemented with heterojunction bipolar transistor (HBT) technology. A maximum operating frequency of 9.72 GHz with power consumption of 650 mW has been measured. The high-speed performance is attributed to the circuit design, which minimizes the critical path delay, and the intrinsic high-speed characteristics of HBT technology. The phase noise of the prescaler is important for frequency synthesizer applications. With 6.24-GHz input frequency, the phase noise was -110 dBc/Hz at 100-Hz offset frequency and -120 dBc at 1-kHz offset frequency. The noise floor decreases as the input frequency decreases. Phase noises of -125 dBc/Hz at 100-Hz offset and -135 dBc/Hz at 1-kHz offset were obtained for a 1.2-GHz input frequency     

Sub-1-V design techniques for high-linearity multistage/pipelined analog-to-digital converters

The design of an ultra-low-voltage multistage (two-stage algorithmic) analog-to-digital converter (ADC) employing the opamp-reset switching technique is described. A highly linear input sampling circuit accommodates truly low-voltage sampling from external input signal source. A radix-based digital calibration technique is used to compensate for component mismatches and reduced opamp gain under low supply voltage. The radix-based scheme is based on a half-reference multiplying digital-to-analog converter structure, where the error sources seen by both the reference and input signal paths are made identical for a given stage. The prototype ADC was fabricated in a 0.18-/spl mu/m CMOS process. The prototype integrated circuit dissipates 9 mW at 0.9-V supply with an input signal range of 0.9 V/sub p-p/ differential. The calibration of the ADC improves the signal-to-noise-plus-distortion ratio from 40 to 55 dB and the spurious-free dynamic range from 47 to 75 dB.     

A CMOS chopper amplifier

A highly sensitive CMOS chopper amplifier for low-frequency applications is described. It is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique. The circuit has been integrated in a 3-/spl mu/m p-well CMOS technology. The chopper amplifier DC grain is 38 dB with a 200-Hz bandwidth. The equivalent input noise is 63 nV//spl radic/Hz and free from 1/f noise. The input offset is below 5 /spl mu/V for a tuning error less than 1%. The amplifier consumes only 34 /spl mu/W.     

On the reduction of thermal and flicker noise in ENG signal recording amplifiers

Because of the extremely low amplitude of the input signal, the design of electro-neuro-graph (ENG) amplifiers involves a special care for flicker and thermal noise reduction. The task becomes really challenging in the case of implantable electronics, because power consumption is restricted to few hundreds μW. In this work, two different circuit techniques aimed to reduce flicker and thermal noise, in ultra-low noise amplifiers for implantable medical devices, are demonstrated. The circuit design, and measurement results are presented, in both cases showing an excellent performance, and noise to power consumption trade-off. In the first circuit, a very simple low-pass G_m–C chopper amplifier is used for flicker noise cancellation. It consumes only 28 mW, with a measured input referred noise and offset of 2  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ , and 2.5 μV, respectively. In the second circuit, a ultra-low noise amplifier, a energy-efficient DC–DC down-converter, and low voltage design techniques are combined, for the reduction of thermal noise with a minimum power consumption. Measured input referred noise in this case was 5.5  $ {{{\text{nV}}} \mathord{\left/ {\vphantom {{{\text{nV}}} {\sqrt {{\text{Hz}}} }}} \right. \kern-0em} {\sqrt {{\text{Hz}}} }} $ at only 380 μW power consumption. Both circuits were fabricated in a 1.5 μm technology.     

基于斩波技术的CMOS运算放大器失调电压的消除设计

实现传感器系统的高分辨率,要求其内部运算放大器具有低失调电压和低噪声的性能,为此介绍了一种可减少运算放大器的失调电压和低频噪声的斩波技术,并基于该技术进行温度传感器中CMOS运算放大电路失调电压的消除设计,最后通过SPICE仿真分析来权衡电路各参数的设定。     

A programmable instrumentation amplifier for 12-bit resolution systems

Describes the design of and experimental results obtained from a monolithic gain-programmable instrumentation amplifier that attains performance compatible with 12-bit or higher resolution data acquisition systems. Nonlinearity is held to a 0.01 percent worst-case level over the -25 to 85/spl deg/C temperature range for gains of 1-1000, independent of process variations. Input and output voltage noise and offset drift are also reduced to low levels. A novel input overvoltage protection scheme is also described. The amplifier is fabricated on a standard-beta junction isolated bipolar process that has in addition process-compatible ion implanted JFETs and silicon-chromium thin-film resistors.