倒装芯片焊点可靠性的有限元模拟法探讨

随着集成电路封装技术的发展,倒装芯片技术得到广泛应用.由于材料的热膨胀失配,使倒装焊点成为芯片封装中失效率最高的部位,而利用快捷又极具参考价值的有限元模拟法是研究焊点可靠性的重要手段之一.简单介绍了集成电路芯片焊点可靠性分析的有限元模拟法,重点概括了利用该方法对芯片焊点进行可靠性评价常见的材料性质和疲劳寿命预测模型.     

倒装芯片焊点可靠性的有限元模拟法综述

随着集成电路封装技术的发展,倒装芯片技术得到广泛的应用。由于材料的热膨胀失配,使倒装焊点成为芯片封装中失效率最高的部位,而利用快捷又极具参考价值的有限元模拟法是研究焊点可靠性的重要手段之一。介绍了集成电路芯片焊点可靠性分析的有限元模拟法,概括了利用该方法对芯片焊点进行可靠性评价常见的材料性质和疲劳寿命预测模型。     

焊盘尺寸对FC—PBGA焊点可靠性的影响

影响封装可靠性的因素很多,其中对封装及供货厂商相关的封装设计方面的各种变量应该给予足够的重视。焊盘尺寸是影响焊点可靠性的关键因素之一,不同供货厂商的各种工艺造成焊盘尺寸方面的差异,对可靠性造成了极大的影响。有限元应力分析、波纹干涉测量试验及可靠性试验表明,基板厚度影响封装可靠性。文章采用有限元模拟来定量分析焊盘尺寸对PBGA封装可靠性的影响,把空气对空气热循环试验结果与FEM预测进行比较,讨论最佳焊盘尺寸,并预测对焊点可靠性的影响。     

Solder Joint Reliability Assessment for Flip Chip Ball Grid Array Components with Various Designs in Lead-Free Solder Materials and Solder Mask Dimensions

This study investigates the reliability of flip chip ball grid array (FCBGA) components with three types of solder materials: eutectic solder with a composition Sn63Pb37 and the lead-free solders SnAg3.0Cu0.5 and SnAg4.0Cu0.5. Two substrate-side solder mask (S/M) opening sizes, 0.4 mm and 0.525 mm, were used. Both the monotonic and cyclic mechanical four-point bend tests are conducted for the reliability assessment. It is found that the FCBGA components with SnAg3.0Cu0.5 solder have the best durability during the cyclic bend test, yet the eutectic solder is the strongest during the monotonic bend test. Besides, the FCBGA components with 0.525-mm S/M opening have around 3 times more life cycles than those with the 0.4-mm S/M opening in the cyclic bend test. It is also noteworthy that the lead-free solder materials have much variation in the failed cycles during the cyclic test. Moreover, the failure locations for those components with 0.4-mm S/M openings are found to be at the interface between the package side metal pad and the solder ball, and those with an S/M opening of 0.525 mm are observed to be failed mostly at the interface between the printed circuit board (PCB) side metal pad and the solder ball.     

Effect of Size of Lid-Substrate Adhesive on Reliability of Solder Balls in Thermally Enhanced Flip Chip PBGA Packages

Six design cases of lid-substrate adhesive with various combinations of widths and heights were analyzed to investigate how the size of the adhesive affects the reliability of the solder balls of thermally enhanced flip chip plastic ball grid array (FC-PBGA) packages in thermal cycling tests. Analysis results were compared with data on the reliability of conventional FC-PBGA packages. Thermal-mechanical behavior was simulated by the finite element (FE) method and the eutectic solder was assumed to exhibit elastic-viscoplastic behavior. The temperature-dependent nonlinear stress/strain relationship of the adhesive was experimentally determined and used in the FE analysis. Darveaux's model was employed to obtain the predicted fatigue life of the solder ball. Simulation results reveal that the fatigue life of the solder balls in thermally enhanced FC-PBGA packages is much shorter than that in conventional FC-PBGA packages, and the life of solder balls increases with both the width and the height of the adhesive. However, the effect of the width of the adhesive on the reliability of the solder ball is stronger than that of the height. Moreover, increasing either the width or the height reduces the plastic strain in the adhesive at critical locations, indicating that the reliability of the adhesive can be improved by its size. The predicted results of the life of solder balls for some selected studied packages are also compared with experimental data from thermal cycling tests in the paper     

有机印制板上倒装芯片的可靠性研究

对一种有机印制板上倒装芯片（Ｆｌｉｐｃｈｉｐ）进行温度循环试验,测出其失效分布曲线,然后通过扫描声显微镜、红外显微镜和剖面等失效分析手段,发现失效模式主要是合金焊点中的断裂以及下部填充料（Ｕｎｄｅｒｆｉｌ）中的损伤如分层（Ｄｅｌａｍｉｎａｔｉｏｎ）和内部裂缝（Ｃｒａｃｋ）。详细地阐述了倒装芯片中的下部填充料损伤在温度循环试验条件下的产生、发展及它们对合金焊点可靠性的影响。     

Thermomechanical Reliability Study of Flip Chip Solder Bumps: Using Laser Ultrasound Technique and Finite Element Method

Current techniques for nondestructive quality evaluation of solder bumps in electronic packages are either incapable of detecting solder bump cracks, or unsuitable for in-line inspection due to high cost and low throughput. As an alternative, a solder bump inspection system is being developed at Georgia Institute of Technology using laser ultrasound and interferometric techniques . This system uses a pulsed Nd:YAG laser to induce ultrasound in electronic packages in the thermoelastic regime; it then measures the transient out-of-plane displacement responses on the package surfaces using laser interferometric technique. The quality of solder bumps in electronic packages is evaluated by analyzing the transient responses. This paper presents a systematic study on thermomechanical reliability of flip chip solder bumps using laser ultrasound–interferometric inspection technique and finite element (FE) method. The correlation between the failure parameter extracted from FE simulation for evaluating solder bump reliability and quality degradation characterization of solder bumps through noncontact, nondestructive laser ultrasound testing has also been investigated.      

焊料凸点式倒装片与引线键合成本比较分析

文章讨论了引线键合芯片与板上或有机基板上焊料凸点式倒装片的成本比较问题。核查了IC芯片效率、金丝与焊接材料及这些技术使用的主要设备对成本的影响。采用有用的公式和图表,确定成本,并比较了采用这些技术的成本状况。     

形成倒装芯片焊点的铜接线柱焊凸(SBC)法

在倒装芯片应用中生长晶圆焊凸的工艺中对于间距较小(即小于150μm)、具有数个尺寸为150μm的焊凸,倒装前的焊锡涂敷好坏对产品的良率和可靠性起着重要作用。因为,如果涂敷的焊锡体积不均匀,就经不起涂敷过程中为确保涂敷在引线框上焊锡的完整和体积一致性而引入的强制视像系统检查,从而降低产出率。这就是一些组装工艺正设法减少或取消这些限制的原因。另一方面,采用直接熔化焊凸的方法来形成焊点是一种速度较快的工艺,但在保证回流处理后的离板高度方面有缺点,导致在温度和功率循环测试中的表现较差。介绍的采用铜接线柱焊凸(SolderBumponCopperStud;SBC)法解决了这些问题;对于那些需要倒装的组装工艺而言,这是可保障其制造性较佳的解决方案。介绍采用铜接线柱焊凸(SBC)工艺在附着在倒装芯片上的金属基片和焊凸之间形成焊点的新方法,利用铜接线柱焊凸技术再配合晶圆级的焊锡丝印工艺在半导体上预先形成焊凸。这是替代电镀焊凸工艺一种别具成本效益的方法。     

无铅倒装焊封装工艺中的芯片应力及开裂分析

采用粘塑性Garofalo-Arrhenius模型描述无铅焊料的非弹性力学行为,确定了Sn3.5Ag焊料该模型的材料参数。采用与固化过程相关的粘弹性力学模型描述倒装焊底充胶的力学行为。利用有限元仿真的方法,模拟了无铅倒装封装器件封装的工艺及可靠性测试。结果表明:由于无铅技术在封装中的引入,芯片破裂的可能性随之增加,破裂出现时裂纹的尺寸更小。     

Materials and Processes Issues in Fine Pitch Eutectic Solder Flip Chip Interconnection

New product designs within the electronics packaging industry continue to demand interconnects at shrinking geometry, both at the integrated circuit and supporting circuit board substrate level, thereby creating numerous manufacturing challenges. Flip chip on board (FCOB) applications are currently being driven by the need for reduced manufacturing costs and higher volume robust production capability. One of today's low cost FCOB solutions has emerged as an extension of the existing infrastructure for surface mount technology and combines an under bump metallization (UBM) with a stencil printing solder bumping process, to generate mechanically robust joint structures with low electrical resistance between chip and board. Although electroless Ni plating of the UBM, and stencil printing for solder paste deposition have been widely used in commercial industrial applications, there still exists a number of technical issues related to these materials and processes as the joint geometry is further reduced. This paper reports on trials with electroless Ni plating and stencil paste printing and the correlation between process variables in the formation of bumps and the shear strength of said bumps at different geometries. The effect of precise control of tolerances in squeegees, stencils and wafer fixtures was examined to enable the optimization of the materials, processes, and tooling for reduction of bumping defects     

Characteristics of Sn–Cu Solder Bump Formed by Electroplating for Flip Chip

Sn–Cu near eutectic solder bump was fabricated by electroplating for flip-chip, and its electroplating and bump characteristics were studied. A Si-wafer was used as a substrate and the under bump metallization (UBM) comprised 400 nm of Al, 300 nm of Cu, 400 nm of Ni, and 20 nm of Au sequentially from bottom to the top of the metallization. The electrolyte for plating Sn–Cu solder consisted of$hbox Sn^+2$(concentration of 30 g/L) and$hbox Cu^+2$(0.3 g/L) solutions with methasulfonic acid and deionized water. The experimental results showed that the plating ratio of the Sn–Cu increased from 0.25 to 2.7$mu/hbox min$with increasing current density from 1 to 8$hbox A/dm^2$. In this range of current density, the plated Sn–Cu maintained its composition nearly constant level as Sn-(0.9$sim$1.4)wt% Cu. The solder bump of typical mushroom shape with 120-$muhbox m$stem diameter and 75-$muhbox m$height was formed by plating at 5$hbox A/dm^2$for 2 h. The mushroom bump changed its shape to the hemispherical type of 140-$muhbox m$diameter by air reflow on a hot plate at 260$^circhbox C$. The homogeneity of element distribution in the solder bump was examined, and Sn content in the mushroom bump appears to be uneven changed to more uniform after the air reflow. The highest shear bond strength of the Sn–Cu hemispherical bump showed 113 gf by reflowing at 260$^circhbox C$for 10 s.     

军用倒装焊器件底部填充胶选型及验证方法讨论

从分析倒装焊器件底部填充的必要性入手,对底部填充胶的选型流程、选型基本方法及重点参数匹配情况进行了分析,优选出4款底部填充材料。通过对4款材料关键参数的理论计算及恒定加速度、热力学耦合仿真计算,优选出一种材料作为样本材料。同时对底部填充材料验证内容进行了梳理,通过试验验证摸索出材料的适用范围及边界条件。该底部填充胶的选型验证方法对于军用混合集成电路其他聚合材料的选型具有一定的指导意义。     

Electromigration in the Flip Chip Solder Joint of Sn-8Zn-3Bi on Copper Pads

Electromigration in Sn-8Zn-3Bi flip chip solder bumps on Cu pads has been studied at 120°C with an average current density of 4 × 10³ A/cm² and 4.5 × 10⁴ A/cm². Due to the polarity effect, the thickness of the intermetallic compound Cu-Zn (γ-phase) formed at the anode is much greater than that at the cathode. The solder joint fails after 117 h of stressing at 4.5 × 10⁴ A/cm², and void formation at the cathode can clearly be seen after polishing. However, it is the melting at the edge of the bump that causes the solder joint to fail. A simulation of the current density distribution indicates that the current density is not distributed uniformly, and current crowding occurs inside the bump. The results indicate that the increase of current density associated with Joule heating has affected melting and enhanced damage in the solder joint during electromigration.     

无铅倒装焊点的热应力与湿热应力分析

板上倒装芯片（FCOB）作为一种微电子封装结构形式得到了广泛的应用。微电子塑封器件中常用的聚合物因易于吸收周围环境中的湿气而对封装本身的可靠性带来很大影响。文章采用有限元软件分析了潮湿环境下板上倒装芯片下填充料在湿敏感元件实验标准MSL-1条件下（85℃／85％RH、168h）的潮湿扩散分布,进而分别模拟计算出无铅焊点的热应力与湿热应力,并加以分析比较。论文的研究成果不仅对于塑封电子元器件在潮湿环境中的使用具有一定的指导意义,而且对于FCOB器件在实际应用中的焊点可靠性问题具有一定的参考价值。     

Design of Solder Joint Structure for Flip Chip Package with an Optimized Shear Test Method

The structure of flip chip solder bumps was optimized in terms of shear height and shear speed using a shear test method with both experimental investigation and nonlinear, three-dimensional, finite element analysis being conducted. A representative, Pb-free solder composition, Sn-3.0Ag-0.5Cu, was used to optimize the shear test of the flip chip solder joints. Increasing the shear height, at a fixed shear speed, decreased the shear force, as did decreasing the shear speed, at a fixed shear height. These experimental and computational results supported the recommendation of low shear height and low shear speed condition for the shear testing of flip chip solder bumps. This optimized shear test method was applied to investigate the effect of various heights of mini bumps on the shear force of the solder joints. The shear force increased with increasing Ni-P mini bump height.     

倒装芯片底部填充工艺

从热疲劳故障的角度论述了倒装芯片底部填充的必要性,介绍了倒装芯片底部填充的参数控制。通过正确的底部填充,可提高倒装芯片组装的成品率和可靠性。     

空洞对功率芯片粘贴焊层热可靠性影响的分析

采用有限元方法,建立了功率器件封装的三维有限元模型,分析了封装体的温度场和应力场,讨论了芯片粘贴焊层厚度、空洞等因数对大功率器件封装温度场和应力场的影响.有限元结果表明,封装体的最高温度为73.45℃,位于芯片的上端表面,焊层热应力最大值为171 MPa,出现在芯片顶角的下面位置.拐角空洞对芯片最高温度影响最大,其次是中心空洞.空洞沿着对角线从中点移动到端点,芯片最高温度先减小后增加.焊层最大热应力出现在拐角空洞处,最大值为309 MPa.最后分析了芯片粘贴工艺中空洞形成的机理,并根据有限元分析结论对工艺的改善优化提出建议.     

实施倒装芯片的组装

成功的倒装芯片组装要求在焊剂应用、贴装设备、再流焊接、底部填充、密封剂密封和固化等方面予以特别的考虑.     

Study of Flip Chip Solder Joint Cracks Under Temperature Cycling Using a Laser Ultrasound Inspection System

The current techniques for nondestructive quality evaluation of bumped solder joint connections in electronics packages are either incapable of detecting solder joint cracks, or unsuitable for inline inspection due to cost and throughput reasons. As an alternative, a novel solder joint inspection system is being developed. The system projects short laser pulses onto specimen surface through optic fibers to induce structural vibration. The induced surface displacements are then measured by a laser Doppler vibrometer. A number of digital signal processing algorithms, such as error ratio and correlation coefficient, were used to analyze the vibration responses and identify defective specimens. This paper presents a systematic study of parameters such as error ratio, correlation coefficient, resonant frequency, electrical resistance, and the extension of solder joint cracks, to quantitatively characterize the relationships among them. These relationships verified that the laser ultrasound inspection system provides a reliable and efficient way to evaluate flip chip solder joint cracks nondestructively.