Effect of underfill filler settling on thermo-mechanical fatigue analysis of flip-chip eutectic solders

Underfills containing filler particles exhibit filler settling during the (capillary-based) wicking and curing processes, thus causing the reliability estimation to deviate from that of the presumed base of no filler settling. This paper examines the thermo-mechanical responses of the solder joints in flip-chip packaging to various conditions of filler settling. We built five y-dependent profiles for describing the uniform, bilayered, and gradual settling of filler spheres in the through-depth direction of the underfill and used the Mori-Tanaka method to calculate the effective material properties of the filler-resin underfill compound by considering a linearly elastic, temperature-dependent resin with a glass transition temperature range of 70-130 °C. For each settling profile we analyzed the fatigue indicators, referred to as the inelastic shear strain ranges and the inelastic shear strain energy densities of the solder joints, and compared their magnitudes against the extent of filler settling. The results show that the fatigue indicators depend on the extent of filler settling. A greater extent of bilayered filler settling produced larger (in magnitude) fatigue indicators. The fatigue indicators associated with gradual filler settling, however, were almost always smaller, on average, than those associated with no filler settling, indicating that some types of filler settling might favor a longer solder fatigue life. This preliminary but intriguing finding may be partially explained by considering the asymmetric thermal mismatch in the through-depth direction of the underfill; a comparatively good thermal match near the bottom side of the solder joints may compensate for the thermal mismatch at the top side, thus contributing to an overall better thermal match in the solder joint.     

Wafer-Level Packaging With Soldered Stress-Engineered Micro-Springs

Micro-springs for integrated circuit test and packaging are demonstrated as soldered flip chip interconnects in a direct die to printed circuit board package. The spring interconnects are fabricated with thin film metallization as the last step in a wafer-scale process. The z-compliance of the interconnects can be used to test and/or burn-in parts in wafer form. After the parts are diced from the wafer, the springs then become the first-level (and often the last-level) interconnect between the chip and the board. The xy-compliance of the interconnect enables considerably large die to be soldered to an organic printed circuit board without underfill using a surface mount compatible process. To demonstrate this concept, daisy chain test vehicles were fabricated on die measuring 11.5 mm $times$ 6.5 mm with 48 spring contacts on a 0.8 mm $times$ 0.65 mm grid array, each spring measuring 400 $, mu$m $times$ 100 $mu$m. The parts were placed onto organic boards with screen printed solder paste using a pick and place machine. The parts were reflowed to complete the solder connection to each spring using eutectic and lead-free solder. Assembled parts have undergone ${>}20thinspace 000$ hot plate thermal cycles and ${>}1000$ oven thermal cycles without failure.      

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

Parametric reliability analysis of no-underfill flip chip package

This research proposes a parametric analysis for a flip chip package with a constraint-layer structure. Previous research has shown that flip-chip type packages with organic substrates require underfill for achieving adequate reliability life. Although underfill encapsulant is needed to improve the reliability of flip chip solder joint interconnects, it will also increase the difficulty of reworkability, increase the packaging cost and decrease the manufacturing throughput. This research is based on the fact that if the thermal mismatch between the silicon die and the organic substrate could be minimized, then the reliability of the solder joint could be accordingly enhanced. This research proposes a structure using a ceramic-like material with CTE close to silicon, mounted on the backside of the substrate to constrain the thermal expansion of the organic substrate. The ceramic-like material could reduce the thermal mismatch between silicon die and substrate, thereby enhancing the reliability life of the solder joint. Furthermore, in order to achieve better reliability design of this flip chip package, a parametric analysis using finite element analysis is performed for package design. The design parameters of the flip chip package include die size, substrate size/material, and constraint-layer size/material, etc. The results show that this constraint-layer structure could make the solder joints of the package achieve the same range of reliability as the conventional underfill material. More importantly, the flip chip package without underfill material could easily solve the reworkability problem, enhance the thermal dissipation capability and also improve the manufacturing throughput     

Unequal Error Protection: An Information-Theoretic Perspective

An information-theoretic framework for unequal error protection is developed in terms of the exponential error bounds. The fundamental difference between the bit-wise and message-wise unequal error protection ( UEP) is demonstrated, for fixed-length block codes on discrete memoryless channels (DMCs) without feedback. Effect of feedback is investigated via variable-length block codes. It is shown that, feedback results in a significant improvement in both bit-wise and message-wise UEPs (except the single message case for missed detection). The distinction between false-alarm and missed-detection formalizations for message-wise UEP is also considered. All results presented are at rates close to capacity.      

Noncoherent Synchronization of UWB-IR Multiple-Antenna Multipath Channels

This paper deals with the maximum-likelihood (ML) noncoherent data-aided (e.g., no blind) synchronization of multiple-antenna ultrawideband impulse-radio (UWB-IR) terminals that operate over broadband channels and are affected by multipath fading with a priori unknown number of paths and path-gain statistics. The synchronizer that we developed achieves the ML data-aided joint estimate of the number of paths and their arrival times (e.g., time delays), without requiring any a priori knowledge and/or a posteriori estimate of the amplitude (e.g., module and sign) of the channel gains. The ultimate performance of the proposed synchronizer is evaluated (in closed form) by developing the corresponding CramÉr–Rao bound (CRB), and the analytical conditions for achieving this bound are provided. The performance gain for the synchronization accuracy of multipath-affected UWB-IR signals arising from the exploitation of the multiple-antenna paradigm is (analytically) evaluated. Furthermore, a low-cost sequential implementation of the proposed synchronizer is detailed. It requires an all-analog front-end circuitry composed of a bank of sliding-window correlators, whose number is fully independent from the number of paths comprising the underlying multiple-antenna channel. Finally, the actual performance of the proposed synchronizer is numerically tested under both the signal acquisition and tracking operating conditions.      

Buffered Cross-Bar Switches, Revisited: Design Steps, Proofs and Simulations Towards Optimal Rate and Minimum Buffer Memory

Regarding the packet-switching problem, we prove that the weighed max-min fair service rates comprise the unique Nash equilibrium point of a strategic game, specifically a throughput auction based on a “least-demanding first-served” principle. We prove that a buffered crossbar switch can converge to this equilibrium with no pre-computation or internal acceleration, with either randomized or deterministic schedulers, (the latter with a minimum buffering of a single-packet per crosspoint). Finally, we present various simulation results that corroborate and extend our analysis.      

Novel Scheme for Joint Estimation of SNR, Doppler, and Carrier Frequency Offset in Double-Selective Wireless Channels

As receiver performance will be degraded by carrier frequency offset (CFO), Doppler shift, and low signal-to-noise ratio (SNR), a novel estimator that jointly considers CFO, Doppler shift, and SNR is proposed in this paper. The proposed algorithm uses the Fourier transform (FT) to calculate the power spectral density of time-varying channels through channel estimates. Then, a new periodogram technique is utilized to estimate CFO, Doppler shift, and SNR together. Unlike conventional methods in sinusoid estimation, which rely on the peak-value search of a periodogram, this paper exploits the hypothesis test to address the random frequency modulation of time-varying channels. Furthermore, to optimize estimation performance, a theoretical analysis is also provided on the influences of some key parameters, e.g., the length of the signal processed with fast FT , the amplitude threshold value, the SNR dynamic range, and the velocity dynamic range. Correspondingly, the appropriate key parameters are chosen according to this analysis and are validated by simulations. The results are consistent with our analysis and present high accuracy over a wide range of velocities and SNRs.      

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法,确定了倒装焊SnPb焊点的热循环寿命．采用粘塑性和粘弹性材料模式描述了SnPb焊料和底充胶的力学行为,用有限元方法模拟了SnPb焊点在热循环条件下的应力应变过程．基于计算的塑性应变范围和实验的热循环寿命,确定了倒装焊SnPb焊点热循环失效Coffin-Manson经验方程的材料参数．研究表明,有底充胶倒装焊SnPb焊点的塑性应变范围比无底充胶时明显减小,热循环寿命可提高约20倍,充胶后的焊点高度对可靠性的影响变得不明显．     

Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits

Along with the progress of advanced VLSI technology, noise issues in dynamic circuits have become an imperative design challenge. The twin-transistor design is the current state-of-the-art design to enhance the noise immunity in dynamic CMOS circuits. To achieve the high noise-tolerant capability, in this paper, we propose a new isolated noise-tolerant (INT) technique which is a mechanism to isolate noise tolerant circuits from noise interference. Simulation results show that the proposed 8-bit INT Manchester adder can achieve 1.66$times$ average noise threshold energy (ANTE) improvement. In addition, it can save 34% power delay product (PDP) in low signal-to-noise ratio (SNR) environments as compared with the 8-bit twin-transistor Manchester adder under TSMC 0.18-$mu$ m process.      

Analysis of Two Alternative ADI-FDTD Formulations for Transverse-Electric Waves in Lossy Materials

A numerical dispersion analysis of the alternating-direction implicit finite-difference time-domain method for transverse-electric waves in lossy materials is presented. Two different finite-difference approximations for the conduction terms are considered: the double-average and the synchronized schemes. The numerical dispersion relation is derived in a closed form and validated through numerical simulations. This study shows that, despite its popularity, the accuracy of the double-average scheme is sensitive to how well the relaxation-time constant of the material is resolved by the time step. Poor resolutions lead to unacceptably large numerical errors. On the other hand, for good conductors, the synchronized scheme allows stability factors as large as 100 to be used without deteriorating the accuracy significantly.      

A new experimental method to evaluate creep fatigue life of flip-chip solder joints with underfill

A new accelerated stress test method was developed to evaluate creep life of flip-chip solder joints with underfill. With this method, a cyclic creep test can be done simply by applying a displacement to the FR-4 printed circuit board (PCB) board in the axial direction. The creep fatigue test was performed under displacement control with real-time electrical continuity monitoring. Test results show that the displacement arising from the force is equivalent to the thermal stress during thermal expansion. It was found that the magnitude of displacement was proportional to the inelastic strain sustained by the solder joints. This indicates that the creep fatigue life obtained will not only reflect the quality of the solder joints, but can also be used to characterize the reliability of the flip-chip assembly. Finite element modeling was also performed to confirm the agreement of deformation of the solder joints under mechanical and thermal loading. Results suggest that deformation and strain of the flip-chip assembly are consistent or comparable between the mechanical and thermal cycling. The failure analysis indicates that fatigue cracks often initiate from the top edge of a corner solder joint in the creep fatigue test, which is similar to what would happen in thermal cycling test. Lastly, the effect of underfill on the creep fatigue test is discussed. It is postulated that the test method is applicable to other flip-chip assemblies, such as conductive adhesive interconnections.     

Do chip size limits exist for DCA?

Solder joints, the most widely used flip chip on board (FCOB) interconnects, have a relatively low structural compliance due to the large thermal expansion mismatch between silicon die and the organic substrate. The coefficient of thermal expansion (CTE) of the printed wiring board (PWB) is almost an order of magnitude greater than that of the integrated circuit (IC). Under operating and testing conditions, this mismatch subjects the solder joints to large creep strains and leads to early failure of the solder connections. The reliability of such flip chip structures can be enhanced by applying an epoxy-based underfill between the chip and the substrate, encapsulating the solder joints. This material, once cured, mechanically couples the IC and substrate together to locally constrain the CTE mismatch. However, the effects of CTE mismatch are assumed to become more severe with increasing chip size. Even with the addition of an underfill material, it has been supposed that there are limits on the chip size used in flip chip applications     

Highly reliable non-conductive adhesives for flip chip CSP applications

Non-conductive adhesives (NCA), widely used in display packaging and fine pitch flip chip packaging technology, have been recommended as one of the most suitable interconnection materials for flip-chip chip size packages (CSPs) due to the advantages such as easier processing, good electrical performance, lower cost, and low temperature processing. Flip chip assembly using modified NCA materials with material property optimization such as CTEs and modulus by loading optimized content of nonconductive fillers for the good electrical, mechanical and reliability characteristics, can enable wide application of NCA materials for fine pitch first level interconnection in the flip chip CSP applications. In this paper, we have developed film type NCA materials for flip chip assembly on organic substrates. NCAs are generally mixture of epoxy polymer resin without any fillers, and have high CTE values un-like conventional underfill materials used to enhance thermal cycling reliability of solder flip chip assembly on organic boards. In order to reduce thermal and mechanical stress and strain induced by CTE mismatch between a chip and organic substrate, the CTE of NCAs was optimized by filler content. The flip chip CSP assembly using modified NCA showed high reliability in various environmental tests, such as thermal cycling test (-55/spl deg/C/+160/spl deg/C, 1000 cycle), high temperature humidity test (85/spl deg/C/85%RH, 1000 h) and high temperature storage test (125/spl deg/C, dry condition). The material properties of NCA such as the curing profile, the thermal expansion, the storage modulus and adhesion were also investigated as a function of filler content.     

倒装焊SnPb焊点热循环失效和底充胶的影响

采用实验方法 ,确定了倒装焊 Sn Pb焊点的热循环寿命 .采用粘塑性和粘弹性材料模式描述了 Sn Pb焊料和底充胶的力学行为 ,用有限元方法模拟了 Sn Pb焊点在热循环条件下的应力应变过程 .基于计算的塑性应变范围和实验的热循环寿命 ,确定了倒装焊 Sn Pb焊点热循环失效 Coffin- Manson经验方程的材料参数 .研究表明 ,有底充胶倒装焊 Sn Pb焊点的塑性应变范围比无底充胶时明显减小 ,热循环寿命可提高约 2 0倍 ,充胶后的焊点高度对可靠性的影响变得不明显     

A Control Strategy for Four-Switch Three-Phase Brushless DC Motor Using Single Current Sensor

A control strategy based on single current sensor is proposed for a four-switch three-phase brushless dc (BLDC) motor system to lower cost and improve performance. The system's whole working process is divided into two groups. In modes 2, 3, 5, and 6, where phase c works, phase- c current is sensed to control phases a and b, and phase-c current is consequently regulated. In modes 1 and 4, the combination of four suboperating modes for controlling phase-c current is proposed based on detailed analysis on the different rules that these operating modes have on phase-c current. Phase-c current is maintained at nearly zero level first, and phase- a and phase-b currents are regulated by speed circle. To improve control performance, a single-neuron adaptive proportional–integral (PI) algorithm is adopted to realize the speed regulator. Simulation and experimental systems are set up to verify the proposed strategy. According to simulation and experimental results, the proposed strategy shows good self-adapted track ability with low current ripple and strong robustness to the given speed reference model. Also, the structure of the drive is simplified.      

Development of Ultrabroadband (DC–50 GHz) Wafer-Scale Packaging Method for Low-Profile Bump Flip-Chip Technology

A locally matched flip-chip (LMFC) interconnect that uses a capacitive compensation technique to minimize impedance mismatch in coplanar waveguide lines is described. With an optimum percentage change in capacitance of 55$, pm ,$5%, we observe return loss below 25 dB over 90% of a 50 GHz bandwidth. When compared to a conventional flip-chip method, the minimum performance improvement in return loss is 10 dB and the insertion loss is smooth up to 30 GHz. The LMFC interconnect consists of two micromachined features: 1) an air cavity underneath the chip and 2) local trenches in the transition region of the flip-chip interconnect interface. A comparison of different LMFC interconnect designs to the conventional flip-chip approach is made, and design rules to obtain local trench dimensions are discussed.      

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures

Modern portable embedded devices require processors that can provide sufficient performance for demanding multimedia and wireless applications. At the same time they have to be flexible to support a wide range of products and extremely energy efficient to provide a long battery life. Coarse Grained Reconfigurable Architectures (CGRAs) potentially meet these constraints by providing a mix of flexible computational resources and large amounts of programmable interconnect. The vast design space of CGRAs complicates the development of optimized processors. Most effort has been spent on improving the performance. However, the energy cost of the programmable interconnect is becoming more expensive and this cost can no longer be neglected. In this work we present an energy- and performance-aware exploration for the interconnect of a CGRA and show that important tradeoffs can be made for those metrics. This will enable designers to develop more efficient architectures, tuned to a targeted application domain.      

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose Flexbus, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. Flexbus achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge by-pass, and component remapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of Flexbus-based architectures.      

Message Scheduling for the FlexRay Protocol: The Static Segment

In recent years, time-triggered communication protocols have been developed to support time-critical applications for in-vehicle communication. In this respect, the FlexRay protocol is likely to become the de facto standard. In this paper, we investigate the scheduling problem of periodic signals in the static segment of FlexRay. We identify and solve two subproblems and introduce associated performance metrics: 1) The signals have to be packed into equal-size messages to obey the restrictions of the FlexRay protocol, while using as little bandwidth as possible. To this end, we formulate a nonlinear integer programming (NIP) problem to maximize bandwidth utilization. Furthermore, we employ the restrictions of the FlexRay protocol to decompose the NIP and compute the optimal message set efficiently. 2) A message schedule has to be determined such that the periodic messages are transmitted with minimum jitter. For this purpose, we propose an appropriate software architecture and derive an integer linear programming (ILP) problem that both minimizes the jitter and the bandwidth allocation. A case study based on a benchmark signal set illustrates our results.