A triple-channel micropower operational amplifier

One method of increasing the amount of circuit functions using bipolar devices is to simplify the design of the monolithic chip. This paper describes such a new integrated circuit. The circuit has three independent, micropower, high- gain operational amplifiers on the monolithic chip. Open-loop voltage gain as high as 100 dB has been achieved with a power dissipation of under 300 /spl mu/W. The gain and power dissipation are externally controlled byout board components. Complete performance characteristics along with analysis are presented.     

A high precision micropower operational amplifier

An operational amplifier configuration implemented as a true micropower high precision op amp is described. It includes a well controlled and predictable DC biasing network that is insensitive to variations in temperature, supply voltages, and process. Also, it permits single supply operation. Excellent DC precision characteristics, comparable to or better than the very best precision op amps currently available, are realized yet at micropower levels. By simply increasing the biasing currents, a version of this design operates in general purpose applications without any degradation in its high precision characteristics. Thus, the AC performance levels of general purpose op amps are attained at a fraction of supply current. This device is fabricated using a standard bipolar IC process; an ion-implanted JFET is added to simplify biasing.     

Low-distortion low-voltage operational transconductance amplifier

A new operational transconductance amplifier (OTA) is proposed, which is based on the flipped voltage follower and source degeneration techniques. The OTA is simulated in a standard TSMC 0.18 μm CMOS process with a 1.8 V supply voltage. The simulation results show that the total harmonic distortion of the proposed OTA is less than 1% up to 0.85 Vp-p.     

CMOS low-voltage class-AB operational transconductance amplifier

The authors present a new low-voltage class-AB operational transconductance amplifier (OTA). The proposed OTA achieves a fast non slew-rate limited settling time with low power consumption. The circuit is power efficient when driving large capacitive loads. The OTA circuit is well suited for low-voltage low-power switched capacitor applications. Experimental results of the proposed circuit are included     

A novel low-voltage operational amplifier for low-power pipelined ADCs

A novel low-voltage two-stage operational amplifier employing class-AB architecture is presented. The structure utilizes level-shifters and current mirrors to create the class-AB behavior in the first and second stages. With this structure, the transconductances of the two stages are double compared with the normal configuration without class-AB behaviors with the same current consumption. Thus power can be saved and the operation frequency can be increased. The nested cascode miller compensation and symmetric common-mode feedback circuits are used for large unit-gain bandwidth, good phase margin and stability. Simulation results show that the sample-and-hold of the 12-bit 40-Ms/s pipelined ADC using the proposed amplifier consumes only 5.8 mW from 1.2 V power supply with signal-to-noise-and-distortion ratio 89.5 dB, spurious-free dynamic range 95.7 dB and total harmonic distortion -94.3 dB with Nyquist input signal frequency.     

A low-voltage sense amplifier with two-stage operational amplifier clamping for flash memory

A low-voltage sense amplifier with reference current generator utilizing two-stage operational amplifier clamp structure for flash memory is presented in this paper, capable of operating with minimum supply voltage at 1 V. A new reference current generation circuit composed of a reference cell and a two-stage operational amplifier clamping the drain pole of the reference cell is used to generate the reference current, which avoids the threshold limitation caused by current mirror transistor in the traditional sense amplifier. A novel reference voltage generation circuit using dummy bit-line structure without pull-down current is also adopted, which not only improves the sense window enhancing read precision but also saves power consumption. The sense amplifier was implemented in a flash realized in 90 nm flash technology. Experimental results show the access time is 14.7 ns with power supply of 1.2 V and slow corner at 125 ℃.     

A free but efficient low-voltage class-AB two-stage operational amplifier

A simple and efficient low-voltage two-stage operational amplifier with Class-AB output stage is introduced. It has a large effective output current boosting factor (/spl sim/50) and close to a factor 2 bandwidth enhancement. This is achieved at the expense of minimum increase in circuit complexity and no additional static power dissipation. Experimental verification of the characteristics of the proposed circuit is provided.     

一种用于低功耗流水线模数转换器的新型低电压运算放大器

本文提出一种新型适用于低电压的两级运算放大器。该放大器采用电平平移技术和电流镜镜像技术分别在第一级和第二级实现CLASS-AB偏置,在相同的电流消耗下,有效输入跨导相对传统的两级运放提高了一倍,从而实现了低功耗、大带宽、建立时间短的目标。采用嵌套米勒补偿技术和对称结构的共模反馈电路,运放在动态工作时可以达到很好的稳定性。在1.2伏的电源电压、0.18微米CMOS工艺下,该运放用于12位40兆赫兹采样频率的流水线模数转换器前端采样保持中,仿真结果显示,采样保持电路的无杂散动态范围达到95.7dB,总谐波失真-94.3dB,信噪失真比达到89.5dB,功耗仅为5.8毫瓦。     

低压低功耗运算放大器结构设计技术

低电压、低功耗、动态摆幅达到轨到轨（Rail—to—Rail）的运放是实现SOC设计的核心，而相关的输入输出模块是其中的关键技术。本文分析了两种分别工作于弱反型区和强反型区的恒跨导Rail—to—Rail输入级，同时给出了低压和极低压下两种AB类控制输出级的实现方案，并对各方案进行了比较和总结。     

A JFET/bipolar eight-channel analog multiplexer

Describes the design and fabrication of the first of a new generation of analog multiplexers using the bipolar/ionimplanted JFET process. The switch configuration used is especially suited to this process, and consequently results in a moderate size bipolar IC. The design of the switch, aided by the process characteristics, produces a high-performance monolithic multiplexer which can withstand input signals of greater than the power supplies and does not require special care in handling. A high degree of optimization is attained in the design of the bias circuits, and this plays a major role in achieving high fabrication yield, and subsequently low production costs.     

A micropower low-voltage multiplier with reduced spurious switching

We describe a micropower 16times16-bit multiplier (18.8 muW/MHz @1.1 V) for low-voltage power-critical low speed (les5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by ~62% and ~79% compared to conventional 16times16-bit and 32times32-bit designs respectively) the spurious switching in the Adder Block in the multiplier. The approach taken is to use latches to synchronize the inputs to the adders in the Adder Block in a predetermined chronological sequence. The hardware penalty of the latches is small because the latches are integrated (as opposed to external latches) into the adder, termed the latch adder (LA). By means of the LAs and timing, the number of switchings (spurious and that for computation) is reduced from ~5.6 and ~10 per adder in the adder block in conventional 16times16-bit and 32times32-bit designs respectively to ~2 in our designs. Based on simulations and measurements on prototype ICs (0.35 mum three metal dual poly CMOS process), we show that our 16times16-bit design dissipates ~32% less power, is ~20% slower but has ~20% better energy-delay-product (EDP) than conventional 16times16-bit multipliers. Our 32times32-bit design is estimated to dissipate ~53% less power, ~29% slower but is ~39% better EDP than the conventional general multiplier     

Micropower monolithic filters using bipolar/JFET technology

Two approaches for the implementation of micropower monolithic filters operating from a 1.3-V supply were investigated. The filters were fabricated using a bipolar/JFET compatible technology. The characteristics and limitations of each of the filtering approaches are discussed and a comparison between the two, based on the performance of second-order bandpass filter realizations, is presented.     

Micropower monolithic filters using bipolar/JFET technology

Two approaches for the implementation of micropower monolithic filters operating from a 1.3-V supply were investigated. The filters were fabricated using a bipolar/JFET compatible technology. The characteristics and limitations of each of the filtering approaches are discussed and a comparison between the two, based on the performance of second-order bandpass filter realizations, is presented.     

A 7.2 GHz bipolar operational transconductance amplifier for fully integrated OTA-C filters

Using a complementary bipolar junction transistor process having NPN transistors with a maximum short circuit common emitter gain-bandwidth product (ft) of 7.2 GHz and PNP transistors with a maximumft of 4.5 GHz, an operational transconductance amplifier has been designed for a 3-dB bandwidth of 7.2 GHz. The design process invokes new phase compensation strategies and develops innovative new ways of exploiting existing broadbanding techniques. The utility of the design is confirmed by demonstrating its application in two operational transconductance amplifier-capacitance filters. One of these examples is a 225 MHz lowpass filter, while the other is a bandpass filter with a center frequency of 250 MHz.This paper is an elaboration of work presented by the authors at the36th IEEE Midwest Symposium On Circuits And Systems in Detroit, Michigan, in August 1993.     

A CMOS current-mode operational amplifier

A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2.4-μm process     

A high-voltage monolithic operational amplifier

An operational amplifier capable of operating with power supplies up to /spl plusmn/40 V is discussed. The device exhibits output voltage and input common mode swings to within a few volts of either power supply, has an input offset current of 1 nA, a slew rate of 2 V//spl mu/s, and is internally compensated. This paper describes special circuit and device techniques used to reliably fabricated this amplifier with essentially standard monolithic diffused technology.     

A low-noise NMOS operational amplifier

NMOS operational amplifiers are known to have low-voltage gain and a poor noise performance. A new circuit technique is described which improves these parameters to achieve a typical DC voltage gain of 40000 and an average noise of 57 (nV/Hz/SUP 1/2/) over a 3 kHz bandwidth, with a total power dissipation of 6 mW.     

A low-noise high-precision operational amplifier

A low-noise high-precision operational amplifier has recently been fabricated in monolithic form with dielectric isolation. The amplifier exhibits a V/SUB OS/ of 10 /spl mu/V, V/SUB OS/T/SUB c/ of 0.3 /spl mu/V//spl deg/C, voltage gain of 140 dB with a 600 /spl Omega/ load, and an input noise voltage of 9 nV//spl radic/Hz. The settling time to within 0.01 percent of final value is 15 /spl mu/s for a 10 V pulse.     

Monolithic micropower amplifier using SiGe n-MODFET device

A micropower-relevant model is extracted from the DC characteristics of an n-type buried channel Si/SiGe hetero-junction modulation doped FET (HMODFET). This model is then used to design a novel monolithic SiGe single-stage class-A power amplifier for micropower operation (sub 500 /spl mu/W). The amplifier is fabricated and measured data of the power-gain against operating power are presented for the first time.     

一种高性能Folded-Cascode运算放大器的设计

介绍了一种高性能Foldcd-Cascode运放的电路结构,它具有先进的偏置电源结构以调节输出动态幅度、动态开关电容反馈电路用于控制运放输出端的稳定性、合理地关断电路以降低电路非工作时的功耗等特点.运用HSPICE对电路进行了模拟,并给出了结果.