收录机特种电路和机构的分析及修理快速复制电路

当前,中高档双卡收录机大多具有磁带快速复制的功能.这种复制速度一般是普通复制速度的两倍.要实施快速录音,必须具备以下各项条件:一是放音机芯与录音机芯必须具有两倍转速的功能,并且要同步;二是录音和放音均衡电路的高频补偿在快速录音时要相应提高;三是录音时的偏磁振荡频率要相应升高;四     

收录机的超音频干扰机理与克服方法

录音机采用超音频偏磁,具有录音灵敏度高、信噪比高、录音动态范围大、失真小等优点,因而近代多数录音机都采用此法偏磁。为保证录音机的高频频响,要求偏磁频率要高于录音机工怍的最高顿率5～10倍。因此,偏磁频率范围一般选择在几十至二百千     

杜比HX系统在高速机中的作用

众所周知,常见的一些录音方式,是将高频偏磁信号和音频信号混合进行录音的,根据不同磁带调节不同的偏磁点。对于每一个音频频率都存在一个理想的磁带偏磁电平,如图(1)所示。对315Hz的中音频能给出最大输出电平和可接受的低失真率的偏磁与10kHz频率时的最佳偏磁相差很大。可以看出录音的频率越高,所需的偏磁越小。一般来说偏磁选择的大小,要有一定的频率覆盖。在低、中频率最高输出电平时的最优偏磁略高,以照顾一定的高频输出。这样设置偏磁主要是照顾低、中频。磁带高频饱和现     

组合音响立体声录音座录放电路的检修（2）

录音电路由录音输入电路、录音放大电路、自动电平控制电路(ALC)、恒流录音电路、偏磁振荡器和录放磁头等组成，如图8所示。录音电路的作用是将所要录制的音频信号(包括话筒信号、收音信号、双卡磁带复制信号、唱机信号和线路输入信号等)进行转换、放大、频率补偿及电平控制等，最后供给录放磁头，在磁头中产生录音磁场，把音频信号记录在磁带上。下面介绍几种常见的录音电路。     

数字音频磁带记录系统（第六讲）

一、引言目前,在音频信号的记录方面,广泛使用的是高频偏置式的模拟录音机,它是具有许多特长的优良的记录系统,因而成为当前最为普及的音响设备之一。模拟录音机经过了几十年的发展、改进、提高已经到了极限,不能适应当今CD唱片和卫星广播普及所引起的人们对音响质量的更高的要求。传统的模拟录音机性能受限的主要原因有两点。第一是因为记录介质磁粉的非线性和磁头位置、录音电平、均衡及偏磁等的微小失调使录音产生失真、动态范围受到限制、转录时有串音、保存引起性能     

录音机的动态偏磁

近年来,由于高性能磁带的出现和电路技术的进展,磁迹窄、带速低的盒式录音机性能有了很大的提高,其主要技术指标已不亚于民用盘式录音机.然而,如果用盒式机与高速盘式机对同一音乐节目进行录放比较,那么就会发现,盒式机的放音质量不及盘式机,尤其在高频段,音质明显变差.这主要是由于盒式机采用低带速和固定偏磁录音方式而引起的须响差、高频过载能力低所造成的。本文通过磁带的偏磁特性来说明产生上述现象的原     

改造AAC语音室学习机音质的措施

介绍了改造AAC语音室学习机音质的措施,包括选择优质磁头调整录音补偿网络电路、放音补偿网络电路、音频压缩/扩展电路、电机稳速电路的参数。改造后的学习机带速稳定、音质层次分明、信噪比显著提高。此方法成本低、检测性能优、工作效率高。     

CT-6920立体声收录机频率均衡电路的计算机辅助分析

在磁带录音和放音过程中,由于存在着放音微分效应和录、放音的各种高频损耗现象,即使在恒流录音的条件下,放音输出也并非是平坦的频率特性,因此必须对录音放大器和放音放大器进行频率补偿.这种补     

盒式录音机原理与维修(三)——录音机的基本电路

录音机电路主要由录音电路、放音电路和超音频振荡电路组成。在三磁头式录音机中,录音和放音电路是分开的,而盒式机大多采用两磁头方式,录放电路是共用的。由于录、放电路要求不同,须用一组录放开关来进行转换,如图3-1所示。     

用USB供电的Hi-Fi唱机前置放大器

老式唱机和录音机的输出信号为模拟信号,而且在灌唱片或录音时,均具有低频衰减,高频提升的录音特性。放音时按RIAA(美国录音工业协会)所制定的标准补偿。因此,在唱机前置放大器中,不仅应具有一定的放大作用,还需要有均衡作用,按RIAA标准来提升低频,衰减高频。以前的Hi-Fi放大器有专门的唱机输入口,内有均衡电路。时至今日,带唱机输入口的商品放大器已很少见到了。现代的CD唱机有线性输出,无需再线性化。     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

高速高精度A/D转换器

本文介绍了用于观测太阳磁场的天文望远镜系统的高速高精度局部级联式多阈值A/D转换器。文章着重讨论了,为实现高速、高精度所采用的技术要点,并提出了研制高速高精度A/D转换器所必须考虑的有关问题。 我们所研制的A/D转换器,分辨率为1mV,相对误差0.025％,字长12位,前面接采样保持电路后,速度为10万次/秒。     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

A Convenient Multivariate Gram-Charlier Type A Series

It is often necessary to approximate the probability density function of a random variable from given statistical moments. The Gram-Charlier Type A series is one well known method for such representations. In this note, the Gram-Charlier Type A series is generalized to the multidimensional case.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

没有管理者的密钥共享方案

一般的密钥共享方案中都假设有一个管理者,管理者的作用是分发密钥,因此对管理者的可信要求很高,而现实生活中很难找到符合要求的管理者.文中利用单调存取结构上的张成方案构造了一个没有管理者的密钥共享方案,并证明其是一个可行的实用的密钥共享方案.基于这个的方案,构造了一个分布式密钥生成器.