Analysis of novel transparent gate recessed channel (TGRC) MOSFET for improved analog behaviour

In this paper, a novel device structure called transparent gate recessed channel MOSFET (TGRC-MOSFET) is proposed to alleviate the hot carrier effects for the advanced nanometer process. TGRC-MOSFET involving a recessed channel and incorporates indium tin oxide as a transparent gate. TCAD analysis shows that the performance of TGRC-MOSFET surpasses conventional recessed channel (CRC)-MOSFET in terms of high I_ON/I_OFF ratio and better carrier transport efficiency in comparison to CRC-MOSFET. This simulation divulges the reduction in hot-carrier-effects metrics like electron velocity, electron temperature, potential, and electron mobility. Furthermore, the effect of gate length is observed on the analog behavior of TGRC-MOSFET. All the simulations have been done using DEVEDIT-3D and ATLAS device simulator. The work proposes the novel design for reduced hot carrier and low power switching applications.     

Oxide bound impact on hot-carrier degradation for gate electrode workfunction engineered (GEWE) silicon nanowire MOSFET

In this present work, we explore the hot carrier fidelity of gate electrode workfunction engineered silicon nanowire (GEWE-SiNW) MOSFET at 300 K using DEVEDIT-3D device editor and ATLAS device simulation software. TCAD simulation shows reduction in the hot carrier reliability of a GEWE SiNW MOSFET in terms of electron temperature, electron velocity and Hot Electron gate current for reflecting its efficacy in high power CMOS applications. Further, a comparative investigation for different values of oxide thickness and high-k has been done to analyze the performance of GEWE-SiNW MOSFET in terms of electrical parameters such as conduction band, DIBL, electric field, electron temperature, electric velocity and gate current. It has been clearly shown that with oxide thickness 0.5 nm the hot-carrier reliability and device performance improves in comparison to oxide thickness 2.5 nm. In addition, with k = 21(HfO₂) device performance in terms of hot-carrier reliability further enhanced due to increased capacitance and thus offer its effectiveness in sub-nm range analog applications.     

Study of device parameters for work function engineered gate recessed S/D SOI MOSFET incorporating quantum mechanical effects

For the first time analytical modeling of nanoscale work function engineered gate recessed S/D SOI MOSFET including quantum mechanical effects has been presented based on the solution of 1 D Schrödinger and 2 D Poisson’s equation. As classical models are insufficient in nanoscale regime, quantization effect has been incorporated in this model to explore the actual potential profile characteristics along the film thickness. An extensive calculation has been carried out with proper boundary condition to solve the 2-D Poisson’s equation for device parameters. The value of deviated quantum threshold voltage has been calculated from classical model, and then these two are added to resolve the final quantum threshold voltage. Channel length modulation has also been taken into consideration during drain current modeling for this structure. A comparative study based on the threshold voltage, drain current, transconductance and drain conductance has been presented for the classical and quantum model. The results are also compared with the simulation of SILVACO Deck build, Deck Editor Version 4.2.5.R (aka 4.2.5.R) device simulator to validate the proposed model.

     

Effect of fringing field capacitances in RF and small signal parameters of surrounding gate MOSFET

Microsystem Technologies - A small signal equivalent model of surrounding gate MOSFET incorporating fringing capacitances has been proposed and detailed in this paper. Detail modeling of the...     

Assessment of analog RF performance for insulated shallow extension (ISE) cylindrical surrounding gate (CSG) MOSFET incorporating gate stack

In this paper, insulated shallow extension cylindrical surrounding gate (ISE-CSG) MOSFET with high-k gate stack has been proposed and extensively investigated. The performance of high-k ISE-CSG MOSFET has been compared with cylindrical surrounding gate MOSFET. ISE-CSG with high-k gate stack has number of desirable features at 30 nm regimes. The results reveal that ISE-CSG MOSFET with gate stack is more immune to short channel effects because of improved carrier transportation capability. It has been observed that high-k ISE-CSG MOSFET shows improved figure of merits as drive current (I_ON), I_ON/I_OFF ratio, transconductance (g_m), cutoff frequency f_T, transconductance generation factor, intrinsic gain (A_v), transconductance frequency product, gain transconductance frequency product and gain frequency product. ISE-CSG with high-k gives better control over the depletion region and therefore it is a suitable device for high speed, high frequency and analog/RF circuit applications.

     

Novel design to improve band to band tunneling and gate induced drain leakages (GIDL) in cylindrical gate all around (GAA) MOSFET

Microsystem Technologies - In this paper a cylindrical Dual Metal (DM) Dielectric Engineered (DE) Gate All Around (GAA) MOSFET has been proposed to resolve a big issue of Gate Inducted Drain...     

Hafnium oxide based cylindrical junctionless double surrounding gate (CJLDSG) MOSFET for high speed,high frequency digital and analog applications

Microsystem Technologies - In this paper Hafnium Oxide (HfO2) based cylindrical Junctionless Double Surrounding Gate (CJLDSG) MOSFET has been analyzed for various metrics of device performance....     

MOSFET输出电容的非线性对振荡谐波的影响

MOSFET的输出电容COSS具有非线性。在射频震荡器中，电容的这一非线性会影响振荡器的谐波分量。本文选取不同直流电源电压和输出电压，对在不同工作状态下振荡器的输出谐波分量进行了Matlab数值分析。实验结果验证了数值分析的结论。     

Influence of channel‐deposition conditions and gate insulators on performance and stability of top‐gate IGZO transparent thin‐film transistors

Abstract— Amorphous‐oxide‐semiconductor thin‐film transistors (TFTs) have gained wide attention in recent years due to their many merits. In this paper, a series of top‐gate transparent thin‐film transistors (TFTs) based on amorphous‐indium—gallium—zinc—oxide (a‐IGZO) semiconductors have been fabricated and investigated. Specifically, low‐temperature SiNx and SiOx were used as the gate insulator and different Ar/O² gas‐flow ratios were used for a‐IGZO channel deposition to study the influences of gate insulators and channel‐deposition conditions. In addition to the investigation of device performance, the stability of these TFTs was also examined by applying constant‐current stressing. It was found that a high mobility of 30‐45 cm²/V‐sec and small threshold‐voltage shift in constant‐current stressing can be achieved using SiNx with suitable hydrogen‐content stoichiometry as the gate insulator and the carefully adjusted Ar/O² flow ratio for channel deposition. These results may be associated with hydrogen incorporation into the channel, the lower defect trap density, and the better water/oxygen barrier properties (impermeability) of the low‐temperature SiNx.     

基于有限元方法的半导体器件电一热分析

随着微电子技术的迅猛发展,各种微电子设备获得了空前广泛的应用,电子系统对电磁干扰的敏感程度也随之增加。在电磁脉冲的影响下,电子系统中的晶体管会发生电、热击穿,因此,半导体器件的可靠性日益成为电磁兼容性领域的关键问题。为了研究半导体器件在常见电磁脉冲影响下的可靠性问题,本文采用了一种混合时域有限元方法,对半导体器件进行综合的电-热分析,通过计算机仿真数值求解半导体物理方程和热力学方程,获得在电磁脉冲下半导体器件内部的温度分布情况。从仿真结果可以看到,半导体器件在电磁脉冲作用下会产生严重的热效应,内部温度甚至能达到材料熔点。因而,在电子系统设计中必须采用相应的技术对半导体器件进行电磁防护。     

Effect of band non-parabolicity on energy sub-band profile for nano-dimensional MOSFET

Microsystem Technologies - In this paper, the effect of band non-parabolicity on the sub bands of an nano-dimensional junction less MOSFET have been presented using analytical models. Hence, one-...     

基于线结构光和足底扫描的足部参数测量研究

针对现有足部轮廓三维重构方法精度低,鲁棒性差,成本昂贵且不符合实际足部生物力学研究要求等问题,设计了一种利用光学测量技术实现无接触式足部参数测量的系统。该系统一方面通过对足底扫描图像处理,构建足底轮廓点云,分割足底压力区域,计算足底相关参数;另一方面利用线结构光技术,重构足面轮廓,将足底轮廓点云与足面轮廓点云在系统规定世界坐标系内融合,形成完整足部轮廓点云,根据定义计算足部围度等足部系列参数。通过搭建相应硬件平台对多组人体足部进行测量,实验结果表明系统能够快速、精确地完成足部三维重构,具有很好的鲁棒性。     

Effect of personality type on structured tool comprehension performance

Accurate understanding of software requirements by end users and software developers is important to ensure a high quality software product. While comprehension performance on systems analysis tools has been studied in the past, there is little research that examined the influence of personality type of an individual on his/her performance. This paper has two objectives. First, the research uncovers the relationships between personality types (introvert/extrovert, sensing/intuitive, feeling/thinking, and perceptive/judging) and comprehension performance (accuracy and speed) of users/developers using the structured tools: Decision Tables (DT), Nassi–Schneiderman Charts (NS) and Structured English (SE). Second, it examines the trade-offs between comprehension accuracy and speed for each personality type. Using laboratory experiments, we measured individual performance with the three structured tools. We found that introverts and feeling personalities comprehended more accurately with DT; thinking and intuitive personalities comprehended more accurately with NS and SE. The comprehension accuracy increased with time more for SE than for DT and NS. The results show the most suitable combinations of structured tools and personality types for high comprehension. The results also provide guidelines to managers with tight project schedules, such as structured tools that are easier/faster to understand and the matching personalities who can comprehend faster.     

Effect of process parameters on the surface morphology andmechanical performance of silicon structures after deep reactive ionetching (DRIE)

The ability to predict and control the influence of process parameters during silicon etching is vital for the success of most MEMS devices. In the case of deep reactive ion etching (DRIE) of silicon substrates, experimental results indicate that etch performance as well as surface morphology and post-etch mechanical behavior have a strong dependence on processing parameters. In order to understand the influence of these parameters, a set of experiments was designed and performed to fully characterize the sensitivity of surface morphology and mechanical behavior of silicon samples produced with different DRIE operating conditions. The designed experiment involved a matrix of 55 silicon wafers with radius hub flexure (RHF) specimens which were etched 10 min under varying DRIE processing conditions. Data collected by interferometry, atomic force microscopy (AFM), profilometry, and scanning electron microscopy (SEM), was used to determine the response of etching performance to operating conditions. The data collected for fracture strength was analyzed and modeled by finite element computation. The data was then fitted to response surfaces to model the dependence of response variables on dry processing conditions     

Inelastic electron tunneling spectroscopy （IETS） study of high-k gate dielectrics

This paper provides a review of the inelastic electron tunneling spectroscopy (IETS), a powerful technique for characterizing both the structural and electrical properties of ultra-thin gate dielectrics in MOS devices. The principle of operation of IETS will be described, and examples will be shown to illustrate the wealth of information that can be revealed by IETS, including phonons, bonding vibration modes, impurity bonds, and traps, which is diffcult to accurately characterize on the same sample by othe...     

Improvements on voltage-resistant performance of bipolar static induction transistor (BSIT) with buried gate structure

The breakdown mechanism of power bipolar static induction transistor (BSIT) with buried gate structure is analyzed in depth.A power BSIT sample with high voltage-resistant capability has been designed and fabricated in this paper.The technological methods for improving high voltage performances are represented.The active region of BSIT is surrounded with a deep trench to avoid any probable influences of various defects on device performances.Two field-limiting ring-shape junctions and one channel termination ring-shape junction are arranged around the gate region to reduce the electric field intensity.The gate-source breakdown voltage BV GS of power BSIT has been increased to 110 V from previous value of 50-60 V,and its blocking voltage is increased to 1700 V.The optimal geometrical dimensions for achieving the maximum breakdown voltage BV GS and blocking voltage V block are also represented in the paper.     

Characteristics of the Lower Yellow River channel shrinkage and its discriminant parameters

This paper analyzes the changing trends of the Lower Yellow River(LYR) transverse profile parameters and their aberrance points by the time series analysis method.Research results show that there has been a trend of changes in the LYR channel transverse profile parameters since the 1950s.The main river channel has a tendency of shrinkage year by year and the trend will be continued in the future.The main features of the LYR channel shrinkage are remarkable reductions of bankfull dis-charges and bankfull are...     

Drain current modelling of unipolar junction dual material double-gate MOSFET (UJDMDG) for SoC applications

Microsystem Technologies - A simple continuous analytical model is developed for the drain current of unipolar junction dual material double gate MOSFET (UJDMDG). The model is based on...