An ultra-high-speed ECL-BiCMOS technology with silicon filletself-aligned contacts

We have developed a half-micron super self-aligned BiCMOS technology for high speed application. A new SIlicon Fillet self-aligned conTact (SIFT) process is integrated in this BiCMOS technology enabling high speed performances for both CMOS and ECL bipolar circuits. In this paper, we describe the process design, device characteristics and circuit performance of this BiCMOS technology. The minimum CMOS gate delay is 38 ps on 0.5 μm gate and 50 ps on 0.6 μm gate ring oscillators at 5 V. Bipolar ECL gate delay is 24 ps on 0.6 μm emitter ring oscillators with collector current density of 40 kA/cm². A single phase decision circuit operating error free over 8 Gb/s and a static frequency divider operating at 13.5 GHz is demonstrated in our BiCMOS technology     

Process integration and device performance of a submicrometerBiCMOS with 16-GHz ft double poly-bipolar devices

Submicrometer-channel CMOS devices have been integrated with self-aligned double-polysilicon bipolar devices showing a cutoff frequency of 16 GHz. n-p-n bipolar transistors and p-channel MOSFETs were built in an n-type epitaxial layer on an n⁺ buried layer, and n-channel MOSFETs were built in a p-well on a p⁺ buried layer. Deep trenches with depths of 4 μm and widths of 1 μm isolated the n-p-n bipolar transistors and the n- and p-channel MOSFETs from each other. CMOS, BiCMOS, and bipolar ECL circuits were characterized and compared with each other in terms of circuit speed as a function of loading capacitance, power dissipation, and power supply voltage. The BiCMOS circuit showed a significant speed degradation and became slower than the CMOS circuit when the power supply voltage was reduced below 3.3 V. The bipolar ECL circuit maintained the highest speed, with a propagation delay time of 65 ps for C_L=0 pF and 300 ps for C_L=1.0 pF with a power dissipation of 8 mW per gate. The circuit speed improvements in the CMOS circuits as the effective channel lengths of the MOS devices were scaled from 0.8 to 0.4 μm were maintained at almost the same ratio     

Full-swing Schottky BiCMOS/BiNMOS and the effects of operatingfrequency and supply voltage scaling

Novel full-swing BiCMOS/BiNMOS logic circuits which use Schottky diode in the pull-up section for low supply-voltage regime are developed. The full-swing pull-up operation is performed by saturating the bipolar transistor with a base current pulse. After which, the base is isolated and bootstrapped to a voltage higher than V_DD. The BiCMOS/BiNMOS circuits do not require a PNP bipolar transistor. They outperform other BiCMOS circuits at low supply voltage, particularly at 2 V using 0.5 μm BiCMOS technology. Delay, area, and power dissipation comparisons have been performed. The new circuits offer delay reduction at 2 V supply voltage of 37% to 56% over CMOS. The minimum fanout at which the new circuits outperform CMOS gate is 2 to 3. Furthermore, the effect of the operating frequency on the delay of a wide range of BiCMOS and BiNMOS circuits is reported for the first time, showing the superiority of the Schottky circuits     

Technology leverage for ultra-low power information systems

Many applications for future generations of logic and memory chips will be requiring highly sophisticated computing functions at low cost. Small form factors, portability, and low cost will require low power operation. While continued scaling of silicon technology to dimensions below quarter micron devices and interconnections appears technically feasible, higher levels of integration and operation at higher speed have been driving the power consumption of logic chips up instead of down. This paper discusses how scaled submicron silicon technology can provide leverage to reduce power, while gaining in throughput for logic chips, and in capacity for memory functions. Strong reductions in voltage supply have to accompany shrinking dimensions. Materials limits such as tunneling currents through ultra-thin silicon-dioxide gate dielectrics and electromigration in minimum pitch interconnections emerge to be key challenges to realize low power 0.1 μm level CMOS circuits. A more than 10× gain in productivity as measured by the energy*delay product can be realized by shrinking from 0.5-0.125 μm CMOS device technology     

A 0.5-μm very-high-speed silicon bipolar devices technologyU-groove-isolated SICOS

A 0.5-μm high-performance silicon bipolar technology is developed and a very-high-speed emitter-coupled-logic (ECL) circuit is demonstrated. Circuits are fabricated with a 0.5-μm SICOS (sidewall base contact structure) technology featuring U-groove isolation, a shallow impurity profile, and reduced base resistance. A U-groove-isolated SICOS structure is realized by the new self-alignment technology using the double polysilicon planarization method. To reduce the extrinsic base resistance, a large-grain base polysilicon is grown from the amorphous silicon layer. A greatly reduced substrate capacitance and small base resistance are obtained. Using these technologies, a minimum ECL gate delay of 27 ps at F_in =1 is realized. A 20-ps ECL gate will be possible in a device having a smaller emitter and the optimal graft base depth     

BiCMOS circuit technology for a 704 MHz ATM switch LSI

This paper describes BiCMOS level-converter circuits and clock circuits that increase VLSI interface speed to 1 GHz, and their application to a 704 MHz ATM switch LSI. An LSI with a high speed interface requires a BiCMOS multiplexer/demultiplexer (MUX/DEMUX) on the chip to reduce internal operation speed. A MUX/DEMUX with minimum power dissipation and a minimum pattern area can be designed using the proposed converter circuits. The converter circuits, using weakly cross-coupled CMOS inverters and a voltage regulator circuit, can convert signal levels between LCML and positive CMOS at a speed of 500 MHz. Data synchronization in the high speed region is ensured by a new BiCMOS clock circuit consisting of a pure ECL path and retiming circuits. The clock circuit reduces the chip latency fluctuation of the clock signal and absorbs the delay difference between the ECL clock and data through the CMOS circuits. A rerouting-Banyan (RRB) ATM switch, employing both the proposed converter circuits and the clock circuits, has been fabricated with 0.5 μm BiCMOS technology. The LSI, composed of CMOS 15 K gate logic, 8 Kb RAM, I Kb FIFO and ECL 1.6 K gate logic, achieved an operation speed of 704-MHz with power dissipation of 7.2 W     

A high-speed complementary silicon bipolar technology with 12-fJpower-delay product

A complementary silicon bipolar technology offering a substantial improvement in power-delay performance over conventional n-p-n-only bipolar technology is demonstrated. High-speed n-p-n and p-n-p double-polysilicon, self-aligned transistors were fabricated in a 20-mask-count integrated process using an experimental test site designed specifically for complementary bipolar applications. N-p-n and p-n-p transistors with 0.50-μm emitter widths have cutoff frequencies of 50 GHz and 13 GHz, respectively. Two novel complementary bipolar circuits-AC-coupled complementary push-pull ECL, and NTL with complementary emitter-follower-display a significant advantage in power dissipation as well as gate delay when compared to conventional n-p-n-only ECL circuits. Record power-delay products of 34 fJ (23.2 ps at 1.48 mW) and 12 fJ (19.0 ps at 0.65 mW) were achieved for these unloaded complementary circuits, respectively. These results demonstrate the feasibility and resultant performance leverage of high-speed complementary bipolar technologies     

13-ns, 500-mW, 64-kbit ECL RAM using Hi-BiCMOS technology

The development is discussed for a 13-ns, 500-mW, 16K word/spl times/4-bit emitter-coupled logic (ECL) RAM using high-performance bipolar CMOS (Hi-BiCMOS) technology that combines a bipolar and a CMOS device on the same chip. The power dissipation of the RAM is about one half that of the conventional 64-kb bipolar ECL RAM. This high-speed, low-power RAM has been realized through a concept of a MOS-type memory cell, bipolar circuits, and a CMOS combination gate to allow for increased LSI integration.     

Very-high-speed silicon bipolar transistors with in-situ dopedpolysilicon emitter and rapid vapor-phase doping base

We present a detailed study of the performance of very-high-speed silicon bipolar transistors with ultra-shallow junctions formed by thermal diffusion. Devices are fabricated with double-polysilicon self-aligned bipolar technology with U-groove isolation on directly bonded SOI wafers to reduce the parasitic capacitances. Very thin and low resistivity bases are obtained by rapid vapor-phase doping (RVD), which is a vapor diffusion technique using a source gas of B₂H₆. Very shallow emitters are formed by in-situ phosphorus doped polysilicon (IDP) emitter technology with rapid thermal annealing (RTA). In IDP emitter technology, the emitters are formed by diffusion from the in-situ phosphorus doped amorphous silicon layer. Fabricated transistors are found to have ideal I-V characteristics, large current gain and low emitter resistance for a small emitter. Furthermore, a minimum ECL gate delay time of 15 ps is achieved using these key techniques. Analyses of the high performance using circuit and device simulations indicate that the most effective delay components of an ECL gate are cut-off frequency and base resistance. A high cut-off frequency is achieved by reducing the base width and active collector region. In this study, RVD is used to achieve both high cut-off frequency and low base resistance at the same time     

A fully complementary BiCMOS technology for 10 V mixed-signalcircuit applications

A 10 V fully complementary BiCMOS technology, HBC-10, has been developed for high speed, low noise and high precision mixed signal system integration applications. In this technology, two varieties of CMOS transistors have been implemented for 10 V analog and 5 V digital applications. A gate oxide thickness of 30 nm is utilized for the 10 V CMOS transistors with a lightly doped drain extension added to the NMOS structure to achieve device lifetime in excess of 10 years. A gate oxide thickness of 18 nm is used for 5 V CMOS logic circuits. These transistors are specially architected so that they may also serve as analog transistors in 5 V circuit applications. The 5 V NMOS transistor lifetime is guaranteed by use of a double diffused drain structure. The active devices are isolated by a fully recessed 1.5 μm oxide grown under high pressure conditions. Use of high pressure steam, plus combining diffusion operations where possible, results in a low overall thermal budget. This allows the up-diffusion of buried layers to be minimized so that a thin, 1.6 μm epitaxial silicon layer is sufficient to support 10 V bipolar transistors. The resultant vertical PNP and NPN transistors are characterized with cut-off frequencies of more than 1.3 GHz and 5 GHz, respectively. Likewise, the associated products of the current gain and Early voltage of PNP and NPN bipolar transistors are more than 1000 and 6000 V, respectively. A precision, buried Zener diode (for voltage reference applications), PtSi Schottky diode, polysilicon-oxide-polysilicon capacitor and trimmable thin film resistor are integrated into this process. This wide variety of passive and active components is essential for system integration and has been carefully designed for precision analog applications. The total number of masking operations is 23, which includes double layer metallization     

BiCMOS technology with 60 GHz n-p-n bipolar and 0.25 μm CMOS

A BiCMOS technology has been developed that integrates a high-performance self-aligned double-polysilicon bipolar device into an advanced 0.25 μm CMOS process. The process sequence has been tailored to allow maximum flexibility in the bipolar device design without perturbation of the CMOS device parameters. Thus, n-p-n cutoff frequencies as high as 60 GHz were achieved while maintaining a CMOS ring oscillator delay per stage of about 54 ps at 2.5 V supply comparable to the performance in the CMOs-only technology. BiCMOS and BiNMOS circuits were also fabricated. BiNMOS circuits exhibited ≈45% delay improvement compared to CMOS-only circuits under high load conditions at 2.5 V     

CMOS scaling for high performance and low power-the next ten years

A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described. One optimized for highest speed and the other trading off speed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 μm channel length at 2.5 V down to sub-0.1 μm at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the power supply voltage will lead to a substantial rise in standby power compared to active power and some tradeoffs of performance and/or changes in design methods must be made. Key technology elements and their impact on scaling are discussed. It is shown that a speed improvement of about 7× and over two orders of magnitude improvement in power-delay product (mW/MIPS) are expected by scaling of bulk CMOS down to the sub-0.1 μm regime as compared with today's high performance 0.6 μm devices at 5 V. However, the power density rises by a factor of 4× for the high-speed scenario. The status of the silicon-on-insulator (SOI) approach to scaled CMOS is also reviewed, showing the potential for about 3× savings in power compared to the bulk case at the same speed     

Threshold voltage-minimum gate length trade-off in buried channelPMOS devices for scaled supply voltage CMOS technologies

The trade-off between threshold voltage (V_th) and the minimum gate length (L_min) is discussed for optimizing the performance of buried channel PMOS transistors for low voltage/low power high-speed digital CMOS circuits. In a low supply voltage CMOS technology it is desirable to scale V_th and L_min for improved circuit performance. However, these two parameters cannot be scaled independently due to the channel punch-through effect. Statistical process/device modeling, split lot experiments, circuit simulations, and measurements are performed to optimize the PMOS transistor current drive and CMOS circuit speed. We show that trading PMOS transistor V_th for a smaller L_min results in faster circuits for low supply voltage (3.3 to 1.8 V) n⁺-polysilicon gate CMOS technology, Circuit simulation and measurements are performed in this study. Approximate empirical expressions are given for the optimum buried channel PMOS transistor V _th for minimizing CMOS circuit speed for cases involving: (1) constant capacitive load and (2) load capacitance proportional to MOS gate capacitance. The results of the numerical exercise are applied to the centering of device parameters of a 0.5 μm 3.3 V CMOS technology that (a) matches the speed of our 0.5 μm 5 V CMOS technology, and (b) achieves good performance down to 1.8 V power supply. For this process the optimum PMOS transistor V_th (absolute value) is approximately 0.85-0.90 V     

Self-aligned AlGaAs/GaAs HBT with low emitter resistance utilizingInGaAs cap layer

A self-aligned AlGaAs/GaAs heterojunction bipolar transistor (HBT) with an InGaAs emitter cap layer that has very low emitter resistance is described. In this structure, a nonalloyed emitter contact allows the emitter and base electrodes to be formed simultaneously and in a self-aligned manner. The reduction of emitter resistance greatly improves the HBT's transconductance and cutoff frequency. In fabricated devices with emitter dimensions of 2 μm×5 μm, a transconductance-per-unit-area of 16 mS/μm² and a cutoff frequency of 80 GHz were achieved. To investigate high-speed performance, a 21-stage ECL ring oscillator was fabricated using these devices. Propagation delay times as low as 5.5 ps/gate were obtained, demonstrating the effectiveness of this structure     

Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 Vsupply voltage regime

Novel full-swing BiCMOS/BiNMOS logic circuits using bootstrapping in the pull-up section for low supply voltage down to 1 V are reported. These circuit configurations use noncomplementary BiCMOS technology. Simulations have shown that they outperform other BiCMOS circuits at low supply voltage using 0.35 μm BiCMOS process. The delay and power dissipation of several NAND configurations have been compared. The new circuits offer delay reduction between 40 and 66% over CMOS in the range 1.2-3.3 V supply voltage. The minimum fanout at which the new circuits outperform CMOS gate is 5, which is lower than that of other gates particularly for sub-2.5 V operation     

High-performance implanted base silicon bipolar technology for RFapplications

A 0.4 μm silicon bipolar technology for mixed digital/analog RF-applications is described. Without increasing the process complexity in comparison to current production technologies transit frequencies of 52 GHz, maximum oscillation frequencies of 65 GHz and minimum noise figures of 0.7 and 1.3 dB at 3 and 6 GHz are achieved. Emitter-coupled logic (ECL) ring oscillators have a minimum gate delay of 12 ps, the low power capability of the technology is proven by a current-mode logic (CML) power delay product of 5.2 fJ and a dynamic frequency divider operates up to 52 GHz. These results demonstrate the suitability of this technology for mobile communications up to at least 6 GHz and for high-speed optical data links at 10 Gbit/s and above     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

High-speed low-power Darlington ECL circuit

Presents an ECL circuit with a Darlington configured dynamic current source and active-pull-down emitter-follower stage for low-power high-speed gate array application. The dynamic current source provides a large dynamic current during the switching transient to improve the power delay of the logic stage (current switch). A novel self-biasing scheme for the dynamic current source and the active-pull-down transistor with no additional devices and power in the biasing circuit is described. Based on a 0.8-μm double-poly self-aligned bipolar technology at a power consumption of 1 mW/gate, the circuit offers 28% improvement in the loaded (FI/FO=3, C_L=0.3 pF) delay and 42% improvement in the load driving capability compared with the conventional ECL circuit. The design and scaling considerations of the circuit are discussed     

Capacitor-free level-sensitive active pull-down ECL circuit withself-adjusting driving capability

This paper introduces a new self-adjusting active pull-down scheme for ECL circuit. The circuit offers self-terminating dynamic pull-down action by sensing the output level rather than using traditional load-dependent capacitive coupling. No capacitor or large resistor is required, and therefore it adds no process complexity and no area penalty. Implemented in an ECL gate array in a 1.2 μm double-poly self aligned bipolar technology, the circuit offers 300-ps delay at a power consumption of 1 mW/gate under FO=1 and C_L=0.55 pF loading condition. This is a 4.4 times speed improvement over the conventional ECL circuit. Furthermore, the circuit consumes only 0.25 mW for a gate speed of 700 ps/gate, which is a 1/7.8 power reduction compared with the conventional ECL circuit. The circuit requires a regulated reference voltage, which is also studied     

A high performance super self-aligned 3 V/5 V BiCMOS technologywith extremely low parasitics for low-power mixed-signal applications

A high performance BiCMOS technology, BEST2 (Bipolar Enhanced super Self-aligned Technology) designed for supporting low-power multiGHz mixed-signal applications is presented. Process modules to produce low parasitic device structures are described. The developed BiCMOS process implemented with 1 μm design rules (0.5 μm as one nesting tolerance) has achieved f_l and f_max for npn bipolar (A_e=1×2 μm²) of 23 GHz and 24 GHz at V_ce=3 V, respectively, with BV_ceo⩾5.5 volts, and βV_A product of 2400. Typical measured ECL gate delay is 48 ps/37 ps per stage (A_e=1×2 μm² ; 500 mV swing) at 0.6 mA/2.1 mA switching currents, and CMOS gate delay (gate oxide=125 Å, L_eff=0.6 μm; V_th,nch =0.45 V; V_th,pch=-0.45 V) 70 ps/stage. A BiCMOS phase-locked-loop (emitter width=1 μm; gate L_eff=0.7 μm) has achieved 6 GHz operation at 2 V power supply with total power consumption of 60 mW