Built-in self-test of MEMS accelerometers

A built-in self-test technique that is applicable to symmetric microsystems is described. A combination of existing layout features and additional circuitry is used to make measurements from symmetrically located points. In addition to the normal sense output, self-test outputs are used to detect the presence of layout asymmetry that are caused by local, hard-to-detect defects. Simulation results for an accelerometer reveal that our self-test approach is able to distinguish misbehavior resulting from local defects and global manufacturing process variations. A mathematical model is developed to analyze the efficacy of the differential built-in self-test method in characterization of a wide range of local manufacturing variations affecting different regions of a device and/or wafer. Model predictions are validated by simulation. Specifically, it has been shown that by using a suitable modulation scheme, sensitivity to etch variation along a particular direction is improved by nearly 30%.     

Built-in self-test of the Macrolan chip

The implementation of self-test in the medium access controller chip for Macrolan, a fibre-optic, local area network, is described. The test style for 80% of the chip's combinational logic is quasiexhaustive testing. This approach, despite its apparent inefficiency in terms of the number of patterns used, gives considerable flexibility to the designer in arranging linear-feedback shift registers and so is easier to implement than some other techniques. The chip also uses a form of random-pattern test, not normally considered for memory testing, instead of a specialized pattern generator. Built-in self-test was implemented without using fault simulation or approximate testability measures     

Built-in self-test: assuring system integrity

Today's complex electronic products are harder to test using traditional external methods. Built in self test can frequently be used without significantly increasing a product's size, cost and production time     

ALU的功能测试

本文给出了ＡＬＵ 的几种结构框图和ＡＬＵ 的进位链图模型以及基于该模型的功能测试方法，该方法对ＡＬＵ 加法器的测试可达到较高的测试有效性     

一种可重构体系结构的声码器ALU设计

文章介绍了采用可重构体系结构的TR600语音编解码器中的ALU设计。重点讨论了ALU的资源部件、数据通路、指令及在设计中的平衡规则。该ALU采用VHDL语言描述,经过仿真、综合和FPGA验证后,完全符合设计要求。     

Economics of built-in self-test

Using built-in self-test at the right level offers users significant cost savings, but determining which level, if any, is best for BIST can be complex. A detailed economic analysis can unravel heterogeneous costs and benefits so that designers and managers can make the right decision     

VLSI and SPICE modeling of ALU

The Arithmetic and Logic Unit （ALU） is a combination circuit that performs a number of arithmetic and logical operations within a microprocessor. The demand for faster and compact ALUs makes it desirable to test the ALU in conjunction with pre-design parts prior to manufacture. This may be accomplished in a process using CAD and SPICE simulation software. Our purpose is to realize a method for importing a layout drawn in Tanner L-edit and simulated in T-Spice into PSpice which is referred to as software talking. To do so we use an eight-function instruction set called Complimentary Metal Oxide Semiconductor Arithmetic and Logic Unit （CMOS ALU） which is laid out in Tanner L-edit and produces an extracted net-list which is simulated in T-Spice. An ALU equivalent design is then modeled in PSpice for further testing with pre-manufactured parts of the PSpice library.     

A time-code ALU for a microprocessor-based video editing system

An Arithmetic Logic Unit (ALU) was designed for use in a microprocessor-based video editing system. The hardware ALU developed implemented the time-code addition/subtraction required for video editing operating using the European Broadcasting Union standard format for time-code. The ALU was interfaced to an S-100 bus and tested with the North Star Z80A microprocessor development system.     

声码器中一种四级可重构ALU的研究与设计

在面向语音编解码算法实现的高性能声码器设计中,支持可变长VLIW指令集的ALU单元是实现其设计目标的重要环节.本文提出一种四级可重构的ALU设计,以前缀算法加法器为核心,并通过操作数和资源的重构,能在单周期内完成81种复合算术逻辑运算,同时将其控制编码压缩了58.93%以适应指令集的宽度约束,高效实现了算法中潜在的高并行性,很好的满足了运算密集型的算法应用需求.     

Circular self-test path for FSMs

Circular self test path (CSTP) is an attractive method for automatically transforming sequential circuits generated by automatic synthesis tools into BIST structures. The authors extend this method-making it more suitable for FSMs derived from synthesized control parts-and are integrating it into an industrial design flow supporting testable synthesis. The CSTP approach provides good results in terms of test length and fault coverage in large circuits. It requires substitution of all or some of the flip-flops in the circuit with special cells and their connection to constitute a circular chain. CSTP also has application in industrial environments, and several commercial CAE environments, such as that used by AT&T, now support CSTP as an approach for automatic introduction of BIST in circuits     

一种支持SIMD指令的低功耗分裂式ALU设计

在面向多媒体运算的高性能、低功耗DSP芯片MD32设计中,支持SIMD指令的分裂式、低功耗ALU设计是实现其没计目标的重要环节。该文提出了利用基于资源共享的设计思想,以超前进位加法器(Catry Look-ahead Adder)为核心构造数据处理单元,完成算术以及逻辑运算,减少了ALU模块的面积,同时均衡了不同数据通路长度,并且采用先进行数据选择,而后进行数据处理的设计原则,降低不使用模块的活动度,减少了功耗。根据Design Power分析其综合后门级实现结果,芯片面积可减少8％,功耗可减少51％。     

基于规则的寄存器传输级ALU工艺映射算法的研究

提出寄存器传输级工艺映射（RTLM）算法，该算法支持使用高层次综合和设计再利用的现代VLSI设计方法学，允许复杂的RT级组件，尤其是算术逻辑单元（ALU）在设计中重用，该映射算法使用目标ALU组件来实现源ALU组件，映射规则通过表格的方式给出，此算法对于规则结构的数据通路特别有效，应用k阶贪婪算法的实验结果表明，RTLM在高层次综合中对数据通路组件再利用是一种有效的方法。     

Boundary scan with built-in self-test

The authors propose a way to merge boundary scan with the built-in self-test (BIST) of printed circuit boards. Their boundary-scan structure is based on Version 2.0 of the Joint Task Action Group's recommendations for boundary scan and incorporates BIST using a register based on cellular automata (CA) techniques. They examine test patterns generated from this register and the more conventional linear-feedback shift register. The advantages of the CA register, or CAR, are its modularity, which allows modification without major redesign, its higher stuck-at fault coverage, and its higher transition fault coverage     

兼容MCS-96指令集的ALU设计

设计了一款能够完全兼容MCS-96系列单片机指令集的ALU。在设计中使用了经过逻辑简化的运算单元和改进的T型进位链,有效缩短了关键路径的延迟。采用硬件资源共享的策略进行运算单元和移位单元的结构组织设计,在不增加指令执行周期的前提下,最大限度地减小了电路面积。     

Realistic built-in self-test for static RAMs

The authors present the specification and design of a self-test mechanism for static random-access memories (RAMs). The test algorithm provides excellent fault detection, and its structure is independent of address and data scrambling. The self-test machine generates data backgrounds on chip and is therefore suitable for both bit-oriented and word-oriented SRAMs. It is also suitable for both embedded SRAMs and stand-alone SRAMs, and adapts to boundary-scan environment. Because of the regular and symmetric structure of the test algorithm, the silicon overhead is only 3% for a 16 K synchronous SRAM     

Embedded software-based self-test for programmable core-baseddesigns

The programmable cores on SoCs can perform on-chip test generation, measurement, response analysis, and even diagnosis. This software-based approach to self-testing enables at-speed testing and incurs low DFT overhead. We give an overview of the existing embedded software-based self-testing and self-diagnosis methods for core-based SoC designs, and we discuss the challenges to further developing this new testing paradigm     

一种结构简单的低压低功耗ALU单元设计

1位的ALU单元在某些集成电路的设计中非常重要,本文提出了一种结构简单的高速,低功耗,低工作电压的ALU单元.在此设计中采用了XOR/XNOR结构,并加入了适当的缓冲电路,有效的提高了运算速度,并可以减少在级连中的阀值损失,同时还保持了较低的MOS管数量.通过HSPICE (CSMC 0.35um工艺)仿真,得了很好的特性.     

DC built-in self-test for linear analog circuits

DC testing of analog circuits is cheaper than AC testing and covers many fault classes, including some that AC tests cannot detect. This efficient, low-cost, built-in self-test (BIST) methodology uses the checksum encodings of matrix representations to uncover faults that affect a circuit's DC transfer function