Head of the line arbitration of packet switches with combined input and output queueing

A single-stage non-blocking N × N packet switch is considered. Data units may be stored before switching at the inputs as well as after switching at the outputs. Some output buffering capacity is intended to achieve high throughput, whereas an additional input buffering capacity keeps losses due to input-buffer overflow reasonably low. The paper studies the impact on performance of the head of the line arbitration policy, i.e. the sequence which is used to transfer data units from the heads of input queues to each output queue. The investigation is based on two performance measures: the average delay and the maximum throughput of the switch. Closed-form expressions for the FCFS, LCFS and the ROS policies are obtained. The result of the average delay with the FCFS policy leads to a lower bound, and that with the LCFS policy to an upper bound for the average delay, corresponding to an arbitrary symmetric policy which does not use information related to the state of the input queues. It is shown that the maximum throughput does not depend on the head of the line arbitration policy. It depends only on the output-buffer size and the packet-size distribution. The cases of fixed and exponentially distributed packet sizes are studied. The effects of asymmetric policies which result in different behaviours of some of the input queues is also considered.     

带VOQ和交叉点缓冲的交叉矩阵

带虚拟输出队列(VOQ)的输入队列(IQ)交换结构可按比例地达到很高的速度,甚大规模集成电路(VLSI)集成度的不断提高使得对于Crossbar的交叉点在硬件上为每个信元或包留有足够的缓存成为可能。采用组合输入／输出排FX(CICQ)交换,可利用简单的算法得到比IQ交换更低的延迟。     

Departure Batch-size Distribution of Unbuffered Crossbar Packet Switches

In this letter, we present an exact closed-form solution for the probability distribution of the packet batch-size at the output ports of unbuffered crossbar based packet switches. The general case of a switch with M inputs and N outputs is considered under balanced traffic and using an optimum arbitration scheme. The solution can be applied to a wide range of queuing systems, even beyond the field of packet switching.     

A multistage ATM switch with interstage buffers

Asynchronous transfer mode (ATM) is the transport technique for the broadband ISDN recommended by CCITT (I.121). Many switches have been proposed to accommodate the ATM that requires fast packet switching capability.^1-8 The proposed switches for the broadband ISDN can be classified as being of input queueing or output queueing type. Those of the input queueing type have a throughput performance which is approximately 58 per cent that of the output queueing type. However, output queueing networks require larger amounts of hardware than input queueing networks. In this paper, we propose a new multistage switch with internal buffering that approaches a maximum throughput of 100 per cent as the buffering is increased. The switch is capable of broadcasting and self-routeing. It consists of two switching planes which consist of packet processors, 2 x 2 switching elements, distributors and buffers located between stages and in the output ports. The internal data rate of the proposed switch is the same as that of the arriving information stream. In this sense, the switch does not require speed-up. The switch has log₂ N stages that forward packets in a store-and-forward fashion, thus incurring a latency of log₂ N time periods. Performance analysis shows that the additional delay is small.     

Preventing internal and external conflicts in an input buffering reverse baseline ATM switch

When two or more packets that are destined to the same output of an ATM switch arrive at different inputs, buffers at inputs or outputs are used to queue all but one of these packets so that external conflict is prevented. Although input buffering ATM switches are more economical and simpler than output buffering ATM switches, significant loss of throughput can occur in input buffering ATM switches due to head‐of‐line (HOL) blocking when first‐in–first‐out (FIFO) queueing is employed. In order to avoid both external conflict and alleviate HOL blocking in non‐blocking ATM switches, some window‐based contention resolution algorithms were proposed in the literature. In this paper, we propose a window‐based contention resolution algorithm for a blocking ATM switch based on reverse baseline network with content addressable FIFO (CAFIFO) input buffers. The proposed algorithm prevents not only external conflicts but also internal conflicts, in addition to alleviating HOL blocking. This algorithm was obtained by adapting the ring reservation algorithm used on non‐blocking ATM switches to a reverse baseline network. The fact that a non‐blocking network is replaced by a log₂ N‐stage reverse baseline network yields a significant economy in implementation. We have conducted extensive simulations to evaluate the performance of reverse baseline network using the proposed window‐based contention resolution algorithm. Simulation results show that the throughput of reverse baseline network can be as good as the throughput of non‐blocking switches if the window depth of input buffers is made sufficiently large. Copyright © 2000 John Wiley & Sons, Ltd.     

Dynamic buffer management using per‐queue thresholds

Shared buffer switches consist of a memory pool completely shared among output ports of a switch. Shared buffer switches achieve low packet loss performance as buffer space is allocated in a flexible manner. However, this type of buffered switches suffers from high packet losses when the input traffic is imbalanced and bursty. Heavily loaded output ports dominate the usage of shared memory and lightly loaded ports cannot have access to these buffers. To regulate the lengths of very active queues and avoid performance degradations, threshold‐based dynamic buffer management policy, decay function threshold, is proposed in this paper. Decay function threshold is a per‐queue threshold scheme that uses a tailored threshold for each output port queue. This scheme suggests that buffer space occupied by an output port decays as the queue size of this port increases and/or empty buffer space decreases. Results have shown that decay function threshold policy is as good as well‐known dynamic thresholds scheme, and more robust when multicast traffic is used. The main advantage of using this policy is that besides best‐effort traffic it provides support to quality of service (QoS) traffic by using an integrated buffer management and scheduling framework. Copyright © 2006 John Wiley & Sons, Ltd.     

An evolution to crossbar switches with virtual output queuing and buffered cross points

Input queued (IQ) switch architectures with virtual output queues (VOQ) scale up to very high speeds and have been a subject of intense research in the past decade. VOQ IQ switches require switch matrix scheduling algorithms to match input ports to out ports. In this tutorial article, we present an overview of switch matrix scheduling for VOQ IQ switches with crossbar switch fabrics. We then describe what we believe will be the next generation of high-speed crossbar switches: the evolution of IQ switches to combined input and crossbar queued (CICQ) switches. With the continued increase in density of VLSI, sufficient buffering at crossbar cross points for one cell or packet has become feasible to implement. We show how CICQ switches have simple schedulers and result in lower delay than IQ switches. Both IQ and CICQ switches have unstable regions. We show how a threshold and bursting technique can feasibly achieve stability. We also show how CICQ switches are better suited (than IQ switches) for switching of variable-length packets such as IP packets. Many challenges remain in IQ and CICQ switches. In particular, the inclusion of QoS scheduling methods that are currently only suitable for output queued switches is a major open problem.     

A high-performance input access scheme for ATM multicast switching

In this paper, we propose an input access scheme for input-queued ATM multicast switches, achieving high system throughput, low packet delay and packet loss probability. Multicast and unicast packets of each input port are separately queued. Multicast queues take priority over the unicast queues, and both types of queues are fairly served in a cyclic-priority access discipline. In particular, each unicast queue is handled on a window-service basis, and each multicast packet is switched in a one-shot scheduling manner. To evaluate the performance of the access scheme, we propose an approximate analysis based on a simplified cyclic-priority model for anN×N finite-buffer multicast switch possessing Bernoulli multicast and unicast arrivals, with window-service (for unicasting) and one-shot scheduling (for multicasting) both taken into account. Finally, we show simulation results to demonstrate the accuracy of the approximate analysis and the superiority of the scheme over existing schemes with respect to normalized system throughput, mean packet delay, and packet loss probability.An earlier version of this paper appeared in IEEE ICC'96.     

A high‐performance switch architecture based on mesh of trees

With emergence of various new Internet‐enabled devices, such as tablet PCs or smart phones along with their own applications, the traffic growth rate is getting faster and faster these days and demands more communication bandwidth at even faster rate than before. To accommodate this ever‐increasing network traffic, even faster Internet routers are required. To respond for these needs, we propose a new mesh of trees based switch architecture, called MOTS(N) switch. In addition, we also propose two more variations of MOTS(N) to further improve it. MOTS(N) is inspired by crossbar with crosspoint buffers. It forms a binary tree for each output line, where each gridpoint buffer ? ? Because the fabric of MOTS(N) switch is not pure crossbar, we call the buffers in the same location in pure crossbar gridpoint buffers. Details will be presented in the following sections.
is a leaf node and each internal node is 2‐in 1‐out merge buffer § § 2‐in 1‐out merge buffer can accommodate two memory writes and one memory read simultaneously by using its modularized architecture 31 .
emulating FIFO queues. Because of this FIFO characteristic of internal buffers, MOTS(N) ensures QoS like FIFO output‐queued switch. The root node of the tree for each output line is the only component connected to the output port where each cell is transmitted to output port without any contention. To limit the number of buffers in MOTS(N) switch, we present one of its improved (practical) variations, IMOTS(N) switch, as well. For IMOTS(N) switch architecture, sizes of the buffers in the fabric are limited by a certain amount. As a downside of IMOTS(N), however, every cell should go through log ₂N + 1 number of buffers in the fabric to be transmitted to the designated output line. Therefore, for even further improvement, IMOTS(N) with cut‐through, denoted as IMOTS‐CT(N), is also proposed in this paper. In IMOTS‐CT(N) switch, the cells can cut through one or more empty buffers to be transferred from inputs to outputs with simple 1 or 2 bit signal exchanges between buffers. We analyze the throughput of MOTS(N), IMOTS(N), and IMOTS‐CT(N) switches and show that they can achieve 100% throughput under Bernoulli independent and identically distributed uniform traffic. Our quantitative simulation results validate the theoretical analysis. Copyright © 2012 John Wiley & Sons, Ltd.     

Round-robin selection with adaptable-size frame in a combined input-crosspoint buffered switch

As an alternative to input-buffered switches, combined input-crosspoint buffered switches relax arbitration timing and provide high-performance switching for packet switches with high-speed ports. It has been shown that these switches, with one-cell crosspoint buffer and round-robin (RR) arbitration at input and output ports, provide 100% throughput under uniform traffic. However, under admissible traffic patterns with nonuniform distributions, only weight-based selection schemes are reported to provide high throughput. We propose an RR based arbitration scheme for a combined input-crosspoint buffered packet switch that provides nearly 100% throughput for several admissible traffic patterns, including uniform and unbalanced traffic, using one-cell crosspoint buffers. The presented scheme uses adaptable-size frames, so that the frame size adapts to the traffic pattern.     

Matching From the First Iteration: An Iterative Switching Algorithm for an Input Queued Switch

An iterative switching algorithm for an input queued switch consists of a number of iterations in every time step, where each iteration computes a disjoint matching. If input is matched to output in a given iteration, a packet (if any) is forwarded from to in the corresponding time step. Most of the iterative switching algorithms use a request grant accept (RGA) arbitration type (e.g. iSLIP). Unfortunately, due to this particular type of arbitration, the matching computed in one iteration is not necessarily maximal (more input and output ports can still be matched). This is exactly why multiple iterations are needed. However, multiple iterations make the time step larger and reduce the speed of the switch. We present a new iterative switching algorithm (based on the RGA arbitration) called with the underlying assumption that the number of iterations is possibly limited to one, hence reducing the time step and allowing the switch to run at a higher speed. We prove that achieves throughput and delay guarantees with a speedup of 2 and one iteration under a constant burst traffic model, which makes as good as any maximal matching algorithm in the theoretical sense. We also show by simulation that achieves relatively high throughput in practice under uniform and non-uniform traffic patterns with one iteration and no speedup.     

Queuing analysis of shared‐buffer ATM switches with grouped output channels

Shared buffering and channel grouping are powerful techniques with great benefits in terms of both performance and implementation. Shared‐buffer switches are known to have better performance and better utilization than input or output queued switches. With channel grouping, a cell is routed to a group of channels instead of a specific output channel. In this way, congestion due to output contention can be minimized and the switch performance can therefore be greatly improved. Although each technique is well known by itself in the traditional study of queuing systems, their combined use in ATM networks has not been much explored previously. In this paper, we develop an analytical model for a shared‐buffer ATM switch with grouped output channels. The model is then used to study the switch performance in terms of cell loss probability, cell delay and throughput. In particular, we study the impact of the channel grouping factor on the buffer requirements. Our results show that grouping the output channels in a shared‐buffer ATM switch leads to considerable savings in buffer space. Copyright © 2001 John Wiley & Sons, Ltd.     

Performance trade-offs in input/output buffer design for a non-blocking space-division packet switch

Performance trade-offs in buffer architecture design for a space-division packet switching system is studied. As described in Figure 1, the system is constructed by a non-blocking switch fabric and input/output buffers. The capacity of the non-blocking switch fabric is defined by the maximum number of packets, denoted by m, which can be simultaneously routed from multiple inputs to each output. The buffer size at each input is considered to be finite, equal to K. The emphasis here is placed on the input packet loss probability for systems constructed by different ms and Ks. From the performance point of view, we conclude:

• (a) choosing m = 3 or 4 is sufficient to exploit the maximum utilization of a non-blocking switch fabric
• (b) introducing input buffers of moderate size K significantly reduces the packet loss probability.

     

A Knockout Switch for Variable-Length Packets

The Knockout Switch is a new packet switch architecture recently proposed for high-speed local and metropolitan area networks, multiprocessor interconnects, and local or toll switches for integrated traffic loads. We describe an approach to extend the original Knockout Switch to work with variable-length packets. This new architecture employs an input broadcast bus arrangement to achieve complete interconnection of the inputs and outputs. Consequently, there is no congestion in the switch fabric other than the unavoidable conflict of multiple simultaneous packets destined for the same output. It is with this output contention that the Knockout principle is fully utilized to efficiently concentrate and store contending packets while maintaining the first-in first-out discipline of the packet sequence; and yet the fabric speed required is no more than the input/output line speeds, Under these design goals, no switch can yield better delay/ throughout performance. These are the most important attributes that have been preserved in the current proposal from the original Knockout Switch. For anN times Nswitch configuration, the variable-length packet Knockout Switch consists ofNinput broadcast buses, and anN:Lconcentrator (L ll N) and a shared buffer for each output. The design of each subsystem is discussed with emphasis on possible VLSI realization. Using today's technology, we should be able to implement the proposed switch with both input/output lines and internal hardware operating at 50 Mbits/s. The dimension of the switch (N times N) can grow modularly from say 32 × 32 to 1024 × 1024, rendering a total throughput in the range of tens of gigabits per second. Future upgrading of the line interfaces to much higher speed without modification to the internal switch hardware is also possible with a modest restriction on the minimum length of new packets.     

Performance comparison between fixed length switching and variable length switching

Fixed length switching (FLS) and variable length switching (VLS) are two main types of switching architecture in high‐speed input‐queued switches. FLS is based on a cell‐by‐cell scheduling algorithm, while VLS operates on the variable packet granularity. This paper aims to make a comprehensive comparison between these two switching modes to guide the industrial design and academic research. We use stochastic models, Petri net models, analysis and simulations to investigate various performance measures of interest. Average packet latency, bandwidth utilization, segmentation and reassembly overhead, as well as packet loss are the identified key parameters that influence the outcome of the comparison. The results achieved in this paper are twofold. On one hand, it is shown that FLS enables smaller packet loss and lower packet delay in case of a short packet. On the other hand, VLS favors better bandwidth utilization, reduced implementation complexity and lower average packet delay. We recommend VLS in the conclusion since its disadvantages can be compensated by some methods, while the problems in FLS are difficult to be solved. Copyright © 2007 John Wiley & Sons, Ltd.     

ON IMPROVING THE DESIGN OF AN ATM SWITCH BASED ON INPUT–OUTPUT BUFFERS

We describe the development and analysis of an asynchronous transfer mode (ATM) switch architecture based on input–output buffers, a sort-Banyan network and a feedback acknowledgement (ACK) signal to be sent to the input unit. This is an input-buffer and output-buffer type of switch but with the different approach of feedback, which uses an acknowledgement feedback filter for recycling cells that lose contention at the routing network. In contrast to another design¹ which uses a merge network, a path allocation network and a concentration network at the output of the sort network to generate the acknowledgement signal, in this new proposal, the filler network has been simplified using only N filter nodes (2 × 2 switch element) and multiplexers which are placed at the feedforward of the sort network. This switch provides non-blocking, low cell loss and high throughput properties. It is designed with internal speed-up to enhance its throughput, to reduce the head of line (HOL) blocking, and to reduce the end-to-end delay.     

Architecture design,performance analysis and VLSI implementation of a reconfigurable shared buffer for high‐speed switch/router

Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high‐speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst‐case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer‐sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer‐sharing scheme by both a numerical model and extensive simulations under uniform and non‐uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 µm CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high‐speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers. Copyright © 2008 John Wiley & Sons, Ltd.     

Performance study of ATM multicast switching systems

We evaluate the performance of an N × N ATM discrete time multicast switch model with input queueing operating under two input access disciplines. First we present the analysis for the case of a purely random access discipline and subsequently we concentrate on a cyclic priority access based on a circulating token ring. In both cases, we focus on two HOL (head-of-line) packet service disciplines. Under the first (one-shot transmission discipline), all the copies generated by each HOL packet seek simultaneous transmission during the same time slot. Under the second service discipline (call-splitting), all HOL copies that can be transmitted in the same time slot are released while blocked copies compete for transmission in subsequent slots. In our analysis the performance measures introduced are the average packet delay in the input buffers as well as the maximum throughput of the switch. A significant part of the analysis is based on matrix geometric techniques. Finally, numerical results are presented and compared with computer simulations.     

Saturn: a terabit packet switch using dual round robin

Large input-output buffering with a moderate speedup has been widely considered as the most feasible solution for large-capacity switches. We propose a new terabit per second packet switch and call it the Saturn switch. It uses a simple dual round-robin arbitration scheme to schedule packets, and achieves high throughput and low statistical delay bound. It employs a bit-sliced crossbar fabric to switch packets at 10 Gb/s at inputs and outputs, and adopts a novel token-tunneling technique to arbitrate contending packets at high speed (e.g., within 10 ns), thus achieving a switch capacity of more than 1 Tb/s with existing electronic technology.     

Design of a non-blocking shared-memory copy network for ATM

The design of a copy network is presented for use in an ATM (asynchronous transfer mode) switch supporting BISDN (broadband integrated services digital network) traffic. Inherent traffic characteristics of BISDN services require ATM switches to handle bursty traffic with multicast connections. In typical ATM switch designs a copy network is used to replicate multicast cells before being forwarded to a point-to-point routeing network. In such designs, a single multicast cell enters the switch and is replicated once for each multicast connection. Each copy is forwarded to the routeing network with a unique destination address and is routed to the appropriate output port. Non-blocking copy networks permit multiple cells to be multicasted at once, up to the number of outputs of the copy network. Another critical feature of ATM switch design is the location of buffers for the temporary storage of transmitted cells. Buffering is required when multiple cells require a common switch resource for transmission. Typically, one cell is granted the resource and is transmitted while the remaining cells are buffered. Current switch designs associate discrete buffers with individual switch resources. Discrete buffering is not efficient for bursty traffic as traffic bursts can overflow individual switch buffers and result in dropped cells, while other buffers are under-used. A new non-blocking copy network is presented in this paper with a shared-memory input buffer. Blocked cells from any switch input are stored in a single shared input buffer. The copy network consists of three banyan networks and shared-memory queues. The design is scalable for large numbers of inputs due to low hardware complexity, O (N log₂ N), and distributed operation and control. It is shown in a simulation study that a switch incorporating the shared-memory copy network has increased throughput and lower buffer requirements to maintain low packet loss probability when compared to a switch with a discrete buffer copy network.