Hardware Organization to Achieve High-Speed Elliptic Curve Cryptography for Mobile Devices

Elliptic curve cryptography (ECC) is recognized as a fast cryptography system and has many applications in security systems. In this paper, a novel sharing scheme is proposed to significantly reduce the number of field multiplications and the usage of lookup tables, providing high speed operations for both hardware and software realizations.

Low-Complexity PAPR Reduction of MC-SS Signals in PAN

A peak-to-average power ratio (PAPR) reduction scheme with low complexity is proposed for the multicarrier spread spectrum (MC-SS) system in personal area network (PAN). Traditional clipping and filtering scheme requires a high oversampling rate to meet the emission mask requirements. This would cause high power consumption for mobile PAN devices in personal network. To solve the problem, upsampling is introduced between clipping and filtering in this paper to reduce the oversampling rate. A simplified implementation structure is also derived for the proposed scheme. Simulation results show that its complexity is about 65% of the conventional scheme while achieving satisfying performance.

Analysis of Lifting and B-Spline DWT Implementations for Implantable Neuroprosthetics

The large amount of data generated by neuroprosthetic devices requires a high communication bandwidth for extra-cranial transmission, critically limiting the number and utility of wireless implantable applications. Discrete wavelet transform (DWT) can provide exceptionally efficient data compression for neural records. Two energy efficient hardware implementations for one dimensional, multi-level, multi-channel DWT have been compared to identify the optimal approach for real time processing within an implanted device. This paper defines area-power minimized hardware implementation of the lifting and B-spline DWT schemes and analyzes their performance tradeoffs for implantable neuroprosthetics. The lifting scheme is shown to be increasingly superior for a larger number of input channels.

Feasibility analysis for service differentiation using an FDL bank in OBS networks

A service differentiation scheme in optical burst switching (OBS) networks, which is based on dynamic fiber delay line (FDL) assignment, is shown. The effectiveness of the scheme is validated by numerical analysis and extensive simulations. Especially, the feasibility conditions for the service differentiation scheme, which are considered as the minimum number of FDLs for each sub-FDL group, are displayed. The feasibility conditions are derived numerically, and are verified through extensive simulations. The results of extensive simulations show that the proposed scheme and the feasibility conditions are valid for service differentiation in OBS networks.

An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n

A pipelined Fast Fourier Transform and its inverse (FFT/IFFT) processor, which utilizes hardware resources efficiently, is proposed for MIMO-OFDM WLAN 802.11n. Compared with a conventional MIMO-OFDM implementation, (in which as many FFT/IFFT processors as the number of transmit/receive antennas is used), the proposed architecture (using hardware sharing among multiple data sequences) reduces hardware complexity without sacrificing system throughput. Further, the proposed architecture can support 1–4 input data sequences with sequence lengths of 64 or 128, as needed. The FFT/IFFT processor is synthesized using TSMC 0.18 um CMOS technology and saves 25% area compared to a conventional implementation approach using radix-2³ algorithm. The proposed FFT/IFFT processor can be configured to improve power efficiency according to the number of input data sequences and the sequence length. The processor consumes 38 mW at 75 MHz for one input sequence with 64-point length; it consumes 87 mW at 75 MHz for four input sequences with length 128-point and can be efficiently used for IEEE 802.11n WLAN standard.

Low-Power FPGA-Implementation of <Emphasis Type="Italic">atan</Emphasis>(<Emphasis Type="Italic">Y</Emphasis>/<Emphasis Type="Italic">X</Emphasis>) Using Look-Up Table Methods for Communication Applications

This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm or conventional LUT-based methods. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC or 46% lower than multipartite approach.

Performance analyses of serial-mode multicasting scheme in optical packet switched networks

The serial-mode multicasting scheme (SM), which can achieve duplication, buffering, and serial export of optical multicast packets in Optical Packet Switched (OPS) networks, is experimentally studied in this paper. Based on the experimental results, several limitations of this scheme, such as the multicast latency and signal impairment, are discussed. In addition, its performance in OPS networks is investigated by computer simulations. From the simulation results, a conclusion can be drawn that compared with the parallel-mode multicasting scheme (PM) producing multiple simultaneous copies of the optical packets by an optical power splitter or other devices, the SM scheme can increase the multicast success ratio and reduce the multicast retransmission times at the costs of some signal impairments and some extra transmission latency.

Error Probability for <Emphasis Type="Italic">L</Emphasis>-branch Coherent BPSK Equal Gain Combiners over Generalized Rayleigh Fading Channels

In this paper, a closed-form expression for the probability of error in a coherent BPSK system over Generalized Rayleigh fading channels is derived. An L-branch equal gain combining diversity scheme is used. Theoretical results for the probability of error are plotted for various values of the number of degrees of freedom (n) and diversity order (L). A simulation is performed and the simulated results are found to match very well with the theoretical results.

A Tool for Unbiased Comparison between Logarithmic and Floating-point Arithmetic

For applications requiring a large dynamic, real numbers may be represented either in floating-point, or in the logarithm number system (LNS). Which system is best for a given application is difficult to know in advance, because the cost and performance of LNS operators depend on the target accuracy in a highly non linear way. Therefore, a comparison of the pros and cons of both number systems in terms of cost, performance and overall accuracy is only relevant on a per-application basis. To make such a comparison possible, two concurrent libraries of parameterized arithmetic operators, targeting recent field-programmable gate arrays, are presented. They are unbiased in the sense that they strive to reflect the state-of-the-art for both number systems. These libraries are freely available at .

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Sub-Carrier and Band Hopped Orthogonal Frequency Division Multiple Access (OFDMA) Systems

This article proposes a novel way of grouping users in an orthogonal frequency division multiplexing (OFDM) communication link based on predefined criteria. The total available spectrum is divided into a number of bands equal to the number of groups. For efficient time-frequency resource allocation, sub-carrier and band hopping are used simultaneously. Under some constraints, sub-carriers can also be assigned to different users based on known channel characteristics using dynamic sub-carrier allocation. Sub-carrier and band hopping are used for mitigating the frequency selectivity of the wireless channel and for minimizing and avoiding interference in the system. The proposed scheme is equally applicable to both downlink and uplink.

SPOCS: Application Specific Signal Processor for OFDM Communication Systems

This paper presents an Application-Specific Signal Processor (ASSP) for Orthogonal Frequency Division Multiplexing (OFDM) Communication Systems, called SPOCS. The instruction set and its architecture are specially designed for OFDM systems, such as Fast Fourier Transform (FFT), scrambling/descrambling, puncturing, convolutional encoding, interleaving/deinterleaving, etc. SPOCS employs the optimized Data Processing Unit (DPU) to support the proposed instructions and the FFT Address Generation Unit (FAGU) to automatically calculate input/output data addresses. In addition, the proposed Bit Manipulation Unit (BMU) supports efficient bit manipulation operations. SPOCS has been synthesized using the SEC 0.18 μm standard cell library and has a much smaller area than commercial DSP chips. SPOCS can reduce the number of clock cycles over 8%~53% for FFT and about 48%~84% for scrambling, convolutional encoding and interleaving compared with existing DSP chips. SPOCS can support various OFDM communication standards, such as Wireless Local Area Network (WLAN), Digital Audio Broadcasting (DAB), Digital Video Broadcasting-Terrestrial (DVB-T), etc.

OVSF Code Sharing and Reducing the Code Wastage Capacity in WCDMA

The non quantized nature of user rate wastes the code capacity in Orthogonal Variable Spreading Factor Codes (OVSF) based Code Division Multiple Access (CDMA) systems. The code sharing scheme in multi code CDMA is proposed to minimize the code rate wastage. The scheme combines the unused (wastage) capacity of already occupied codes to reduce the code blocking problem. Simulation results are presented to show the superiority of the proposed code assignment scheme as compared to existing schemes.

MGFs for Rayleigh Random Variables

Expressions are given for the moment generating functions of the Rayleigh and generalized Rayleigh distributions.

A Novel Adaptive Detection Scheme based on Parallel Interference Cancellation for V-BLAST System

In this paper, in order to reduce the computational complexity of the detector of vertical Bell Laboratories layered space-time (V-BLAST) system over time-varying channels, an adaptive detection scheme is proposed based on parallel interference cancellation (PIC). The presented scheme has three units, which are primary adaptive detector, detection ordering determiner, and adaptive PIC detector. The proposed scheme can employ many of known adaptive algorithms for detection of V-BLAST system. In this paper, we present computational complexity of the proposed scheme using LMS, RLS, APA and AMSER adaptive algorithms and evaluate its performance with numerical simulations.

Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems

This paper investigates real-time DSP and FPGA implementations of a low complexity technique for asynchronous multiuser delay acquisition and time varying channel tracking for multipath channels in WCDMA and cdma2000 systems. A multiuser-LMS-like structure along with smoothing/prediction filters to improve tracking quality is reviewed. We investigate an efficient implementation based on FFT/IFFT technique, under fixed-point data representation and computation constraint. The measured BER reveals that fixed-point implementation is feasible at possibly no performance degradation. Based on real time execution made on a fixed-point high performance DSP, the maximum number of users is 15 and 17 for the proposed method and correlator, respectively. Due to the inherent parallelism and regular data flow FPGA implementation is suggested wherein a maximum number of users more than 80 can be afforded in Xilinx Virtex™ II Pro device.

Joint Carrier-Frequency Offset and Channel Estimation for MIMO-OFDM Transmission

In this paper, we consider a multiple-input multiple-output (MIMO) orthogonal frequency division multiplexing (OFDM) system operating over frequency-selective fading channels. We propose a novel scheme for joint carrier-frequency offset (CFO) and channel estimation based on the expectation–maximization (EM) algorithm. Furthermore, the Cramer-Rao bounds (CRBs) for both CFO and channel estimators are exploited to evaluate the performance of the proposed scheme. Computer simulations show that the proposed algorithm achieves almost ideal performance compared with the CRBs for both channel and frequency offset estimations.

A Novel Scheme for Power Amplifier Predistortion Based on Indirect Learning Architecture

Polynomial predistortion techniques for power amplifier (PA) non-linearities based on indirect learning architecture (IDLA) are widely used. The benefit of the IDLA leaves unnecessary the assumption of a model for PA, corresponding parameters estimation and inverse construction. In this paper, a novel scheme based on IDLA for PA predistortion is proposed. It has better power spectral density (PSD) and relative mean square error (RMSE) performances than the conventional IDLA-based methods especially when the PA non-liearity is more severe. Simulations and theoretical analysis verify the good performances of the proposed scheme.

Coding Schemes for Crisscross Error Patterns

This paper addresses two coding schemes which can handle emerging errors with crisscross patterns. First, a code with maximum rank distance, so-called Rank-Codes, is described and a modified Berlekamp–Massey algorithm is provided. Secondly, a Permutation Code based coding scheme for crisscross error patterns is presented. The influence of different types of noise are also discussed.

Methods for Compression of Feedback in Adaptive Multi-carrier 4G Schemes

In this paper, several algorithms for compressing the feedback of channel quality information are presented and analyzed. These algorithms are developed for a proposed adaptive modulation scheme for future multi-carrier 4G mobile systems. These strategies compress the feedback data and, used together with opportunistic scheduling, drastically reduce the feedback data rate. Thus the adaptive modulation schemes become more suitable and efficient to be implemented in future mobile systems, increasing data throughput and overall system performance.

An Area-Efficient Design of Variable-Length Fast Fourier Transform Processor

Fast Fourier transform (FFT) plays an important role in the orthogonal frequency division multiplexing (OFDM) communication systems. In this paper, we propose an area-efficient design of variable-length FFT processor which can perform various FFT lengths of 512/1,024/2,048/4,096/8,192 points used in OFDM-based communication systems, such as digital audio broadcasting (DAB), digital video broadcasting-terrestrial (DVB-T) and digital video broadcasting-handheld (DVB-H). To reduce computational complexity and chip area, we develop a new variable-length FFT architecture by devising a mixed-radix algorithm that consist of radix-2, radix-2² and radix-2/4/8 algorithms and optimizing the realization by substructure sharing. Based on this architecture, an area-efficient design of variable-length FFT processor is presented. By synthesized using the UMC 0.18 μm process, the area of the processor is 2.9 mm² and the 8,192-point FFT can be performed correctly up to 50 MHz with power consumption 823 mW under a 1.8 V supply voltage.