一种基于FPGA的红外图像预处理算法的实现

针对数字图像处理中预处理技术中的滤波算法运算量大,实时性差的问题,利用FPGA来完成此类算法具备一定的优势。该文提出了一种基于FPGA来实现box滤波算法的专用电路结构,并详细介绍了该结构中每一个关键模块的设计,最后给出了运算量和实时性分析。实验证明,该预处理算法在FPGA上的实现完全满足实时处理的需求,并达到各项性能指标。     

BP算法的脉动阵列结构在FPGA上的实现

提出了一种用于实现BP神经网络的串行输入串行输出的脉动阵列结构,在FPGA上实现了基于该阵列结构的用于进行“A－Z” 的印刷体字符识别系统。文中对FPGA中运算部件的微结构进行了讨论。实验结果表明,与软件实现相比用FPGA实现神经网络算法能够极大地提高BP网络的学习和分类速度。     

模糊CMAC的硬件结构分析及其FPGA实现

提出了模糊CMAC的一种基于FPGA的硬件实现方法。与其它FPGA实现的神经网络相比，包含了可以用于在线学习的权学习算法。分析了模糊CMAC的模型结构及其相应的硬件模块；用VHDL实现基于上述模块的模糊CMAC；对该模糊CMAC进行硬件综合与测试。测试结果表明：该模糊CMAC的FPGA实现方法是可行的，硬件化后的网络具有速度快、精度高、占用器件资源少的特点，是在SOPC中实现模糊CMAC模块的一种有效方法。     

BP算法的改进及用模拟电路实现的神经网络分类器

基于用模拟电路实现神经网络分类器的目的，对多层静态前馈神经网络的ＢＰ算法做了改进，采用线性限幅函数代替Ｓｉｇｍｏｉｄ函数作为神经元的激活函数，给出了改进的ＢＰ算法。对该算法性能的实验研究表明：这种改进算法不但方便了用线性模拟集成运算放大电路实现神经网络，而且具有学习速度快，映射能力强等优点。根据本文算法设计的神经网络分类器，无论是计算机仿真，还是模拟电路实现，都得到了比较高的识别率。     

基于时域算法面积优化的RS解码器VLSI设计

在分析RS解码算法的基础上,使用便于VLSI实现和流水线设计的矢量运算对该算法进行了全新的剖析和推演,并依据所采用矢量法则的运算特征提出一种面积优化的RS解码器体系结构.通过流水线、部件复用、折叠以及共享电路等设计,该体系结构大大提高了解码器主要运算部件的复用率,降低了电路复杂度,删减了冗余电路,缩减了电路规模.基于该体系结构设计的RS(204,188)解码器规模约为27,000门,与同类设计相比电路规模可降低39%,其已集成到一款HDTV信道调制解调芯片中并在实际中得到应用.     

XDL网表的前向电路图生成算法

作为描述FPGA（Field Programmable Gate Array）电路网表的XDL（Xilinx Design Language）描述文件，不仅能用于解析抽取FPGA设计的Inst电路单元和Net电路信号，而且能用于构建FPGA电路网表中信号传播的前向电路图模型。采用有向超图来构建FPGA电路网表中信号的前向拓扑关系，其中FPGA电路单元的有效管脚表示为超图结点，管脚间的外部连线、管脚内的电路逻辑功能表示为有向超边。给出了XDL网表级电路描述文件编译所需的EBNF表达式，提出了基于有向超图的XDL网表的前向电路图生成算法，进行了算法的时空复杂度分析。在Windows平台下基于RapidSmith开源软件实现了前向电路图生成算法，并选用基于Virtex-4型号FPGA测试用例的XDL网表，生成相应的前向电路图以验证XDL网表的前向电路图生成算法的正确性和有效性。     

基于虚电路的拒绝服务攻击防御研究*

设计了一种基于虚电路的拒绝服务保护基体系结构;介绍了基于虚电路的资源分配算法;在基于服务元网络体系结构的虚电路结构原型系统中实现了所提出的资源分配算法。与其他算法相比,该算法能有效对抗来自网络的恶意授权实体的拒绝服务攻击。     

基于FPGA的高速网络入侵检测系统

处理速度成为制约基于软件的网络入侵检测系统性能的瓶颈。文中提出了用可重配置硬件(FPGA)和商用千兆以太网MAC实现的网络入侵检测系统体系结构。在该体系结构中,网络数据包的特征匹配以及复杂协议分析等高强度的计算均由可重配置硬件电路完成,而使主机CPU更专注于对复杂入侵方式的检测和对入侵行为的实时响应。分析表明,该体系结构能够快速适应入侵特征变化对硬件电路的重配置需求,使网络入侵检测系统可以以线速处理网络数据包。     

基于DSP和CPLD的FPGA在线配置

介绍Xilinx公司FPGA的几种基本配置模式,在实际图像处理算法评估系统中设计了基于DSP和CPLD的配置电路,完成对系统中FPGA的在线从并行(SelectMAP)配置.减少器件数目,增加硬件系统的灵活性,并详细介绍该配置电路的具体实现过程和实现方法.     

一种基于忆阻特性的监督神经网络算法及电路设计

针对如何将忆阻器融入人工神经网络算法并进行硬件实现的问题,提出了一种在现场可编程逻辑门阵列(FPGA)平台上实现的基于忆阻特性的监督神经网络算法。该设计以忆阻器模块作为神经网络中的权值存储模块,构建误差反馈机制的监督学习。将该忆阻神经网络电路应用于图像分类问题,并进行了资源占用和处理速度的优化。实验结果表明其分类结果良好,在Cyclone Ⅱ:EP2C70F896I8平台上,整体网络算法占用11 773个逻辑单元(LEs),训练耗时0. 33 ms,图像的测试耗时10μs。这一工作对忆阻器和神经网络的结合提出了一个有益的参考。     

Implementation of multilayer neural network with threshold neurons and its analysis

In this paper, the implementation of new digital architecture for a multilayer neural network (MNN) with on-chip learning is discussed. The advantage of using the digital approach is that it can use state-of-the-art VLSI and ULSI implementation techniques. One of the major hard-ware problems in implementing a neural network is the activating function of the neurons. The proposed MNN uses a simple function as the neuron's activating function to reduce the circuit size. Moreover, the proposed MNN has an on-chip learning capability. As the learning algorithm, a backpropagation algorithm is modified for effective hard-wave implementation. The proposed MNN is implemented on a field-programmable gate array (FPGA) to evaluate the learning performance and circuit size. This work was presented, in part, at the Third International Symposium on Artificial Life and Robotics, Oita, Japan, January 19–21, 1998     

基于狼群算法的RBF神经网络模拟电路故障诊断

提出了一种新的方法来进行模拟电路故障诊断。该方法包括Haar的小波分解,对数据的归一化处理,以及用狼群算法优化RBF神经网络。用Haar小波对所得的电路原始故障数据集进行变换,然后对变换后的数据进行归一化处理,最终得出RBF神经网络训练所需的输入数据。针对RBF神经网络中隐层节点中心、基函数宽度及权值选取困难问题,使用狼群算法来优化训练RBF神经网络,以提高网络训练稳定性与诊断成功率。通过两个电路的诊断实例,来论述这些方法的具体实现过程,验证用该方法进行模拟电路故障诊断的可行性。     

细胞神经网在通信系统中的应用

细胞神经网(CNN)是一种大规模非线性模拟电路。它的两个重要特点是时间连续特性和局部连接特性,这使CNN在数字领域能实现实时、高速、并行的信号处理,并特别适于大规模集成电路(VLSI)的实现。本文阐述了CNN的结构和特点,并介绍了CNN在通信系统中的应用,主要包括信号处理及其硬件实现、混沌通信和通信中的优化问题等方面。     

The simplicial neural cell and its mixed-signal circuit implementation: an efficient neural-network architecture for intelligent signal processing in portable multimedia applications

This paper introduces a novel neural architecture which is capable of similar performance to any of the "classic" neural paradigms while having a very simple and efficient mixed-signal implementation which makes it a valuable candidate for intelligent signal processing in portable multimedia applications. The architecture and its realization circuit are described and the functional capabilities of the novel neural architecture called a simplicial neural cell are demonstrated for both regression and classification problems including nonlinear image filtering.     

Analog and digital FPGA implementation of BRIN for optimization problems.

The binary relation inference network (BRIN) shows promise in obtaining the global optimal solution for optimization problem, which is time independent of the problem size. However, the realization of this method is dependent on the implementation platforms. We studied analog and digital FPGA implementation platforms. Analog implementation of BRIN for two different directed graph problems is studied. As transitive closure problems can transform to a special case of shortest path problems or a special case of maximum spanning tree problems, two different forms of BRIN are discussed. Their circuits using common analog integrated circuits are investigated. The BRIN solution for critical path problems is expressed and is implemented using the separated building block circuit and the combined building block circuit. As these circuits are different, the response time of these networks will be different. The advancement of field programmable gate arrays (FPGAs) in recent years, allowing millions of gates on a single chip and accompanying with high-level design tools, has allowed the implementation of very complex networks. With this exemption on manual circuit construction and availability of efficient design platform, the BRIN architecture could be built in a much more efficient way. Problems on bandwidth are removed by taking all previous external connections to the inside of the chip. By transforming BRIN to FPGA (Xilinx XC4010XL and XCV800 Virtex), we implement a synchronous network with computations in a finite number of steps. Two case studies are presented, with correct results verified from simulation implementation. Resource consumption on FPGAs is studied showing that Virtex devices are more suitable for the expansion of network in future developments.     

Analog implementation of pulse-coupled neural networks

This paper presents a compact architecture for analog CMOS hardware implementation of voltage-mode pulse-coupled neural networks (PCNN). The hardware implementation methods shows inherent fault tolerance specialties and high speed, which is usually more than an order of magnitude over the software counterpart. A computational style described in this article mimics a biological neural network using pulse-stream signaling and analog summation and multiplication, pulse-stream encoding technique uses pulse streams to carry information and control analog circuitry, while storing further analog information on the time axis. The main feature of the proposed neuron circuit is that the structure is compact, yet exhibiting all the basic properties of natural biological neurons. Functional and structural forms of neural and synaptic functions are presented along with simulation results. Finally, the proposed design is applied to image processing to demonstrate successful restoration of images and their features.     

广义细胞自动机的结构及其硬件实现

该文作者曾提出了广义细胞自动机(GCA)的原理和并行算法．并且应用于网络快速包交换等动态优化问题．该文进一步讨论了这种新的广义细胞自动机的体系结构、算法的硬件实现及其电路设计。它们对于GCA的实际应用有重要意义．GCA结构不同于Hopfield神经网络(HNN)和细胞神经网络(CNN),GCA由多层次多粒度宏细胞组成塔形结构．它具有多粒度的宏细胞动力学特征．相同粒度宏细胞之间没有交互,但不同粒度宏细胞之间存在一定程度的交互或反馈．分析和实验表明．在问题求解的优化性、实时性、硬件实现复杂性等方面．该文给出的GCA结构和硬件实现．与HNN和CNN相比有诸多优点．     

基于SIMD的Square Root函数高性能实现与优化

在计算机图形学、积分计算和神经网络等应用场景中,平方根函数的高性能实现在构建处理器的基础软件生态中起到了十分重要的作用.随着A RM架构处理器得到广泛的使用,研究A RM架构下的函数快速算法实现变得更加关键.当前大量处理器都采用了SIMD架构,所以,研究基于SIMD实现高性能函数计算方法具有重要的研究意义和发展前景.因此,对平方根函数进行了高性能的实现与优化.通过分析IEEE 754标准的浮点数在内存中的存储格式,设计了高效的平方根函数算法;然后通过结合平方根倒数和泰勒公式算法,进一步提高了算法精度;最后通过SIMD优化进一步提升了算法性能.实验结果表明,在满足精度的前提下,相比于libm算法库,实现的平方根函数的,性能提高了约7倍,相比于A RM V8提供的计算平方根的指令在性能上提高了约3倍.     

Medical image diagnosis of lung cancer by multi-layered GMDH-type neural network self-selecting functions

In this study, a revised Group Method of Data Handling (GMDH)-type neural network self-selecting functions is applied to the computer aided image diagnosis (CAD) of lung cancer. The GMDH-type neural network algorithm has an ability of self-selecting optimum neural network architecture from three neural network architectures, such as sigmoid function neural network, radial basis function neural network and polynomial neural network. The GMDH-type neural network also has abilities of self-selecting the number of layers, the number of neurons in hidden layers and useful input variables. This algorithm is applied to CAD of lung cancers, and it is shown that this algorithm is useful for the CAD, and is very easy to apply to practical complex problems because optimum neural network architecture is automatically organized.     

Implementing regularly structured neural networks on the DREAMmachine

High-throughput implementations of neural network models are required to transfer the technology from small prototype research problems into large-scale "real-world" applications. The flexibility of these implementations in accommodating for modifications to the neural network computation and structure is of paramount importance. The performance of many implementation methods today is greatly dependent on the density and the interconnection structure of the neural network model being implemented. A principal contribution of this paper is to demonstrate an implementation method which exploits maximum amount of parallelism from neural computation, without enforcing stringent conditions on the neural network interconnection structure, to achieve this high implementation efficiency. We propose a new reconfigurable parallel processing architecture, the Dynamically Reconfigurable Extended Array Multiprocessor (DREAM) machine, and an associated mapping method for implementing neural networks with regular interconnection structures. Details of the system execution rate calculation as a function of the neural network structure are presented. Several example neural network structures are used to demonstrate the efficiency of our mapping method and the DREAM machine architecture on implementing diverse interconnection structures. We show that due to the reconfigurable nature of the DREAM machine, most of the available parallelism of neural networks can be efficiently exploited.