Effects of substrate design on underfill voiding using the low cost, high throughput flip chip assembly process and no-flow underfill materials

The formation of underfill voids is an area of concern in the low cost, high throughput, or "no-flow" flip chip assembly process. This assembly process involves placement of a flip chip device directly onto the substrate pad site covered with pre-dispensed no-flow underfill. The forced motion of chip placement causes a convex flow front to pass over pad and solder mask-opening features promoting void capture. This paper determines the effects of substrate design on the phenomena of underfill voiding using the no-flow process. A full-factorial design experiment analyzes several empirically determined factors that can affect void capture in no-flow processing. The substrate design parameters included pad height, solder mask opening height, pad/solder mask opening separation, and pad pitch. The process parameters include chip placement velocity and underfill viscosity. The process robustness is measured in terms of the number of voids created during chip placement, and is further analyzed for the location and any visible modes of void formation. The goal of the work is to determine improved substrate designs to minimize voiding in flip chip processing using no flow underfills.     

No-flow underfill process modeling and analysis for low cost, high throughput flip chip assembly

A new defect in which a chip "floats" over the board surface after chip placement is appearing in the low-cost, high-throughput flip chip on board (FCOB) assembly that is based on no-flow underfill. This defect has the potential to significantly lower process yield when process variables are not properly controlled. In fact, it was found that much of the yield loss observed post reflow is attributable to "chip floating." A process model has been developed that will allow an understanding of the underlying physics of the floating phenomena and identification of process variables so that this process defect can be eliminated. The critical process variables include chip placement speed, chip placement force, dwell time, deposited underfill mass and underfill material properties such as viscosity, density, surface tension, wetting speed on the board, etc. A test chip and board was specially designed so that chip floating over the board can be easily detected. To validate the model, the effects of the critical process variables on chip floating were investigated by a series of experiments, and the results were compared to the theoretical model's predictions.     

Double-layer no-flow underfill materials and process

The no-flow underfill has been invented and practiced in the industry for a few years. However, due to the interfering of silica fillers with solder joint formation, most no-flow underfills are not filled with silica fillers and hence have a high coefficient of thermal expansion (CTE), which is undesirable for high reliability. In a novel invention, a double-layer no-flow underfill is implemented to the flip-chip process and allows fillers to be incorporated into the no-flow underfill. The effects of bottom layer underfill thickness, bottom layer underfill viscosity, and reflow profile on the solder wetting properties are investigated in a design of experiment (DOE) using quartz chips. It is found that the thickness and viscosity of the bottom layer underfill are essential to the wetting of the solder bumps. Chip scale package (CSP) components are assembled using the double-layer no-flow underfill process. Silica fillers of different sizes and weight percentages are incorporated into the upper layer underfill. With a high viscosity bottom layer underfill, up to 40 wt% fillers can be added into the upper layer underfill and do not interfere with solder joint formation.     

Reliability assessment and hygroswelling modeling of FCBGA with no-flow underfill

In the flip-chip ball grid array (FCBGA) assembly process, no-flow underfill has the advantage over traditional capillary-flow underfill on shorter cycle time. Reliability tests are performed on both unmolded and molded FCBGA with three different types of no-flow underfill materials. The JEDEC Level-3 (JL3) moisture preconditioning, followed by reflow and pressure cooker test (PCT) is found to be a critical test for failures of underbump metallization (UBM) opening and underfill/die delamination. In this paper, various types of modeling techniques are applied to analyze the FCBGA-8×8 mm on moisture distribution, hygroswelling behavior, and thermomechanical stress. For moisture diffusion modeling, thermal-moisture analogy is used to calculate the degree of moisture saturation in the multi-material system of FCBGA. The local moisture concentration along the critical interface, e.g. die/underfill, is critical for delamination, because the moisture weakens the interfacial adhesion strength, generates internal vapor pressure during reflow, and induces tensile hygroswelling stress on UBM during PCT. The results of moisture distribution can be used as loading input for the subsequent hygroswelling modeling. The magnitude of hygroswelling stress acting on UBM is found to be greater than the thermal stress induced during reflow, both in tensile mode which may cause the UBM-opening failure. Underfill with lower saturated moisture concentration (C_sat) and coefficient of moisture expansion (CME) are found to induce lower UBM stress and has better reliability results. Molded package generally has higher stress level than unmolded package. Parametric studies are performed to study the effects of no-flow underfill materials, package type (molded vs. unmolded), die thickness, and substrate size on the stresses of UBM during reflow and PCT.     

FEM modeling of temperature distribution of a flip-chip no-flow underfill package during solder reflow process

Flip chip on organic substrate has relied on underfill to redistribute the thermomechanical stress and to enhance the solder joint reliability. However, the conventional flip-chip underfill process involves multiple process steps and has become the bottleneck of the flip-chip process. The no-flow underfill is invented to simplify the flip-chip underfill process and to reduce the packaging cost. The no-flow underfill process requires the underfill to possess high curing latency to avoid gelation before solder reflow so to ensure the solder interconnect. Therefore, the temperature distribution of a no-flow flip-chip package during the solder reflow process is important for high assembly yield. This paper uses the finite-element method (FEM) to model the temperature distribution of a flip-chip no-flow underfill package during the solder reflow process. The kinetics of underfill curing is established using an autocatalytic reaction model obtained by DSC studies. Two approaches are developed in order to incorporate the curing kinetics of the underfill into the FEM model using iteration and a loop program. The temperature distribution across the package and across the underfill layer is studied. The effect of the presence of the underfill fillet and the influence of the chip dimension on the temperature difference in the underfill layer is discussed. The influence of the underfill curing kinetics on the modeling results is also evaluated.     

Development of new no-flow underfill materials for both eutectic Sn-Pb solder and a high temperature melting lead-free solder

In recent years, no-flow underfill technology has drawn more attention due to its potential cost-savings advantages over conventional underfill technology, and as a result several no-flow underfill materials have been developed and reported. However, most of these materials are not suitable for lead-free solder, such as Sn/Ag (m.p. 225/spl deg/C), Sn/Ag/Cu (m.p. 217/spl deg/C), applications that usually have higher melting temperatures than the eutectic Sn-Pb solder (m.p. 183/spl deg/C). Due to the increasing environmental concern, the demand for friendly lead-free solders has become an apparent trend. This paper demonstrates a study on two new formulas of no-flow underfill developed for lead-free solders with a melting point around 220/spl deg/C. As compared to the G25, a no-flow underfill material developed in our research group, which uses a solid metal chelate curing catalyst to match the reflow profile of eutectic Sn-Pb solder, these novel formulas employ a liquid curing catalyst thus provides ease in preparation of the no-flow underfill materials. In this study, curing kinetics, glass transition temperature (Tg), thermal expansion coefficient (TCE), storage modulus (E') and loss modulus (E') of these materials were studied with a differential scanning calorimetry (DSC), a thermo-mechanical analysis (TMA), and a dynamic-mechanical analysis (DMA), respectively. The pot-life in terms of viscosity of these materials was characterized with a stress rheometer. The adhesive strength of the materials on the surface of silicon chips were studied with a die-shear instrument. The influences of fluxing agents on the materials curing kinetics were studied with a DSC. The materials compatibility to the solder penetration and wetting on copper clad during solder reflow was investigated with both eutectic Sn-Pb and 95.9Sn/3.4Ag/0.7Cu solders on copper laminated FR-4 organic boards.     

Influence of underfill materials on the reliability of coreless flip chip package

A flip chip package was assembled by using 6-layer laminated polyimide coreless substrate, eutectic Sn37Pb solder bump, two kinds of underfill materials and Sn_3.0Ag_0.5Cu solder balls. Regarding to the yield, the peripheral solder joints were often found not to connect with the substrate due to the warpage at high temperature, modification of reflow profile was benefit to improve this issue. All the samples passed the moisture sensitive level test with a peak temperature of 260 °C and no delamination at the interface of underfill and substrate was found. In order to know the reliability of coreless flip chip package, five test items including temperature cycle test (TCT), thermal shock test (TST), highly accelerated stress test (HAST), high temperature storage test (HTST) and thermal humidity storage test (THST) were done. Both of the two underfill materials could make the samples pass the HTST and THST, however, in the case of TCT, TST and HAST, the reliability of coreless flip chip package was dominated by underfill material. A higher Young’s modules of underfill, the more die crack failures were found. Choosing a correct underfill material was the key factor for volume production of coreless flip chip package.     

No-flow underfill flip chip assembly––an experimental and modeling analysis

In the flip-chip assembly process, no-flow underfill materials have a particular advantage over traditional underfill: the application and curing of the former can be undertaken before and during the reflow process. This advantage can be exploited to increase the flip-chip manufacturing throughput. However, adopting a no-flow underfill process may introduce reliability issues such as underfill entrapment, delamination at interfaces between underfill and other materials, and lower solder joint fatigue life. This paper presents an analysis on the assembly and the reliability of flip-chips with no-flow underfill. The methodology adopted in the work is a combination of experimental and computer-modeling methods. Two types of no-flow underfill materials have been used for the flip chips. The samples have been inspected with X-ray and scanning acoustic microscope inspection systems to find voids and other defects. Eleven samples for each type of underfill material have been subjected to thermal shock test and the number of cycles to failure for these flip chips have been found. In the computer modeling part of the work, a comprehensive parametric study has provided details on the relationship between the material properties and reliability, and on how underfill entrapment may affect the thermal–mechanical fatigue life of flip chips with no-flow underfill.     

Recent advances in flip-chip underfill: materials, process, and reliability

In order to enhance the reliability of a flip-chip on organic board package, underfill is usually used to redistribute the thermomechanical stress created by the coefficient of thermal expansion (CTE) mismatch between the silicon chip and organic substrate. However, the conventional underfill relies on the capillary flow of the underfill resin and has many disadvantages. In order to overcome these disadvantages, many variations have been invented to improve the flip-chip underfill process. This paper reviews the recent advances in the material design, process development, and reliability issues of flip-chip underfill, especially in no-flow underfill, molded underfill, and wafer-level underfill. The relationship between the materials, process, and reliability in these packages is discussed.     

Chemothermal modeling and finite-element analysis for microwave cure process of underfill in flip-chip packaging

The reaction kinetics of microwave cure process of underfill materials in flip-chip packaging was investigated with nonisothermal kinetic method and compared with that of the thermal cure. Three-dimensional (3-D) nonlinear cure kinetic and transient heat transfer coupled model was solved by finite-element method (FEM) to simulate the microwave cure process. The accuracy of the program was verified using a simple heat conduction case by commercial FEM software. Temperature and conversion inside underfill during microwave cure process were evaluated by solving the nonlinear anisotropic heat conduction equation including internal heat generation produced by exothermic chemical reactions. Numerical results show that the iteration calculations are very sensitive to small changes in time step sizes. It was also found that variable frequency microwave can process underfill materials with uniform conversion under different curing temperatures.     

底充胶固化工艺对低k倒装焊器件可靠性的影响

利用四点弯曲实验测试了一组芯片(30片)的强度,使用威布尔统计模型描述了芯片失效率的分布,预测了在后续热循环过程中芯片的失效概率。通过有限元软件研究了底充胶固化工艺对芯片上方垂直开裂应力、焊点等效塑性应变及低k层最大等效应力的影响。结果表明:与未经固化的相比,底充胶固化工艺使得芯片的失效率从0.08%增大到0.37%,焊点的等效塑性应变增大约7倍,低k层的最大等效应力增大约18%。     

Correlation of flip chip underfill process parameters and materialproperties with in-process stress generation

Electronic packaging designs are moving toward fewer levels of packaging to enable miniaturization and to increase performance of electronic products. One such package design is flip chip on board (FCOB). In this method, the chip is attached face down directly to a printed wiring board (PWB). Since the package is comprised of dissimilar materials, the mechanical integrity of the flip chip during assembly and operation becomes an issue due to the coefficient of thermal expansion (CTE) mismatch between the chip, PWB, and interconnect materials. To overcome this problem, a rigid encapsulant (underfill) is introduced between the chip and the substrate. This reduces the effective CTE mismatch and reduces the effective stresses experienced by the solder interconnects. The presence of the underfill significantly improves long term reliability. The underfill material, however, does introduce a high level of mechanical stress in the silicon die. The stress in the assembly is a function of the assembly process, the underfill material, and the underfill cure process. Therefore, selection and processing of underfill material is critical to achieving the desired performance and reliability. The effect of underfill material on the mechanical stress induced in a flip chip assembly during cure was presented in previous publications. This paper studies the effect of the cure parameters on a selected commercial underfill and correlates these properties with the stress induced in flip chip assemblies during processing     

Study on the relationship between the surface composition of copperpads and no-flow underfill fluxing capability

The purpose of this paper is to investigate the effect of copper pad surface composition on the wetting of solder bumps during reflow process for a certain no-flow underfill material. A purchased copper foil which is laminated on FR4 board is used as a control surface. Six different procedures are followed to prepare the surface of the copper foil with six different compositions. XPS is then used to analyze the surface compositions of the six surfaces and the control surface. An in-house developed G25 no-flow underfill encapsulant is used to examine the wetting status of eutectic solder balls on these copper surfaces. The correlation of the copper surface compositions with the solder wetting is then established. It is verified that the compositions of the copper foil surfaces strongly depend on the cleaning procedures. For G25 no-flow underfill material, copper oxide (CuO) is the main composition that prevents the solder ball from wetting the copper foils while the observed organic contamination does not have noticeable effect on the solder wetting     

基于动作类的虚拟拆装过程运动建模仿真

针对装备拆装过程存在的拆装对象动作繁多,缺乏对各种零部件拆装动作的统一,不便于仿真实现的问题,提出维修拆装动作类对拆装运动进行描述,结合UML拆装执行基本拆装动作次数的不同,结合面向对象的思想提出了拆装动作类的概念,对拆装过程中具有相同动作次数的零部件做统一描述。利用UML建立拆装动作类的类图,结合状态机和拆装动作类建立拆装过程的运动模型。拆装仿真实例验证了动作类和拆装运动模型的可行性和实用性。     

Application assessment of high throughput flip chip assembly for ahigh lead-eutectic solder cap interconnect system using no-flowunderfill materials

Flip chip on board (FCOB) is one of the most quickly growing segments in advanced electronic packaging. In many cases, assembly processes are not capable of providing the high throughputs needed for integrated surface mount technology (SMT) processing (Tummala et al, 1997). A new high throughput process using no-flow underfill materials has been developed that has the potential to significantly increase flip chip assembly throughput. Previous research has demonstrated the feasibility and reliability of the high throughput process required for FCOB assemblies. The goal of this research was to integrate the high throughput flip chip process on commercial flip chip packages that consisted of high lead solder balls on a polyimide passivated silicon die bonded with eutectic solder bumped pads on the laminate substrate interface (Qi, 1999). This involved extensive parametric experimentation that focused on the following elements: no-flow process evaluation and implementation on the commercial packages, reflow profile parameter effects on eutectic solder wetting of high lead solder bumps, interactions between the no-flow underfill materials and the package solder interconnect and tented via features, void capture and void formation during processing, and material set compatibility and the effects on long term reliability performance     

基于DSP硬解码的低成本高清屏媒系统

设计并实现了一种基于OMAP3730的低成本高清屏媒系统,能够充分发挥可编程C64+DSP的强大计算功能,利用硬件实现常用视频格式的高清硬解码播放,利用软件兼顾不常有视频格式的解码播放,同时针对屏媒系统的特点利用DSP实现转屏,达到在横屏和竖屏上的自适应播放的效果。本文网络版地址：http：//www.eepw.com.cn/article/273271.htm     

Optimizing design of triplexer chip with low insert loss and high isolation based on planar lightwave circuit

Design optimization of a novel integrated triplexer based on planar lightwave circuit (PLC) for fiber-to-the-home applica- tions is described. The two-mode interference coupler and Mach-Zehnder interference are used to construct the filter chip. Simulation results of high isolation and low insertion loss are gotten for proposed design. Technique tolerance is improved for fabricating device.     

Influence of transient flow and solder bump resistance on underfill process

The underfill flow process is one of the important steps in Microsystems technology. One of the best known examples of such a process is with the flip-chip packaging technology which has great impact on the reliability of electronic devices. For optimization of the design and process parameters or real-time feedback control, it is necessary to have a dynamic model of the process that is computationally efficient yet reasonably accurate. The development of such a model involves identifying any factors that can be neglected with negligible loss of accuracy. In this paper, we present a study of flow transient behavior and flow resistance due to the presence of an array of solder bumps in the gap. We conclude (1) that the assumption of steady flow in the modeling of the flow behavior of fluids in the flip-chip packaging technology is reasonable, and (2) the solder bump resistance to the flow can not be neglected when the clearance between any two solder bumps is less than 60-70 μm. We subsequently present a new model, which extends the one proposed by Han and Wang in 1997 by considering the solder bump resistance to the flow.     

A novel, zone based process monitoring method for low cost MCM-D substrates manufactured on large area panels

This paper describes a novel process monitoring method for low cost MCM-D substrates. By using large area panel processing the EU LAP project aims to reduce the manufacturing costs and to reach the target of 1 US$/in.². To achieve this cost reduction an efficient process control is essential to guarantee a high substrate yield. But when the panel size is increased from 4×4 up to 24×24 in.², the non-uniformity of process parameters is also increased, and new process monitoring challenges arise. Conventional methods, such as placing monitor structures along the panel border or inside the panel area, do not provide enough coverage of the panel centre or may require too much real estate. Our new method presents a solution for this coverage vs. area trade-off by dividing the large panels into zones, thus allowing to control local parameter drifts. The process monitor structures for this new method are laid out for minimum area consumption and maximum panel coverage without requiring additional process steps. A case study exemplifies the benefits of the proposed method.     

Mechanical loading of flip chip joints before underfill: the impact on yield and reliability

The underfill-facilitated migration from ceramic to lower cost laminate substrates has become a powerful enabler of direct chip attach by offering lower cost, greater electrical functionality, and a smaller system footprint over comparable packaging technologies. Once underfilled, flip chip on laminate has proven extremely reliable even in severe automotive environments. However, between the process steps of reflow and underfill cure, unprotected flip chip solder joints assembled to laminate boards are susceptible to damage and breakage if mishandled. Here, the survivability and long-term reliability of flip chip joints was studied over a range of applied strains. Mechanical loading of joints was applied via beam deflections of populated, but nonunderfilled, laminate boards. Electrical continuity was monitored before and after testing to determine when the load applied to the flip chip exceeded the joint fracture strength. The propensity for solder joint fracture was then calculated as a function of solder bump size and also as a function of strain rate. Analysis of the mechanical properties of solder revealed assembly strategies which reduce bump damage and eliminate yield loss during the process steps leading up to underfill cure. Both strained and unstrained units were then underfilled and cycled between −50 and +150 °C. While mechanical damage was evident in bump cross-sections of strained flip chip assemblies, the fatigue lives of underfilled solder joints were found to be independent of the size of mechanical loads applied before underfill.