Trends in low-cost, high-performance substrate technology

The trends in high density interconnection (HDI) multichip module (MCM) techniques that have the potential to reduce interconnection cost and production time are described. The implementation in laminated dielectric (MCM-L) technology of a workstation processor core illustrates current substrate technology capabilities. The design, routing, layout and thermal management of the processor core are described. Thin-film deposited dielectric (MCM-D) technology is discussed as a cost-effective method for future interconnection applications     

Early package analysis: considerations and case study

Several issues associated with multichip module (MCM) system design are discussed. An early analysis tool for evaluating the tradeoffs between a design and packaging technology is presented. A case study of a possible design point suggested by combining different package elements being used in MCMs settings is included. The case study indicates that the most effective packaging solution for high-performance applications, requiring multichip modules, will likely represent a progression from cofired ceramics (MCM-C) to a thin-film and hybrid cofired ceramic (MCM-D/C) module     

Development of an assembly process and reliability investigations for flip-chip LEDs using the AuSn soldering

 A packaging process for flip-chip LEDs (light emitting diodes) is described. The LEDs are picked and placed on a silicon substrate wafer. After reflow the substrates are individualized. AuSn solder is used for the interconnection. The solder compounds, Au and Sn, are electroplated separately: Sn on the silicon substrate and Au on the chip. The interconnections formed by tin-rich and by gold-rich intermetallic phases are compared. The metallurgy and the reliability of the LEDs are investigated. The superiority of the gold-rich interconnection is demonstrated. Received: 30 May 2001 / Accepted: 17 July 2001     

Development of a multichip module DSP

The signal processor packaging design (SPPD) general-purpose digital signal processor (DSP) architecture is discussed. SPPD is a highly modular processor architecture that is based on off-the-shelf components and that supports a multichip module (MCM) design implementation that delivers 400 million floating-point operations per second in a 75-g package. The interconnect-substrate design, MCM package assembly, MCM testing, and tradeoffs in size, weight, and cost of the SPPD packaging are described     

A low-cost through via interconnection for ISM WLP

Wafer level packaging (WLP) for image sensor device has the advantage of small size, high performance and low cost. In WLP technology, in order to form electrical interconnection from image sensor contact pad to the backside of the wafer, several structures have been developed, such as T-contact and through silicon via (TSV). In this paper, a wafer level package of image sensor with new type TSV electrical interconnection for image sensor pad is presented. The target of this development is to reduce process cost and difficulty, and increase yield of image sensor packaging. Key fabrication processes includes glass protecting wafer bonding, device wafer thinning, backside through via etching, via passivation layer deposition, pad oxide opening, via filling and backside re-routing layer formation, etc. Compared to large opening area of tapered via on the backside of CMOS image sensor wafer, only small opening area is need for making via interconnection with vertical sidewall presented in this paper. A fillet structure at bottom corner of via holes can help to reduce sequent process difficulty, so that low-cost and simplified unit processes are successfully adopted in the fabrication process for through via formation. The through via interconnection shows good electrical connection performance, and high-quality photo images are obtained by packaged image sensor device.     

3D MCM热分析技术的研究

三维多芯片组件(3DMCM-ThreeDimensionMulti-ChipModule)是近几年正在发展的一种电子封装技术。在3DMCM封装中,随着芯片封装密度的增加,对其热分析与热设计技术就显得越来越重要了。本文利用有限元方法,通过Ansys软件工具对某静态存储器组件(3DMCM模块)内部温度场进行了模拟仿真,并与实验数据进行了对比,获得了很好的分析效果,为3DMCM的可靠性设计提供了技术支持。     

Flexible Chip-Scale Package and Interconnect for Implantable MEMS Movable Microelectrodes for the Brain

We report here a novel approach called microelectromechanical systems (MEMS) microflex interconnect (MMFI) technology for packaging a new generation of bioMEMS devices that involve movable microelectrodes implanted in brain tissue. MMFI addresses the need for the following: (1) operating space for movable parts and (2) flexible interconnects for mechanical isolation. We fabricated a thin polyimide substrate with embedded bond pads, vias, and conducting traces for the interconnect with a backside dry etch, so that the flexible substrate can act as a thin-film cap for the MEMS package. A double-gold-stud-bump rivet-bonding mechanism was used to form electrical connections to the chip and also to provide a spacing of approximately 15-20 mum for the movable parts. The MMFI approach achieved a chip-scale package that is lightweight and biocompatible and has flexible interconnects and no underfill. Reliability tests demonstrated minimal increases of 0.35, 0.23, and 0.15 mOmega in mean contact resistances under high humidity, thermal cycling, and thermal shock conditions, respectively. High-temperature tests resulted in increases of > 90 and ~ 4.2 mOmega in resistance when aluminum and gold bond pads were used, respectively. The mean time to failure was estimated to be at least one year under physiological conditions. We conclude that MMFI technology is a feasible and reliable approach for packaging and interconnecting bioMEMS devices.     

树状结构多芯片组件互连网络延迟的研究

大多芯片组件互连传输线的电路模型中,必须同时考虑线电感和线电阻,因此其互连延迟的研究比传统的ＰＣＢ和ＩＣ互连更具复杂性。研究了具有树状拓扑结构的ＭＣＭ互连网络的延迟：在明确了ＭＣＭ互连延迟的独特点后,着重给出了树状结构互连网络冲激响应的矩的求法,从矩与延迟的密切关系中给出了求延迟的一种有效方法。     

Sea-of-leads MEMS I/O interconnects for low-k IC packaging

Technology feasibility of MEMS-type chip I/O interconnects (namely Sea-of-Leads or SoL) is demonstrated. Acting like a spring, a MEMS lead can provide high mechanical compliance to compensate for mismatch of coefficient of thermal expansion (CTE) between a Si chip and a composite substrate. The compliant interconnects can provide low-stress connection between a chip and a PWB substrate, and, therefore, are promising to enable wafer-level packaging of IC chips with mechanically weak low-k interlayer dielectrics (ILD). The compliant interconnection also eliminates the need for an expensive underfilling process, which is one of the key challenges for scaling of conventional controlled collapse chip connection (C4) solder bumps in organic flip-chip packages. For the first time, SoL MEMS interconnects were investigated through the whole procedure of process integration, assembly, as well as reliability assessment. Without underfill, the SoL MEMS interconnects survived more than 500 thermal cycles indicating a promising improvement over a regular C4 solder joint. Failure analysis suggests that the MEMS leads do not fracture while failure occurs close to solder-Cu pad interface due to a nonreliable joining. Full reliability potential of the SoL MEMS interconnects may be demonstrated upon optimization of PWB metallurgy, soldermask design and lead compliance.     

Multilayer polyimide film substrates for interconnections in microsystems

 Currently there is a great interest in flexible substrates for their use in the packaging of semiconductors. They allow high packaging density and permit mechanical motion of the components, if necessary. This paper describes a new substrate material which possesses a high flexibility and which can be used for the realization of interconnection cables and MCM-D. These substrates are not only highly flexible but also mechanically stable, chemically inert and can be produced with the same processes as those for rigid substrates. Received: 14 December 1998 / Accepted: 28 December 1998     

电子封装基板材料研究进展及发展趋势

基板材料在电子封装中主要起到半导体芯片支撑、散热、保护、绝缘及与外电路互连的作用。随着电子封装技术向着高频高速、多功能、高性能、小体积和高可靠性方向发展,电子封装基板材料在新一代电子封装材料中发挥着越来越重要的作用。科学与工业界对电子封装基板材料提出了更高的要求,同时也促进了电子封装基板材料飞速发展。文章分别针对三大类基板材料:陶瓷基板、复合材料基板和有机基板的特点、发展现状及未来发展趋势进行了阐述。     

三维封装叠层技术

三维封装技术是一种符合电子系统轻重量,小体积,高性能,低功耗的发展趋势的先进的封装技术,本文对三维封装技术进行了简要介绍,重点介绍了三维封装的叠层工艺和互连技术,阐述了三维封装技术的优点,。简要分析了三维封装技术所面临的问题。     

Poly(dimethylsiloxane)-Based Packaging Technique for Microchip Fluorescence Detection System Applications

A simplified integration process including packaging is presented, which enables the realization of the portable fluorescence detection system. A fluorescence detection microchip system consisting of an integrated p–i–n photodiode, an organic light-emitting diode as the light source, an interference filter, and a microchannel was developed. The on-chip fluorescence detector fabricated by poly(dimethylsiloxane) (PDMS)-based packaging had a thin-film structure. A silicon-based integrated p–i–n photodiode combined with an optical filter removed the background noise, which was produced by an excitation source, on the same substrate. The active area of the finger-type p–i–n photodiode was extended to obtain a higher detection sensitivity of fluorescence. The sensitivity and the limit of detection (LOD;$S/N = 3$) of the system were 0.198 nA/$mu$M and 10$mu$M, respectively. 1710     

MCM基板技术的研究

MCM(多芯片模块)基板技术是MCM技术的一个重要组成部分。该文从基板的结构、性能以及材料等多个方面逐一对5种主要的 MCM基板技术进行了分析。并从封装和应用的角度对MCM基板技术作了相关说明。     

ka频段片式一体化发射组件的设计与实现

介绍了一种ka频段片式一体化发射组件的研制方法和关键技术。为满足一体化片式组件小型化且工作频率高的要求,提出了一种集成天线辐射单元与射频模块三维垂直互联的方法,同时结合多功能芯片 (MFC)技术、多芯片组装(MCM)技术实现组件高密度集成。研制的一体化组件尺寸为48 mm×48 mm×6.3 mm、质量不超过100g,集成16个发射通道,每个通道包含6位数控移相器和5位数控衰减器。该组件集成度高、较传统组件在尺寸和重量上具有较大的优势。     

Addressing the challenges of advanced packaging and interconnection

The author contends that packaging and interconnection technology is undergoing significant changes to meet the rapidly evolving requirements of portable electronics products. The need for high density and high performance at low cost demands sophisticated developments in technology. Future portable equipment packaging requirements can be met only through advanced concepts, including multichip modules, tape-automated bonding, and flip-chip assembly. Supporting technologies, such as adhesive assembly, thermal management, and design tools must also make attendant advances. Consortium-based cooperative research and development of technologies addresses these needs, while also developing the essential vendor infrastructure     

Die separation and packaging of a surface micromachined piezoresistive pressure sensor

The processing steps required to obtain a useful single medical sensor assembly are discussed, starting from an entire silicon wafer with thousands of surface micromachined sensors. Experiences concerning dicing and packaging of a piezoresistive pressure sensor are described, together with proposals for solutions. Problems with fracture of essential sensor structures are solved by use of a wafer protection tape. Existing solutions for flip–chip bonding and design of substrate for electrical interconnection are pushed to their limits due to the very small size of the novel sensor. As many of the processes can be simplified by an improved MEMS design, critical points related to the design are addressed.     

Recent advances in conductive adhesives for direct chip attach applications

 Conductive adhesives are widely used in electronics packaging applications such as in naked chip attachment and interconnection, component fixing, display interconnection and for heat transfer purposes. This paper gives a summary of recent achievements in the use of conductive adhesives in direct flip-chip attach applications. Special emphasis is put on the emerging technology of using anisotropically conductive adhesives as electronics interconnection materials. Some flip-chip application examples on low-cost printed circuitry are given. These examples include flip-chip ACF bonded electronics SBU-based six layer board for Casio′s radio electronics as well as memory chips assembled with the same technique in the latest Hitachi laptop computer. Current research activities as well as achievements so far are also presented. Different possible failure mechanisms for conductive adhesives are elaborated. Finally, future challenges and development trends are discussed. The paper shows that conductive adhesives play a significant role in electronics packaging applications and more applications will be expected in the years to come. Received: 19 December 1997/Accepted: 25 January 1998     

Manufacturing and packaging of sensors for their integration in avertical MCM microsystem for biomedical applications

Demonstrates the feasibility of integrating fragile micromachined chips into a complex three-dimensional (3-D) multichip module (MCM) microsystem for a biomedical application. The system is based on the vertical integration of the different parts: micropumps and valves, a multisensor chip for on-line control of the system and a signal-processing chip. In this paper, packaging of the microsystem is studied in order to minimize the induced stress that can affect the integrity of the different micromachined parts of the system. Standard commercially available components and materials were used so as to minimize costs for the case of high volume packaging. For testing the approach, a multisensor chip which includes thin silicon membrane-based devices has been used as the main test structure to compare different packaging materials. In addition, for the fabrication of such a sensor chip in an efficient mode, technological modules needed to fabricate sensors on complementary metal-oxide-semiconductor (CMOS) wafers are discussed. The definition of standardized "add-on" sensor modules to the CMOS process of a foundry is intended to limit the development cost of smart sensors