Solution-Processed Bootstrapped Organic Inverters Based on P3HT With a High- $k$ Gate Dielectric Material

In this letter, the integration of a high-$k$ gate dielectric has been demonstrated for achieving low-operating-voltage organic field-effect transistors (OFETs) and circuits based on solution-processed poly(3-hexylthiophene) (P3HT). We have successfully demonstrated all-p-type organic circuits based on P3HT operating at below 4 V supply voltage. The switching behavior is improved by using the bootstrapping technique, with the bootstrapped inverter showing good results with a dc gain $(A_{v})$ of $-$ 1.7 and $V_{rm OH}$ and $V_{rm OL}$ values of 3.3 and 0.35 V, respectively. The output swing of the bootstrapped inverter is improved by about 40% when compared to that of simple all-p-type inverters, as demonstrated by using experimental characterizations.      

Analytical Model of $I$– $V$ Characteristics of Arbitrarily Shallow p-n Junctions

For the first time, an analytical model of arbitrarily shallow p-n junctions is presented. Depending on the junction depth, electrical characteristics of ultrashallow p-n junctions can vary from the characteristics of standard Schottky diodes to standard deep p-n junctions. This model successfully unifies the standard Schottky and p-n diode expressions. In the crossover region, where the shallow doping region can be totally depleted, electrical characteristics phenomenologically substantially different from typical diode characteristics are predicted. These predictions and the accuracy of the presented model are evaluated by comparison with the MEDICI simulations. Furthermore, ultrashallow $hbox{n}^{+}$-p diodes were fabricated, and the anomalous behavior in the crossover regime was experimentally observed.      

Proposal of Single Metal/Dual High-$k$ Devices for Aggressively Scaled CMISFETs With Precise Gate Profile Control

We have proposed a single metal/dual high-$k$ gate stack for aggressively scaled complementary metal–insulator–semiconductor field-effect transistors (MISFETs). The threshold voltage is controlled by the dual high-$k$ dielectrics, such as MgO- and $hbox{Al}_{2}hbox{O}_{3}$ -containing HfSiON for n- and p-type MISFETs, respectively. The gate profile is precisely controlled by taking advantage of a common gate electrode, which will suppress the variation in device performance. Based on this device concept, we have actually fabricated W/TiN/HfMgSiON n-type MISFETs and W/TiN/HfAlSiO p-type MISFETs and have successfully demonstrated a low threshold voltage operation for both of n- and p-type MISFETs.      

Eigendecomposition of Images Correlated on $S^{1}$, $S^{2}$, and $SO(3)$ Using Spectral Theory

Eigendecomposition represents one computationally efficient approach for dealing with object detection and pose estimation, as well as other vision-based problems, and has been applied to sets of correlated images for this purpose. The major drawback in using eigendecomposition is the off line computational expense incurred by computing the desired subspace. This off line expense increases drastically as the number of correlated images becomes large (which is the case when doing fully general 3-D pose estimation). Previous work has shown that for data correlated on S ¹ , Fourier analysis can help reduce the computational burden of this off line expense. This paper presents a method for extending this technique to data correlated on S ² as well as SO(3) by sampling the sphere appropriately. An algorithm is then developed for reducing the off line computational burden associated with computing the eigenspace by exploiting the spectral information of this spherical data set using spherical harmonics and Wigner-D functions. Experimental results are presented to compare the proposed algorithm to the true eigendecomposition, as well as assess the computational savings.     

22.7-dB Gain $-$19.7-dBm $ICP_{1{rm dB}}$ UWB CMOS LNA

A fully differential CMOS ultrawideband low-noise amplifier (LNA) is presented. The LNA has been realized in a standard 90-nm CMOS technology and consists of a common-gate stage and two subsequent common-source stages. The common-gate input stage realizes a wideband input impedance matching to the source impedance of the receiver (i.e., the antenna), whereas the two subsequent common-source stages provide a wideband gain by exploiting RLC tanks. The measurements have exhibited a transducer gain of 22.7 dB at 5.2 GHz, a 4.9-GHz-wide B _3dB, an input reflection coefficient lower than -10.5 dB, and an input-referred 1-dB compression point of -19.7 dBm, which are in excellent agreement with the postlayout simulation results, confirming the approach validity and the design robustness.     

Optimal $ Sigma Delta$ Modulator Architectures for Fractional-$ {N}$ Frequency Synthesis

This paper presents a comparative study of $Sigma Delta$ modulators for use in fractional-$ {N}$ phase-locked loops. It proposes favorable modulator architectures while taking into consideration not only the quantization noise of the modulator but also other loop nonidealities such as the charge pump current mismatch that contributes to the degradation in the synthesized tone's phase noise. The proper choice of the modulator architecture is found to be dependent upon the extent of the nonideality, reference frequency, and loop bandwidth. Three modulator architectures are then proposed for low, medium, and high levels of nonidealities.      

The Performance of Acoustic-Optical $Q$-switched Mode-Locking 1.34 $mu$m Nd:GdVO$_{4}$ Laser

A diode-end-pumped $Q$ -switched mode-locking $hbox{Nd:GdVO}_{4}$ laser operating at 1.34 $mu{hbox {m}}$ with an acousto-optical (AO) Q-switch in a compact V-type cavity was realized in our experiment for the first time. When the AO Q-switch repetition rate was 10 kHz, the maximum average output power of 750 mW and the pulse energy of 75 $muhbox{J}$ were obtained at the maximum incident pump power of 9 W. The mode-locking modulation depth of about 100% was obtained at certain pump power over the threshold. The mode-locked pulse inside in the $Q$-switched pulse had a repetition rate of 341 MHz, and its average pulsewidth was estimated to be about 350 ps. A developed rate equation model for the $Q$ -switched and mode-locked lasers with an AO Q-switch were proposed by using the hyperbolic secant functional methods. The results of numerical calculations of the rate equations were in good agreement with the experimental results.      

A $Q$– $f$ Droop Curve for Facilitating Islanding Detection of Inverter-Based Distributed Generation

This paper presents a new method for islanding detection of distributed generation (DG) inverter that relies on analyzing the reactive power versus frequency (Q-f) characteristic of the DG and the islanded load. The proposed method is based on equipping the DG interface with a Q-f droop curve that forces the DG to lose its stable operation once an islanding condition occurs. A simple passive islanding detection scheme that relies on frequency relays can then be used to detect the moment of islanding. The performance of the proposed method is evaluated under the IEEE 1547 and UL 1741 antiislanding test configuration. The studies reported in this paper are based on time-domain simulations in the power systems computer-aided design (PSCAD)/EMTDC environment. The results show that the proposed technique has negligible nondetection zone and is capable of accurately detecting islanding within the standard permissible detection times. In addition, the technique proves to be robust under multiple-DG operation.     

High-Performance Poly-Silicon TFTs Using a High-$k$ $hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is proposed for the first time. Compared to TFTs with a $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric, the electrical characteristics of poly-Si TFTs with a $hbox{PrTiO}_{3}$ gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher $I_{rm on}/I_{rm off}$ current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.      

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

Fringing-Induced Drain Current Improvement in the Tunnel Field-Effect Transistor With High- $kappa$ Gate Dielectrics

The tunnel field-effect transistor (tunnel FET) is a promising candidate for future CMOS technology. Its device characteristics have been subject to a variety of experimental and theoretical studies. In this paper, we evaluate the influence of using a high-$kappa$ gate dielectric in the tunnel FET compared to a standard silicon oxide with same equivalent oxide thickness, which exhibits a quite different behavior compared to a conventional MOSFET due to its totally different working principle. It turns out that the fringing field effect, while deteriorating conventional MOSFET characteristics, leads to a much higher on-current comparable with actual conventional MOSFETs, a subthreshold slope of the tunnel FET lower than the theoretical limit for conventional MOSFETs, and a massive improved inverter delay, underlining its prospect for future applications. This leads to the conclusion that high-$kappa$ materials with permittivities $≫$ 30 can advantageously be used in CMOS technology, giving rise to further technological development.      

Novel Low-$k$ Dielectric Buried-Layer High-Voltage LDMOS on Partial SOI

A high-voltage lateral double diffused metal–oxide–semiconductor transistor on partial silicon on insulator (PSOI) with a buried low-$k$ dielectric (LK PSOI) is proposed. The low-$k$ value enhances the electric field strength in the dielectric $(E_{I})$. The Si window not only makes the substrate share the breakdown voltage (BV) and modulates the field distribution in the SOI layer but also alleviates the self-heating effect. Compared with those of the conventional PSOI, the $E_{I}$ and BV of LK PSOI with $k_{I} = hbox{2}$ are enhanced by 74% and 19%, respectively.      

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

Addressing Cu/Low-$k$ Dielectric TDDB-Reliability Challenges for Advanced CMOS Technologies

Low-$k$ dielectrics, which are beneficial for chip resistance–capacitance ($RC$) delay improvement, crosstalk-noise minimization, and power-dissipation reduction, are indispensable for the continuous scaling of advanced VLSI circuits, particularly that of high-performance logic circuits. In this paper, several critical challenges for Cu/low-$k$ time-dependent dielectric-breakdown (TDDB)-reliability qualification will be reviewed. First, a low-$k$ TDDB field-acceleration model and its determination will be discussed. Second, the macroscopic interconnect line-to-line spacing variation across the wafer and the microscopic line-to-line spacing nonuniformity induced by line-edge roughness within the same test structure and their impacts on low- $k$ TDDB reliability will be carefully examined. The Weibull shape-parameter dependence on applied stress voltage due to such global and local spacing variations will be analyzed. Finally, the moisture effect on low-$k$ TDDB and capacitance stability as an example of the impact from process integration will be reported, demonstrating that low-$k$ TDDB is sensitive to back-end-of-the-line integration.      

A Comparative NBTI Study of $hbox{HfO}_{2}$, $hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in $hbox{HfO}_{2}/hbox{TiN}$, $ hbox{HfSiO}_{x}/hbox{TiN}$, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly $I_{rm DLIN}$ technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, $hbox{HfO}_{2}$ devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and $hbox{HfSiO}_{x}$ devices. $hbox{HfSiO}_{x}$ shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to $hbox{HfO}_{2}$, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between $ hbox{HfSiO}_{x}$ and $hbox{HfO}_{2}$ can be attributed to differences in N density in the $hbox{SiO}_{2}$ IL of these devices.      

A General and Reliable Model for Charge Pumping—Part II: Application to the Study of Traps in $hbox{SiO}_{2}$ or in High- $kappa$ Gate Stacks

The knowledge of the oxide trap characteristics, i.e., density, energy, and depth position, is of great interest not only for MOSFET with $hbox{SiO}_{2}$ but also for those with high-$kappa$ gate stacks. Using the general charge pumping model derived in Part I, this paper focuses on capture by tunneling and on the energy and depth regions probed in the experimental conditions that may allow the extraction of trap depth concentration profiles in the insulators. The impact on these regions of the asymmetry between the band offsets and of the electric field is studied.      

Two-Pulse $C$–$V$ : A New Method for Characterizing Electron Traps in the Bulk of $ hbox{SiO}_{2}/hbox{high-}kappa$ Dielectric Stacks

$hbox{SiO}_{2}/hbox{high-}kappa$ dielectric stack is a candidate for replacing the conventional $hbox{SiO}_{2}$-based dielectric stacks for future Flash memory cells. Electron traps in the high-$ kappa$ layer can limit the memory retention via the trap-assisted tunneling, and there is a pressing need for their characterization. A new two-pulse $C$ –$V$ measurement technique is developed in this letter, which, for the first time, allows us to probe the discharge of electron traps throughout the $hbox{SiO}_{2}/hbox{high-}kappa$ stack. It complements the charge pumping technique, which can only probe near-interface traps. It is demonstrated that a large number of electron traps, indeed, exist in the bulk of high-$kappa$ layer. Bulk electron traps also have different discharge characteristics from those near the $hbox{SiO}_{2}/hbox{high-}kappa$ interface.      

Reconstruction From Limited-Angle Projections Based on $delta-u$ Spectrum Analysis

This paper proposes a sparse representation of an image using discrete ?-u functions. A ?-u function is defined as the product of a Kronecker delta function and a step function. Based on the sparse representation, we have developed a novel and effective method for reconstructing an image from limited-angle projections. The method first estimates the parameters of the sparse representation from the incomplete projection data, and then directly calculates the image to be reconstructed. Experiments have shown that the proposed method can effectively recover the missing data and reconstruct images more accurately than the total-variation (TV) regularized reconstruction method.