Low-temperature conductance measurements of surface states in HfO2–Si structures with different gate materials

Metal-oxide-semiconductor capacitors based on HfO₂ gate stack with different metal and metal compound gates (Al, TiN, NiSi and NiAlN) are compared to study the effect of the gate electrode material on the trap density at the insulator–semiconductor interface.C–V and G–ω measurements were made in the frequency range from 1 kHz to 1 MHz in the temperature range 180–300 K. From the maximum of the plot G/ω vs. ln(ω) the density of interface states was calculated, and from its position on the frequency axis the trap cross-section was found. Reducing temperature makes it possible to decrease leakage current through the dielectric and to investigate the states located closer to the band edge.The structures under study were shown to contain significant interface trap densities located near the valence band edge (around 2×10¹¹ cm⁻²eV⁻¹ for Al and up to (3.5–5.5)×10¹² cm⁻² eV⁻¹ for other gate materials). The peak in the surface state distribution is situated at 0.18 eV above the valence band edge for Al electrode. The capture cross-section is 5.8×10⁻¹⁷ cm² at 200 K for Al–HfO₂–Si structure.     

Optimization of electric properties of high-k zirconium dioxide by varying deposition and annealing conditions

ZrO₂ thin films with a smooth surface were synthesized on silicon by atomic vapor deposition™ using Zr[OC(CH₃)₃]₄ as precursor. The maximum growth rate (7 nm min⁻¹) and strongest crystalline phase were obtained at 400 °C. The increase of the deposition temperature reduced the deposition rate to 0.5 nm min⁻¹ and changed the crystalline ZrO₂ phase from cubic/tetragonal to monoclinic. These films showed no enhancement of the dominating monoclinic phase by annealing. The values of the dielectric constant (up to 32) and leakage current density (down to 1.2×10⁻⁶ A cm⁻² at 1×10⁶ V cm⁻¹) varied depending on the deposition temperature and film thickness. The midgap density of interface states was N_it=5×10¹¹ eV⁻¹ cm⁻². The leakage current and the density of interface states were lowered by the annealing to 10⁻⁷ A cm⁻² at 1×10⁶ V cm⁻¹ and to 10¹⁰ eV⁻¹ cm⁻², respectively. However, this also led to a decrease of the dielectric constant.     

High temperature characterization of high-κ dielectrics on SiC

We have fabricated thin catalytic metal–insulator–silicon carbide based structure with palladium (Pd) gates using TiO₂ as the dielectric. The temperature stability of the capacitor is of critical importance for use in the fabrication of electronics for deployment in extreme environments. We have evaluated the response to temperatures in excess of 450 °C in air and observed that the characteristics are stable. Results of high temperature characterization are presented here with extraction of interface state density up to 650 °C. The results show that at temperatures below 400 °C the capacitors are stable, with a density of interface traps of approximately 6×10¹¹ cm² eV⁻¹. Above this temperature the C–V and G–V characteristics show the influence of a second set of traps, with a density around 1×10¹³ cm² eV⁻¹, which is close to that observed for slow states near the conduction band edge. The study of breakdown field as a function of temperature shows two distinct regions, below 300 °C where the breakdown voltage has a strong temperature dependence and above 300, where it is weaker. We hypothesize that the oxide layer dominates the breakdown voltage at low temperature and the TiO₂ layer above 300 °C. These results at high temperatures confirms the suitability of the Pd/TiO₂/SiO₂/SiC capacitor structure for stable operation in high temperature environments.     

Fabrication and characterization of pentacene-based transistors with a room-temperature mobility of 1.25 cm/Vs

Pentacene-based transistors produced by a novel neutral cluster beam deposition method were characterized, and the effects of the surface pretreatments were examined. Atomic force microscopy and X-ray diffraction showed that the cluster beams were quite efficient in growing high-quality, crystalline thin films on SiO₂ substrates at room-temperature without any thermal post-treatment, and that an amphiphilic surfactant, octadecyltrichlorosilane (OTS), enhances the packing density and crystallinity significantly. The observed field-effect mobilities (μ_eff) were among the best reported thus far: 0.47 and 1.25 cm²/Vs for the OTS-untreated and -pretreated devices, respectively. The device performance was found to be consistent with the estimated trap density and activation energy, which were derived from the transport characteristics for the temperature dependence of μ_eff in the range of 10−300 K.     

Control of Ga doping level in β-FeSi2 using Sn–Ga solvent

We have grown n- and p-type β-FeSi₂ single crystals by the temperature gradient solution growth method using Sn–Ga solvent. The conduction type and the carrier density of the crystals were controlled by the Ga composition in the Sn–Ga solvent. The conduction type was changed from n- to p-type between the Ga composition of 10.2 and 18.5 at% in the solvent. Depending on the Ga composition in the solvent, the carrier density of n- and p-type crystals was changed from 1.5×10¹⁷ to 3×10¹⁷ cm⁻³ and 4×10¹⁷ to 2×10¹⁹ cm⁻³, respectively. The activation energies of n-type crystals were 0.09–0.11 eV while that of p-type crystals were 0.02–0.03 eV.     

Electrically active defects induced by hydrogen and helium implantations in Ge

Results of a study of electrically active defects induced in Sb-doped Ge crystals by implantations of hydrogen and helium ions (protons and alpha particles) with energies in the range from 500 keV to 1 MeV and doses in the range 1×10¹⁰–1×10¹⁴ cm⁻² are presented in this work. Transformations of the defects upon post-implantation isochronal anneals in the temperature range 50–350 °C have also been studied. The results have been obtained by means of capacitance–voltage (C–V) measurements and deep-level transient spectroscopy (DLTS).It was found from an analysis of DLTS spectra that low doses (<5×10¹⁰ cm⁻²) of H and He ion implantations resulted in the introduction of damage similar to that observed after MeV electron irradiation. The Sb–vacancy complex was the dominant deep-level defect in the lightly implanted samples. After implantations with doses higher than 5×10¹⁰ cm⁻² peaks due to more complex defects were observed in the DLTS spectra. Implantations with heavy (5×10¹³ cm⁻²) doses of both H and He ions caused the formation of a sub-surface layer with a high (up to 1×10¹⁷ cm⁻³) concentration of donors. These donors were eliminated by anneals at temperatures in the range 100–200 °C. Heat treatments of the heavy proton-implanted Ge samples in the temperature range 250–300 °C resulted in the formation of shallow hydrogen-related donors, the concentration of which was the highest in a region close to the projected depth of implanted protons. The maximum peak concentration of the H-related donors was higher than 1×10¹⁵ cm⁻³ for a proton implantation dose of 1×10¹⁴ cm⁻².     

Low temperature processed hafnium oxide: Structural and electrical properties

In this work hafnium oxide (HfO₂) was deposited by r.f. magnetron sputtering at room temperature and then annealed at 200 °C in forming gas (N₂+H₂) and oxygen atmospheres, respectively for 2, 5 and 10 h. After 2 h annealing in forming gas an improvement in the interface properties occurs with the associated flat band voltage changing from −2.23 to −1.28 V. This means a reduction in the oxide charge density from 1.33×10¹² to 7.62×10¹¹ cm⁻². After 5 h annealing only the dielectric constant improves due to densification of the film. Finally, after 10 h annealing we notice a degradation of the electrical film's properties, with the flat band voltage and fixed charge density being −2.96 V and 1.64×10¹² cm⁻², respectively. Besides that, the leakage current also increases due to crystallization. On the other hand, by depositing the films at 200 °C or annealing it in an oxidizing atmosphere no improvements are observed when comparing these data to the ones obtained by annealing the films in forming gas. Here the flat band voltage is more negative and the hysteresis on the C–V plot is larger than the one recorded on films annealed in forming gas, meaning a degradation of the interfacial properties.     

ICP-induced defects in GaN characterized by capacitance analysis

The defects induced by inductively coupled plasma reactive ion etching (ICP-RIE) on a Si-doped gallium nitride (GaN:Si) surface have been analyzed. According to the capacitance analysis, the interfacial states density after the ICP-etching process may be higher than 5.4 × 10¹² eV⁻¹ cm⁻², compared to around 1.5 × 10¹¹ eV⁻¹ cm⁻² of non-ICP-treated samples. After the ICP-etching process, three kinds of interfacial states density are observed and characterized at different annealing parameters. After the annealing process, the ICP-induced defects could be reduced more than one order of magnitude in both N₂ and H₂ ambient. The H₂ ambient shows a better behavior in removing ICP-induced defects at a temperature around 500 °C, and the interfacial states density around 2.2 × 10¹¹ eV⁻¹ cm⁻²can be achieved. At a temperature higher than 600 °C, the N₂ ambient provides a much more stable interfacial states behavior than the H₂ ambient.     

An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO2 gate dielectrics

MOSFETs and MOSCs incorporating HfO₂ gate dielectrics were fabricated. The I_DS–V_DS, I_DS–V_GS, gated-diode and C–V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10³ cm/s and 1.63 × 10⁻⁶ s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10⁻¹⁵ cm² using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxide was also made.     

Charge trapping and interface states in hydrogen annealed HfO2–Si structures

Metal–oxide–semiconductor (MOS) capacitors based on HfO₂ gate stacks with Al and TiN gates are compared to study the effect of the gate electrode material to the properties of insulator–semiconductor interface. The structures under study were shown to contain interface trap densities of around 2 × 10¹¹ cm⁻² eV⁻¹ for Al gate and up to 5.5 × 10¹² cm⁻² eV⁻¹ for TiN gate. The peak in the surface state distribution was found at 0.19 eV above the valence band edge for Al electrode. The respective capture cross-section is 6 × 10⁻¹⁷ cm² at 200 K.The charge injection experiments have revealed the presence of hole traps inside the dielectric layer. The Al-gate structure contains traps with effective capture cross-section of 1 × 10⁻²⁰ cm², and there are two types of traps in the TiN-gate structure with cross-sections of 3.5 × 10⁻¹⁹ and 1 × 10⁻²⁰ cm². Trap concentration in the structure with Al electrode was considerably lower than in the structure with TiN electrode.     

Very wide current-regime operation of an InP/InGaAs tunneling emitter bipolar transistor (TEBT)

A novel InP/InGaAs tunneling emitter bipolar transistor (TEBT) is fabricated and demonstrated. The studied device can be operated under extremely wide collector current regime larger than 11 decades in magnitude (10⁻¹² to 10⁻¹ A). A current gain of 3.8 is obtained even operated at an ultra-low collector current of 3 × 10⁻¹² A (1.2 × 10⁻⁷ A/cm²). Furthermore, at lower V_BE bias regime (V_BE < 0.4 V), the low base current ideality factors are found. These results reveal that the tunneling probability for holes is very small. Therefore, the emitter injection efficiency is substantially improved.     

New dielectric material system of Nd(Mg1/2Ti1/2)O3–CaTiO3 at microwave frequency

The microwave dielectric properties of (1 − x)CaTiO₃–xNd(Mg_1/2Ti_1/2)O₃ (0.1  x  1.0) ceramics prepared by the conventional solid state method have been investigated. The system forms a solid solution throughout the entire compositional range. The dielectric constant decreases from 152 to 27 as x varies from 0.1 to 1.0. In the (1 − x)CaTiO₃–xNd(Mg_1/2Ti_1/2)O₃ system, the microwave dielectric properties can be effectively controlled by varying the x value. At 1400 °C, 0.1CaTiO₃–0.9Nd(Mg_1/2Ti_1/2)O₃ has a dielectric constant (ε_r) of 42, a Q × f value of 35 000 GHz and a temperature coefficient of resonant frequency (τ_f) of −10 ppm/°C. As the content of Nd(Mg_1/2Ti_1/2)O₃ increases, the highest Q × f value of 43 000 GHz for x = 0.9 is achieved at the sintering temperature 1500 °C.     

The properties of high-k gate dielectric films deposited on HRSOI

In this paper, HfO₂ dielectric films with blocking layers (BL) of Al₂O₃ were deposited on high resistivity silicon-on-insulator (HRSOI), and the interfacial and electrical properties are reported. High-resolution transmission electron microscopy (HRTEM) indicated that BL could thin the interfacial layer, keep the interface smooth, and retain HfO₂ amorphous after annealing. Energy dispersive X-ray spectroscopy (EDS) and X-ray photoelectron spectroscopy (XPS) confirmed that BL weaken Si diffusion and suppressed the further growth of HfSiO. Electrical measurements indicated that there was no hysteresis was observed in capacitance–voltage curves, and Flatband shift and interface state density is 0.05 V and −1.3 × 10¹² cm⁻², respectively.     

Transport and noise properties of CdTe(Cl) crystals

Experimental studies of transport and noise characteristics of CdTe (Cl doped) crystals, prepared by travelling heater method, have been carried out. The basic material is of p-type with p=1.8×10¹⁴ m⁻³, μ_h=0.0065 m² V⁻¹ s⁻¹, μ_e=0.13 m² V⁻¹ s⁻¹. The current and noise spectral density was measured as a function of the sample illumination, voltages across the sample and incident light wavelengths. Two types of effective charge carrier mobility are assumed: namely, the effective transport mobility, which is 0.065 m² V⁻¹ s⁻¹ and the effective noise mobility, which reaches a value of 0.125 m² V⁻¹ s⁻¹, both for high illumination. Under the same conditions, the density of light generated charge carrier pairs is 1.7×10¹⁵ m⁻³. Experimental results are in a good agreement with the four-level recombination model. The values of 1/f noise parameter α range from 4×10⁻⁴ to 2.5×10⁻³. The α parameter grows with almost the photocurrent square root. The signal-to-noise ratio improves if the electric field strength in the CdTe detector is set to a higher value.     

Determination of the electronic parameters of nanostructure SnO2/p-Si diode

The current–voltage and capacitance–voltage characteristics of the nanostructure SnO₂/p-Si diode have been investigated. The optical band gap and microstructure properties of the SnO₂ film were analyzed by optical absorption method and scanning electron microscopy, respectively. The optical band of the film was found to be 3.58 eV with a direct optical transition. The scanning electron microcopy results show that the SnO₂ film has the nanostructure. The ideality factor, barrier height and series resistance values of the nanostructure SnO₂/p-Si diode were found to be 2.1, 0.87 eV and 36.35 kΩ, respectively. The barrier height obtained from C–V measurement is higher than obtained from I–V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure SnO₂/p-Si interface. The interface state density of the diode was determined by conductance technique and was found to be 8.41 × 10¹⁰ eV⁻¹ cm⁻².It is evaluated that the nanostructure of the SnO₂ film has an important effect on the ideality factor, barrier height and interface state density parameters of SnO₂/p-Si diode.     

Electrical properties of oxidized polycrystalline silicon as a gate insulator for n-type 4H-SiC MOS devices

MOS capacitors were produced on n-type 4H-SiC using oxidized polycrystalline silicon (polyoxide). The polyoxide samples grown by dry oxidation without an anneal had a high interface state density (D_it) of 1.8 × 10¹² cm⁻² eV⁻¹ and the polyoxide samples grown by wet oxidation had a lower D_it of 1.2 × 10¹² cm⁻² eV⁻¹ (both at 0.5 eV below the conduction band). After 1 h Ar annealing, the D_it of wet polyoxide was reduced significantly to 2.6 × 10¹¹ cm⁻² eV⁻¹ (at 0.5 eV below the conduction band). Dry polyoxide exhibits higher breakdown electric fields than wet polyoxide. The interface quality and breakdown characteristics of polyoxide are comparable to published results of low-temperature CVD deposited oxides.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Interfaces between - and silicon

As the epitaxy of crystalline LaAlO₃ has not been realized yet, we investigated the use of a γ-Al₂O₃ buffer layer between the high-κ and the substrate. We firstly studied the structural matching of γ-Al₂O₃(0 0 1) with a Si(0 0 1)-p(2×1) reconstructed surface. According to experimental data and computations in the density functional theory framework, we found stable interfaces between γ-Al₂O₃ and Si which encounters surface reconstruction changes. These interfaces satisfy the criterion of an insulating buffer layer.     

Effects of oxygen partial pressure on structural and electrical characteristics of HfAlO high-k gate dielectric grown on strained SiGe by pulsed-laser deposition

Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si₈₃Ge₁₇ by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×10¹⁰ cm⁻² eV⁻¹ was obtained.     

A study on the improved programming characteristics of flash memory with Si3N4/SiO2 stacked tunneling dielectric

The programming characteristics of memories with different tunneling-layer structures (Si₃N₄, SiO₂ and Si₃N₄/SiO₂ stack) dielectrics are investigated using 2-D device simulator of MEDICI. It is theoretically confirmed that the memory with the SiO₂/Si₃N₄ stacked tunneling layer exhibits better programming characteristics than ones with single tunneling layer of SiO₂ or Si₃N₄ for programming by channel hot electron (CHE) injection. A 10-μs programming time with a threshold-voltage shift of 5 V can be obtained for the memory with SiO₂/Si₃N₄ stacked tunneling layer at V_cg = 10 V and V_ds = 3.3 V. This is attributed to the fact that the floating-gate voltage is close to drain voltage for the stacked tunneling dielectric (TD), and thus the CHE injection current is the largest. Furthermore, optimal substrate concentration is determined to be 5 × 10¹⁶–2 × 10¹⁷ cm⁻³, by considering a trade-off between the programming characteristics and power dissipation/lifetime of the devices. Lastly, the effects of interface states on the programming characteristics are investigated. Low interface-state density gives short programming time and small post-programming control-gate current.