Improved global rational approximation macromodeling algorithm fornetworks characterized by frequency-sampled data

Recently, the demand for high-performance wireless designs has been increasing while simultaneously the speed of high-end digital designs have crossed over the gigahertz range. New simulation tools which accurately characterize high-frequency interconnects are needed. This paper presents improvements to a new macromodeling algorithm. The algorithm employs curve-fitting techniques to achieve a pole-residue approximation of the frequency-sampled network. The frequency sampled S-parameters or Y-parameters can be obtained from measurement or full-wave simulation to characterize the frequency-dependent interconnects behavior. The improvements extend the approach to lossless structures, increase its accuracy with pole-clustering, and ensure its validity with a passivity test. This paper addresses some of the special considerations that must be made to the method so it can efficiently and accurately be applied to lossless circuits and structures. The resulting algorithm is now capable of accurately extracting a wide-band frequency domain macromodel from frequency-sampled data for either LC circuit (lossless) or RLC circuits (lossy). The frequency-domain macromodel can be linked to a SPICE circuit simulator for mixed signal circuit analysis using RF, analog, and digital circuits. The circuit can be simulated in the time domain using recursive convolution     

A new macromodeling approach for nonlinear microwave circuits basedon recurrent neural networks

A new macromodeling approach is developed in which a recurrent neural network (RNN) is trained to learn the dynamic responses of nonlinear microwave circuits. Input and output waveforms of the original circuit are used as training data. A training algorithm based on backpropagation through time is developed. Once trained, the RNN macromodel provides fast prediction of the full analog behavior of the original circuit, which can be useful for high-level simulation and optimization. Three practical examples of macromodeling a power amplifier, mixer, and MOSFET are used to demonstrate the validity of the proposed macromodeling approach     

Broadband Rational Macromodeling Based on the Adaptive Frequency Sampling Algorithm and the Partial Element Equivalent Circuit Method

The increasing operating frequencies in modern designs call for broadband macromodeling techniques. The problem of computing high-accuracy simulation models for high-speed interconnects is of great importance in the modeling arena. Nowadays, many full-wave numerical techniques are available that provide high accuracy, often at a significant cost in terms of memory storage and computing time. Furthermore, designers are usually only interested in a few electrical quantities such as port voltages and currents. So, model order reduction techniques are commonly used to achieve accurate results in a reasonable time. This paper presents a new technique, based on the partial element equivalent circuit method, which allows to generate reduced-order models by adaptively selecting the complexity (order) of the macromodel and suitable frequency samples. Thus, the proposed algorithm allows to limit the computing time while preserving the accuracy. Validation examples are given.     

A resetting algorithm for transient analysis of coupledtransmission line circuits

The numerical inversion of the Laplace transform has been used as an important tool for time domain analysis of high speed VLSI interconnects modeled by transmission line networks. In this paper, a resetting algorithm based on the numerical inversion of Laplace transform with Pade approximation is described. The initial conditions of coupled transmission lines required by the resetting algorithm are also derived. The new method results in substantial improvement of the accuracy of the numerical inversion of Laplace transform for solving transmission line networks with long transients. The new method also bridges the gap between two types of circuit simulation techniques, i.e., the numerical inversion of Laplace transform and the numerical integration     

A coupled efficient and systematic full-wave time-domain macromodeling and circuit Simulation method for signal integrity analysis of high-speed interconnects

This paper presents an accurate and systematic approach for analysis of the signal integrity of the high-speed interconnects, which couples the full-wave finite difference time domain (FDTD) method with scattering (S) parameter based macromodeling by using rational function approximation and the circuit simulator. Firstly, the full-wave FDTD method is applied to characterize the interconnect subsystems, which is dedicated to extract the S parameters of the subnetwork consisting of interconnects with fairly complex geometry. Once the frequency-domain discrete data of the S parameters of the interconnect subnetwork is constructed, the rational function approximation is carried out to establish the macromodel of the interconnect subnetwork by employing the vector fitting method, which provides a more robust and accurate solution for the overall problem. Finally, the analysis of the signal integrity of the hybrid circuit can be fulfilled by using the S parameters based macromodel synthesis and simulation program with integrated circuits emphasis (SPICE) circuit simulator. Numerical experiments demonstrate that the proposed approach is accurate and efficient to address the hybrid electromagnetic (interconnect part) and circuit problems, in which the electromagnetic field effects are fully considered and the strength of SPICE circuit simulator is also exploited.     

Time-domain modeling of high-speed interconnects by modified methodof characteristics

In this paper, a new model of lossy transmission lines is presented for the time-domain simulation of high-speed interconnects. This model is based on the modified method of characteristics (MMC). The characteristic functions are first approximated by applying lower order Taylor series in the frequency domain, and then a set of simple recursive formulas are obtained in the time domain. The formulas, which involve tracking performances between two ends of a transmission line, are similar to those derived by the method of characteristics for lossless and undistorted lossy transmission lines. The algorithm, based on the proposed MMC model, can efficiently evaluate transient responses of high-speed interconnects. It only uses the quantities at two ends of the lines, requiring less computation time and less memory space than required by other methods. Examples indicate that the new method has high accuracy and is very efficient for the time-domain simulation of interconnects in high-speed integrated circuits     

Passivity Compensation Algorithm for Method-of-Characteristics-Based Multiconductor Transmission Line Interconnect Macromodels

Computation of passive and compact macromodels of distributed interconnects has gained considerable importance during the recent years. Method of characteristics (MoC) is widely used for macromodeling of transmission lines, however, it may not be guaranteed passive. This paper presents a new algorithm for passivity enforcement of MoC-based macromodels of multiconductor transmission lines. The algorithm is based on the first-order perturbation of the related delay differential equations and can handle single as well as coupled interconnects. Necessary theoretical foundations and validating numerical results are presented.      

Investigation of tapered multiple microstrip lines for VLSIcircuits

The analysis of tapered, coupled microstrip transmission lines is presented. These lines, used as interconnects between integrated circuit devices, are modeled using an iteration-perturbation approach applied in the spatial domain. From this model, a frequency-dependent scattering parameter characterization is determined. A time-domain simulation of pulse propagation through the tapered, coupled microstrip lines is performed. The frequency-domain scattering parameters are inverse Fourier transformed to obtain the time-domain Green's function. The input pulse is convolved with the Green's function, and a Newton-Raphson algorithm is applied to account for nonlinear loads. Some experimental results are shown, and a simulation approximation is proposed     

Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels

With the ever increasing signal speeds, signal integrity issues of high-speed VLSI designs are presenting increasingly difficult challenges for state-of-the-art modeling and simulation tools. Consequently, characterization and passive macromodeling of high-speed modules such as interconnects, vias, and packages based on tabulated data are becoming important. This paper presents a fast algorithm for passivity verification and enforcement of large order macromodels of scattering parameter based multiport subnetworks. Numerous examples tested on this algorithm demonstrate a significant speed-up compared to the existing algorithms in the literature     

宽带延时宏模型高效延时提取方法

在高速电路信号完整性分析中,电大尺寸互连的建模仿真越来越普遍。而宽带延时宏模型以其仿真的高效性越来越受到重视,但现有延时提取方法比较耗时,限制了延时宏模型整体建模效率的提高。文中提出了一种基于傅里叶反变换IFT的高效延时提取方法。该方法不仅能从频域离散数据中提取多重延时项,而且可以较好地识别其中主要延时项以优化建模过程。文中在Matlab环境中实现该方法,并与目前常用的Gabor变换方法作对比。实验结果表明,文中方法大幅提高了延时提取效率,并且在宽带频域数据情况下具有较高的精度。     

一种提取多导体互连线等效电路频变分布参数的时域全波方法

本文给出了一种基于时域有限差分（ＦＤＴＤ）法，提取多导体互连线等效电路频变分布参数的时域全波方法．提取出的频率分布参数可用来研究含有多种导体互连线的高速集成电路（ＶＬＳＩ）系统的时域响应．由于在全波分析中电压和电流没有唯一的定义，本文还给出了基于不同电压、电流定义而得到的电路参数之间的转换关系．计算结果表明：这种方法是可靠的．     

Macromodeling of single-electron transistors for efficient circuitsimulation

In this study, the possibility of compact modeling in single-electron circuit simulation has been investigated. It is found that each Coulomb island in single-electron circuits can be treated independently when the interconnections between single-electron transistors are large enough and a quantitative criterion for this condition is given. It is also demonstrated that, in those situations, SPICE macromodeling of single-electron transistors can be used for efficient circuit simulation. The developed macromodel produces simulation results with reasonable accuracy and with orders of magnitude less CPU time than usual Monte Carlo simulations     

一种基于局部间断Galerkin方法的IC互连线电容提取策略

求解椭圆方程的局部间断Galerkin(LDG)方法具有精度高、并行效率高的优点,且能适用于各种网格。文章提出采用LDG方法来求解IC版图中电势分布函数满足的Laplace方程,从而给出了一个提取互连线电容的新方法。该问题的求解区域需要在矩形区域内部去掉数量不等的导体区域,在这种特殊的计算区域上,通过数值测试验证了LDG方法能达到理论的收敛阶。随着芯片制造工艺的发展,导体尺寸和间距也越来越小,给数值模拟带来新的问题。文章采用倍增网格剖分方法,大幅减小了计算单元数。对包含不同数量和形状导体的七个电路版图,用新方法提取互连线电容,得到的结果与商业工具给出的结果非常接近,表明了新方法的有效性。     

Generating compact, guaranteed passive reduced-order models of 3-D RLC interconnects

As very large scale integration (VLSI) circuit speeds and density continue to increase, the need to accurately model the effects of three-dimensional (3-D) interconnects has become essential for reliable chip and system design and verification. Since such models are commonly used inside standard circuit simulators for time or frequency domain computations, it is imperative that they be kept compact without compromising accuracy, and also retain relevant physical properties of the original system, such as passivity. In this paper, we describe an approach to generate accurate, compact, and guaranteed passive models of RLC interconnects and packaging structures. The procedure is based on a partial element equivalent circuit (PEEC)-like approach to modeling the impedance of interconnect structures accounting for both the charge accumulation on the surface of conductors and the current traveling in their interior. The resulting formulation, based on nodal or mixed nodal and mesh analysis, enables the application of existing model order reduction techniques. Compactness and passivity of the model are then ensured with a two-step reduction procedure where Krylov-subspace moment-matching methods are followed by a recently proposed, nearly optimal, passive truncated balanced realization-like algorithm. The proposed approach was used for extracting passive models for several industrial examples, whose accuracy was validated both in the frequency domain as well as against measured time-domain data.     

Application of recursive convolution to transient simulation of interconnects using a hybrid phase-pole macromodel

A hybrid phase-pole macromodel (HPPM), which explicitly includes phase shifts (time delays) in addition to the system poles, was recently developed for modeling interconnects. In this paper, the HPPM is applied to the transient simulation of interconnects. First, the time-domain source waveform is expanded in terms of triangular expansion functions. Knowledge of the triangle impulse response (TIR) for an interconnect, which is represented in the form of an HPPM, then allows for the time domain simulation of the interconnect. A recursive convolution algorithm is adopted to carry out the required convolutions efficiently in the transient simulator. Combining this transient simulator with an HPPM extractor yields a transient interconnect signal analysis tool.     

Variation-aware approaches with power improvement in digital circuits

In submicron technology, during the fabrication process factors like lithography and lens defect can change some of the physical parameters of transistors and interconnects. This change can modify the transistor electrical characteristics such as current, threshold voltage and gate capacitance, and thus it causes variation in power, delay and performance of the circuit. Process variation has become one of designer׳s challenges to the point that in below 45 nm technology it is considered as the most important issue in reliability. Power consumption and transistors variation are limiting factors to physical scalability. In this paper, we propose two approaches to reduce D2D and WID variations effects on digital CMOS circuits, at design time. The first approach concerns a variation-aware algorithm capable of extracting optimal design parameters to decrease variation and power. The second approach, using transistor stacking will help further reduce variation and power. Applying the algorithm on a digital design and according to parameters behavior in the presence of variation, we extract for each parameter value that will lead to power and variation reduction. On the other hand, with the stacking approach only basic gates are considered and subsequently gate configurations that reduce power and variation are proposed. The proposed approaches could be used identically for synchronous and asynchronous circuits. To prove this claim, we apply our approaches to a network-on-chip asynchronous router and a circuit from the ISCAS85 benchmark. All simulations are done in 32 nm technology using the HSPICE tool. The proposed algorithm similar to Monte Carlo simulation achieves the same results; however with lower execution time. The application of stacking approach to both asynchronous router and ISCAS85 circuit reduces variation effects up to 40.9% and 13.35%, respectively.     

Nouvelle expression temporelle de ľimpédance interne des conducteurs à section rectangulaire

In this paper, a new time domain internal impedance formula for characterizing the skin effect in interconnects of rectangular cross section is proposed. The comparison with the simulation results of a method involving frequency domain exact formula validates the present model and illustrates its accuracy. We have also shown the lack of precision of the formulations based on conductor losses varying as √ f In order to predict the responses of lossy planar transmission lines, the used methods are the time domain — frequency domain transformation (tdfd) and the finite difference time domain algorithm (fdtd). Theses techniques of analysis are applied to the mtl equations under quasi — tem approximation.     

Delay extraction-based passive macromodeling techniques for transmission line type interconnects characterized by tabulated multiport data

This paper introduces a novel algorithm for delay extraction-based passive macromodeling of multiconductor transmission line type interconnects characterized by multiport (Y, Z, S, or H) tabulated parameters. The algorithm determines a unique logarithm of the H parameters, which is then approximated using a low-order rational function. Subsequently, the DEPACT (delay extraction-based passive compact transmission line macromodel) algorithm is applied to obtain a passive and causal macromodel for SPICE simulation. The new method leads to compact, low-order macromodels resulting in faster transient simulations.     

Circuit models for three-dimensional geometries includingdielectrics

The partial element equivalent circuit (PEEC) approach has proved useful for modeling many different electromagnetic problems. The technique can be viewed as an approach for the electrical circuit modeling for arbitrary 3-D geometries. Recently, the authors extended the method to include retardation with the rPEEC models. So far the dielectrics have been taken into account only in an approximate way. In this work, they generalize the technique to include arbitrary homogeneous dielectric regions. The new circuit models are applied in the frequency as well as the time domain. The time solution allows the modeling of VLSI systems which involve interconnects as well as nonlinear transistor circuits     

Measurements and extractions of parasitic capacitances in ULSI layouts

This paper deals with the extraction of parasitic capacitances of interconnects in submicron layouts. It is well known that, in integrated circuits, the signal delay due to interconnects is comparable to that of gates. This aspect becomes particularly important, for example, during the design of clock trees in high-speed applications. In general, capacitance extraction is carried out with software tools but they should be validated on a set of geometrical structures, which have been accurately characterized and that are representative of the circuit layouts. Experimental characterization of these structures and their set up in a golden set of measures is still a challenging task. In this paper, we first describe some experimental approaches to measure capacitances of structures from the golden set and in particular we identify a high accuracy transducer based on pass-gate transistors. We then propose a software implementation of the floating random walk algorithm that solves the drawbacks in the extraction of capacitances of interconnects in a nonhomogeneous medium as an industrial layout. Finally, experimental and simulation results are presented, validating the adopted approach.