基于磷钝化栅介质的1.2kV 4H-SiC DMOSFET

本文对比了NO退火和磷掺杂两种栅钝化工艺,其中磷钝化采用了平面扩散源进行掺杂,通过C-V特性进行了4H-SiC/SiO₂界面特性评价,使用Terman法分析计算获得距导带底0.2-0.4eV范围内界面态密度.结果表明引入磷比氮能更有效降低界面态密度,提高沟道载流子迁移率.其次,对比了两种栅钝化工艺制备的4H-SiC DMOSFET器件性能,实验表明采用磷钝化工艺处理的器件性能更优.最后,基于磷掺杂钝化工艺首次制备出击穿电压为1200V、导通电阻为20mΩ、漏源电流为75 A、阈值电压为2.4V的4H-SiC DMOSFET.     

P-type 4H and 6H-SiC high-voltage Schottky barrier diodes

High-voltage Schottky barrier diodes have been successfully fabricated for the first time on p-type 4H- and 6H-SiC using Ti as the barrier metal. Good rectification was confirmed at temperatures as high as 250°C. The barrier heights were estimated to be 1.8-2.0 eV for 6H-SiC and 1.1-1.5 eV for 4H-SiC at room temperature using both I-V and C-V measurements. The specific on resistance (R_on,sp) for 4H- and 6H-SiC were found to be 25 mΩ cm^-2 and 70 mΩ cm^-2 at room temperature. A monotonic decrease in resistance occurs with increasing temperature for both polytypes due to increased ionization of dopants. An analytical model is presented to explain the decrease of R_on,sp with temperature for both 4H and 6H-SiC which fits the experimental data. Critical electric field strength for breakdown was extracted for the first time in both p-type 4H and 6H-SiC using the breakdown voltage and was found to be 2.9×10⁶ V/cm and 3.3×10⁶ V/cm, respectively. The breakdown voltage remained fairly constant with temperature for 4H-SiC while it was found to decrease with temperature for 6H-SiC     

Nitrogen Implantation to Improve Electron Channel Mobility in 4H-SiC MOSFET

Normally off 4H-SiC MOSFET devices have been fabricated on a p-type semiconductor and electrically characterized at different temperatures. A gate oxide obtained by nitrogen ion implantation performed before the thermal oxidation of SiC has been implemented in n-channel MOSFET technology. Two samples with a nitrogen concentration at the SiO₂/SiC interface of 5 X 10¹⁸ and 1.5 X 10¹⁹ cm^-3 and one unimplanted sample have been manufactured. The sample with the highest N concentration at the interface presents the highest channel mobility and the lowest threshold voltage. For increasing temperature, in all the samples, the threshold voltage decreases, and the electron channel mobility increases. The latter case attains a maximum value of about 40 cm²/V ldr s at 200degC for the sample with the highest N concentration. These trends are explained by the reduction of interface electron traps in the upper half of the band gap toward the conduction band edge. These results demonstrate that N implantation can be effectively used to improve the electrical performances of an n-type surface channel 4H-SiC MOSFET.     

Ge-Interface Engineering With Ozone Oxidation for Low Interface-State Density

Passivation of Ge has been a critical issue for Ge MOS applications in future technology nodes. In this letter, we introduce ozone oxidation to engineer Ge/insulator interface. Density of interface states (D_it) across the bandgap and close to the conduction band edge was extracted using conductance technique at low temperatures. D_it dependence on growth conditions was studied. Minimum D_it of 3 times 10¹¹ cm^-2V^-1 was demonstrated. Physical quality of the interface was investigated through Ge 3d spectra measurements. We found that the interface and D_it are strongly affected by the distribution of oxidation states and the quality of the suboxide.     

Low Dit, thermodynamically stable Ga2O3-GaAs interfaces: fabrication, characterization, and modeling

Thermodynamically stable, low D_it amorphous Ga₂ O₃-(100) GaAs interfaces have been fabricated by extending molecular beam epitaxy (MBE) related techniques. We have investigated both in situ and ex situ Ga₂O₃ deposition schemes utilizing molecular beams of gallium oxide. The in situ technique employs Ga₂O₃ deposition on freshly grown, atomically ordered (100) GaAs epitaxial films in ultrahigh vacuum (UHV); the ex situ approach is based on thermal desorption of native GaAs oxides in UHV prior to Ga₂O₃ deposition. Unique electronic interface properties have been demonstrated for in situ fabricated Ga₂O₃-GaAs interfaces including a midgap interface state density D_it in the low 10¹⁰ cm^-2 eV^-1 range and an interface recombination velocity S of 4000 cm/s. The existence of strong inversion in both n- and p-type GaAs has been clearly established. We will also discuss the excellent thermodynamic and photochemical interface stability. Ex situ fabricated Ga₂O₃-GaAs interfaces are inferior but still of a high quality with S=9000 cm/s and a corresponding D_it in the upper 10¹⁰ cm^-2 eV^-1 range. We also developed a new numerical heterostructure model for the evaluation of capacitance-voltage (C-V), conductance-voltage (G-V), and photoluminescence (PL) data. The model involves selfconsistent interface analysis of electrical and optoelectronic measurement data and is tailored to the specifics of GaAs such as band-to-band luminescence and long minority carrier response time τ_R. We will further discuss equivalent circuits in strong inversion considering minority carrier generation using low-intensity light illumination     

High temperature formed SiGe p-MOSFETs with good devicecharacteristics

We have used a simple process to fabricate Si_0.3Ge_0.7/Si p-MOSFETs. The Si_0.3Ge _0.7 is formed using deposited Ge followed by 950°C rapid thermal annealing and solid phase epitaxy that is process compatible with existing VLSI. A hole mobility of 250 cm²/Vs is obtained from the Si_0.3Ge_0.7 p-MOSFET that is ~two times higher than Si control devices and results in a consequent substantially higher current drive. The 228 Å Si_0.3Ge_0.7 thermal oxide grown at 1000°C has a high breakdown field of 15 MV/cm, low interface trap density (D_it) of 1.5×10¹¹ eV^-1 cm^-2, and low oxide charge of 7.2×10¹⁰ cm^-2. The source-drain junction leakage after implantation and 950°C RTA is also comparable with the Si counterpart     

Improved inversion channel mobility for 4H-SiC MOSFETs followinghigh temperature anneals in nitric oxide

Results presented in this letter demonstrate that the effective channel mobility of lateral, inversion-mode 4H-SiC MOSFETs is increased significantly after passivation of SiC/SiO₂ interface states near the conduction band edge by high temperature anneals in nitric oxide. Hi-lo capacitance-voltage (C-V) and ac conductance measurements indicate that, at 0.1 eV below the conduction band edge, the interface trap density decreases from approximately 2×10¹³ to 2×10¹² eV^-1 cm^-2 following anneals in nitric oxide at 1175°C for 2 h. The effective channel mobility for MOSFETs fabricated with either wet or dry oxides increases by an order of magnitude to approximately 30-35 cm²/V-s following the passivation anneals     

Electrical conduction and dielectric breakdown in aluminum oxideinsulators on silicon

Leakage currents and dielectric breakdown were studied in MIS capacitors of metal-aluminum oxide-silicon. The aluminum oxide was produced by thermally oxidizing AlN at 800-1160°C under dry O₂ conditions. The AlN films were deposited by RF magnetron sputtering on p-type Si (100) substrates. Thermal oxidation produced Al ₂O₃ with a thickness and structure that depended on the process time and temperature. The MIS capacitors exhibited the charge regimes of accumulation, depletion, and inversion on the Si semiconductor surface. The best electrical properties were obtained when all of the AlN was fully oxidized to Al₂O₃ with no residual AlN. The MIS flatband voltage was near 0 V, the net oxide trapped charge density, Q_0x, was less than 10¹¹ cm ^-2, and the interface trap density, D_it, was less than 10¹¹ cm^-2 eV^-1, At an oxide electric field of 0.3 MV/cm, the leakage current density was less than 10^-7 A cm^-2, with a resistivity greater than 10 ¹² Ω-cm. The critical field for dielectric breakdown ranged from 4 to 5 MV/cm. The temperature dependence of the current versus electric field indicated that the conduction mechanism was Frenkel-Poole emission, which has the property that higher temperatures reduce the current. This may be important for the reliability of circuits operating under extreme conditions. The dielectric constant ranged from 3 to 9. The excellent electronic quality of aluminum oxide may be attractive for field effect transistor applications     

Argon ion-implantation on polysilicon or amorphous-silicon forboron penetration suppression in p+ pMOSFET

In this paper, a technique to use Ar ion-implantation on the p⁺α-Si or poly-Si gate to suppress the boron penetration in p⁺ pMOSFET is proposed and demonstrated. An Ar-implantation of a dose over 5×10¹⁵ cm^-2 is shown to be able to sustain 900°C annealing for 30 min for the gate without having the underlying gate oxide quality degraded. It is believed to be due to gettering of fluorine, then consequently boron, by the bubble-like defects created by the Ar implantation in the p⁺ gate region to reduce the B penetration. Excellent electrical characteristics like dielectric breakdown (E_bd), interface state density (D_it), and charge-to-breakdown (Q_bd) on the gate oxide are obtained. The technique is compatible to the present CMOS process. The submicron pMOSFET fabricated by applying this technique exhibit better subthreshold characteristics and hot carrier immunity     

Schottky barrier height of a new ohmic contact NiSi2 to n-type 6H-SiC

We present a new ohmic contact material NiSi₂ to n-type 6H-SiC with a low specific contact resistance. NiSi₂ films are prepared by annealing the Ni and Si films separately deposited on (0 0 0 1)-oriented 6H-SiC substrates with carrier concentrations (n) ranging from 5.8×10¹⁶ to 2.5×10¹⁹ cm⁻³. The deposited films are annealed at 900 °C for 10 min in a flow of Ar gas containing 5 vol.% H₂ gas. The specific contact resistance of NiSi₂ contact exponentially decreases with increasing carrier concentrations of substrates. NiSi₂ contacts formed on the substrates with n=2.5×10¹⁹ cm⁻³ show a relatively low specific contact resistance with 3.6×10⁻⁶ Ω cm². Schottky barrier height of NiSi₂ to n-type 6H-SiC is estimated to be 0.40±0.02 eV using a theoretical relationship for the carrier concentration dependence of the specific contact resistance.     

Deep-level dominated current-voltage characteristics of buriedimplanted oxide silicon-on-insulator

Current-voltage characteristics of Au contacts formed on buried implanted oxide silicon-on-insulator (SOI) structures are discussed, which indicate that the dominant transport mechanism is space-charge-limited current (SCLC) conduction in the presence of deep-level states. The deep-level parameters, determined using a simple analysis, appear to be sensitive to anneal conditions used and subsequent processing. Silicon implanted with 1.7×10¹⁸ cm^-2 oxygen ions at 150 keV following a 1200°C anneal for 3 h shows deep level 0.37 eV below the conduction band edge with a concentration of unoccupied traps of ~ 2×10¹⁵ cm^-3 . In contrast, arsenic ion implantation, in the 1200°C annealed material with a dose of 1.5×10¹² cm^-2 at 60 keV and activated by rapid thermal annealing (RTA), introduces a deep level 0.25 eV below the conduction band edge with an unoccupied trap concentration of ~6×10¹⁷ cm^-2     

Effects of wet oxidation/anneal on interface properties ofthermally oxidized SiO2/SiC MOS system and MOSFET's

Effects of wet atmosphere during oxidation and anneal on thermally oxidized p-type and n-type MOS interface properties were systematically investigated for both 4H- and 6H-SiC. Deep interface states and fixed oxide charges were mainly discussed. The wet atmosphere was effective to reduce a negative flatband shift caused by deep donor-type interface states in p-type SiC MOS capacitors. Negative fixed charges, however, appeared near the interface during wet reoxidation anneal. In n-type SIC MOS capacitors, the flatband shift indicated a positive value when using wet atmosphere. The relation between interface properties and characteristics of n-channel planar 6H-SiC metal-oxide-semiconductor field effect transistors (MOSFETs) was also investigated. There was little relation between the interface properties of p-type MOS capacitors and the channel mobility of MOSFETs. The threshold voltage of MOSFETs processed by wet reoxidation anneal was higher than that of without reoxidation anneal. A clear relation between the threshold voltage and the channel mobility was observed in MOSFETs fabricated on the same substrate     

Improved performance and reliability of N2O-grownoxynitride on 6H-SiC

This letter reports, for the first time, N₂O-grown oxides on both n-type and p-type 6H-SiC wafers. It is demonstrated that the N₂O-grown technique leads to not only greatly improved SiC/SiO₂ interface and oxide qualities, but also considerably enhanced device reliabilities as compared to N₂O-nitrided and conventional thermally oxidized devices. These improvements are especially obvious for p-type SiC MOS devices, indicating that N₂ O oxidation could be a promising technique for fabricating enhancement-type n-channel SiC MOSFETs     

Long-term bias temperature reliability of P+ polysilicongated FET devices

An instability was found to be associated with +BT stress for P ⁺ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N⁺ poly-gated devices (NNMOS and NPMOS). The instability with the P⁺ poly-gated devices, which is a decrease in threshold voltage (V_t) and an increase in interface state density (D_it), was significantly reduced following N₂ annealing at 400°C. It is shown that adequate reliability for P⁺ poly-gated devices can be achieved for VLSI technologies     

The TEOS oxide deposited on phosphorus in-situ/POCl3doped polysilicon with rapid thermal annealing in N2O

This work presents a TEOS oxide deposited on the phosphorus-in-situ doped polysilicon with rapid thermal N₂O annealing. The oxide exhibits good electron trapping characteristics with a charge-to-breakdown (Q_bd) up to 110 C/cm². It is due to the good polysilicon/oxide interface morphology obtained by replacing POCl₃ doping with in-situ doping and the rapid thermal annealing in N₂O. In addition, the N₂O annealing densifies the deposited oxide and incorporates nitrogen into the oxide and at the polysilicon/oxide interface, thus improving the electrical characteristics     

4H-SiC MOSFETs utilizing the H2 surface cleaningtechnique

The H₂ cleaning technique was examined as the precleaning of the gate oxidation for 4H-SiC MOSFETs. The device had a channel width and length of 150 and 100 μm, fabricated on the p-type epitaxial layer of 3×10¹⁶ cm^-3. The gate oxidation was performed after the conventional RCA cleaning, and H₂ annealing at 1000°C. The obtained channel mobility depends on the pre-cleaning process strongly, and was achieved 20 cm²/N s in the H₂ annealed sample. The effective interface-state density was also measured by the MOS capacitors fabricated on the same chips, resulting 1.8×10¹² cm^-2 from the photo-induced C-V method     

Effect of electron cyclotron resonance H+,Ne+, Ar+, and Xe+ plasma precleaning ontitanium silicide formation

A vacuum integrated cluster tool process incorporating electron cyclotron resonance plasma cleaning, Ti sputter deposition, and rapid thermal annealing in N₂ is used to form a TiN_x<1/TiSi_y bilayer on (100) Si where the film composition is controlled by the preclean chemistry. Chemical cleaning with nominal 10 eV H⁺ completely removes native Si oxide resulting in a hydrogen terminated surface that promotes silicidation compared to one cleaned with buffered-oxide-etching (BOE). If the native oxide is only partially reduced, viz., SiO_x<2 surface, for example by shortening the H⁺ exposure time, then silicidation is largely inhibited and a thicker nitride layer is formed. Sputter cleaning with 50 to 250 eV Ar⁺ results in a bilayer that is roughly equivalent to that formed with BOE, whereas 50 to 150 eV Xe⁺ bombardment favors nitridation. Precleaning with >150 eV Ne⁺ promotes silicidation, thereby minimizing nitride thickness. The effects of precleaning are significant as the activation energy for TiSi_y formation is reduced from 1.8 eV characteristic of a BOE cleaned surface to 1.2 eV on Si etched with 250 eV Ne⁺. Mechanistically, the silicide kinetics are shown to be inhibited by the presence of a thin amorphous layer that is formed only when cleaning Si with Ar⁺ and Xe⁺ with the effect that both knock-on oxygen atoms and implanted noble gas atoms trapped within the amorphous layer retard the requisite solid-phase epitaxial regrowth kinetics. Recrystallizing the amorphous Si surface prior to metallization appears to restore the near-normal silicide kinetics that is characteristic of Ne⁺ cleaning     

Nanometer-scale investigation of metal-SiC interfaces using ballistic electron emission microscopy

We report ballistic-electron emission microscopy (BEEM) investigation of Pd, Pt Schottky contacts on 6H-, 4H-SiC, and Pd/15R-SiC. Measured Schottky barrier heights of 6H- and 4H-SiC samples appear spatially uniform up to the fitting error due to noise (0.03–0.04 eV and 0.1–0.2 eV for 6H- and 4H-SiC, respectively). In 4H-SiC, we observed an additional conduction band minimum (CBM) ∼0.14 eV above the lowest CBM, which provide direct experimental verification of band theoretical calculation results. Additionally, we sometimes observed enhancement in ballistic transmittance over regions intentionally stressed by hot electron injection using BEEM. We also report recent results on Pd/15R-SiC sample indicating a higher CBM ∼0.5 eV above the lowest CBM. In Pd/15R-SiC, interesting large variations in BEEM spectra at different locations were observed, possibly suggesting an inhomogeneous metal/semiconductor interface.     

High performance poly-crystalline silicon thin film transistorsfabricated using remote plasma chemical vapor deposition of SiO2

A remote plasma chemical vapor deposition (RPCVD) of SiO₂ was investigated for forming an interface of SiO₂/Si at a low temperature below 300°C. A good SiO₂/Si interface was formed on Si substrates through decomposition and reaction of SiH₄ gas with oxygen radical by confining plasma using mesh plates. The density of interface traps (D_it) was as low as 3.4×10¹⁰ cm^-2eV^-1. N- and p-channel Al-gate poly-Si TFTs were fabricated at 270°C with SiO₂ films as a gate oxide formed by RPCVD and laser crystallized poly-crystalline films formed by a pulsed XeCl excimer laser. They showed good characteristics of a low threshold voltage of 1.5 V (n-channel) and -1.5 V (p-channel), and a high carrier mobility of 400 cm²/Vs     

Tunneling in MIS structures—II Experimental results on M---SiO2---Si

Experimental results for MOS tunnel structures are discussed and compared to the theory developed in the preceding paper. The low frequency (d.c.) conductance yields a well width wider than the band gap of silicon. For 10 ω-cm p-type silicon, with an oxide thickness of 46 Å, V_w=1.96 eV, in good agreement with the theory, including the effects of interface states. Similar results are obtained for n- and p-type non-degenerate silicon. Structure appears in the conductance well for higher frequency signals. The origin of these peaks is discussed. It is shown that one peak is due to a geometric effect while the second is due to interface states. The conductance due to interface states can be accounted for by the time lag in charge exchange between the majority carrier band in the semiconductor and the interface states; tunneling from the metal to these interface states is not observed. This work indicates a localized state at 0.27 eV above the valence band for 10 ω-cm p-type silicon. The concentration is 7.4 × 10¹¹ cm⁻² and the capture cross-section is 5.0 × 10⁻¹⁸ cm². Capacitance measurements indicate another localized state at 0.14 eV above the valence band which does not contribute to the conductance measurements because of its long time constant.