An image signal multiprocessor on a single chip

A digital image signal multiprocessor (ISMP), a multiprocessor version of a previous real-time image signal processor (RISP) for gray-level image processing, is discussed. It is composed of a main controller and four processor elements (PEs), which are programmable 12-b digital signal processors. One PE has the processing speed of 50-million microinstructions-per-second. The ISMP has 200-million microinstructions-per-second performance using parallel processing with a round-robin method for local image processing. In the other operation mode, each PE processes the same image data with different feature-extracting programs. In addition, system processing power can be easily increased through a novel multichip processing mode. It has 30000 transistors on a 14.4-mm×13.7-mm chip using 1.2-μm double-metal CMOS process technology. Its power dissipation is 2.9 W     

SOPC技术在实时红外图像处理中的应用

可编程片上系统（SOPC）是Altera公司提出的一种灵活、高效的片上系统解决方案,为构建实时、小型化的红外图像处理器提供了有效的解决途径。介绍了一种基于SOPC技术的红外图像处理器,可对数字红外图像进行实时处理和显示驱动。处理器主要包括非均匀校正模块、实时图像增强模块和显示驱动模块。处理功能主要由一片Altera公司的SOPC芯片EPXA4完成。实验结果表明,采用SOPC技术构建的红外图像处理器集成度高、功耗低、可靠性强、实时性好。     

弹载红外图象处理器中多CPU之间通信方法的研究

弹载红外图象处理器是一个复杂的实时红外图象处理系统。由于它的计算量很大，实时性很强，单ＣＰＵ已经不可能完成如此繁重的任务。本文分析了弹载红外图象处理器中多ＣＰＵ之间通信的几种方法。在分析几种通信方法的原理和各自的优缺点之后，提出了弹载红外图象处理器中多ＣＰＵ之间通信应采用双口ＲＡＭ作共享存储器的并行通信方法，我们所设计的系统中均采用这种方法。实验证明这种方法的数据信息通信具有很高的灵活性和可靠性，完全满足弹载红外图象处理器中多ＣＰＵ之间通信的要求。     

基于多DSP与FPGA的实时图像处理系统设计

为解决高速数字图像处理系统和实时性相冲突的要求,设计了以多DSP（数字信号处理器TMS320C6416）和现场可编程门阵列（FPGA）相结合的实时图像处理系统。重点介绍了该系统的硬件资源选择、基本组成、工作原理、电源设计、DSP引导方式以及软件设计等,通过对每秒25帧14位640×512像素的数字图像处理结果表明,该系...     

一种新的实时通用视频处理器的设计

实时通用视频处理器是图像处理系统的核心，协调实时通用视频处理器的Ａ／Ｄ，ＤＳＰ，Ｄ／Ａ三者的时序，使ＤＳＰ有更多的时间处理图像数据是设计的关键。在分析国内外文献中提出了逆程和正程工作方式下的视频处理器原理和结构后，又提出一种新的全程工作方式的视频处理器设计方案，并对三种工作方式的电路及工作原理进行了比较。     

基于3G通信的嵌入式图像传输系统

嵌入式处理器以其高处理性能、低功耗、低成本、易裁剪、体积小等优势,在各类电子设备中越来越普及.3G通信则以其高传输速率、覆盖范围广、通信质量好等优点,适合大数量实时传输.结合两者的优势,文中设计了一种基于3G的嵌入式图像传输系统.该系统使用TCP传输协议,采用C/S服务模式,图像数据通过服务器转发.实验结果表明,图像能够稳定传输,基本满足实时传输要求.     

基于FPGA和DSP的高速图像处理系统

为了提高图像处理系统的高性能和低功耗,提出了一种基于FPGA和DSP协同作业的高速图像处理嵌入式系统,其中DSP为主处理器,负责图像处理,而FPGA为协处理器,负责系统的所有数字逻辑。整个系统中FPGA和DSP的工作之间形成流水,同时借助于单片双口RAM(CY7C025AV-15AI)完成两者的通信,比使用单片DSP建立的处理系统性能提高25%左右。该系统具有可重构性,方便其他的算法于该系统上实现。     

天文光电观测系统实时信息处理机的设计与实现

针对地基天文光电观测系统获取图像数据量大、实时处理难度高等特点,设计并实现了以高可靠CPCI工控机为平台、基于FPGA+双DSP TMS320C6455的实时信息处理机。详细介绍了实时信息处理机硬件结构,深入分析了实时信息处理机的设计特点。针对实时信息处理机实时图像获取和实时图像处理的主要任务,重点描述了工程实现过程中图像获取及处理流程、弱小目标检测算法实现、DSP任务分割和速度优化等。外场实验及大量实测数据处理结果验证了该处理机的实时性和处理能力,满足了天文光电观测系统的要求,为高分辨率图像的处理运算提供了可靠的硬件平台。     

嵌入式车牌识别系统的硬件电路设计

基于数字信号处理器(DSP)TMS320VC5416和复杂可编程逻辑器件(CPLD)的嵌入式车牌识别系统的硬件设计,利用视频处理芯片SAA7111作为视频A/D,在CPLD的控制下将采集到的图像数据写入帧存储器中,DSP对图像数据进行实时分析处理。采用"乒乓"存储结构,实现了图像数据的采集和处理的并行运行。识别结果通过串口传到上位机或者保存在E2PROM中,实现了车牌识别系统脱机、联机工作,在实时高速图像处理系统中有广泛的工程技术应用前景。     

A 24-b 50-ns digital image signal processor

A 50-ns digital image signal processor (DISP)-an image/video application-specific VLSI chip-is discussed. This chip integrates 538 K transistors and dissipates 1.4 W at a 40-MHz clock. It is based on a 24-b fixed-point architecture with a five-stage pipeline. The DISP features a real-time processing capability realized by an enhanced parallel architecture, video-oriented data processing functions, and an instruction cycle time that is typically 35 ns, and 50 ns at worst. This 50-ns cycle time allows the DISP to execute mor than 60-million operations per second (MOPS). High-density 1.0-μm CMOS technology allows numerous on-chip features, including specified resources optimized for image processing. This allows a flexible hardware implementation of various algorithms for picture coding. Several circuit design techniques that are intended to attain a fast instruction cycle are reviewed, including distributed instruction decoding and a hierarchical clocking circuit. The LSI has been designed by the extensive use of a cell-based design method. The processor incorporates a sophisticated testing function compatible with a cell-based design environment     

A single-chip 16-bit 25-ns real-time video/image signal processor

A single-chip 16-b microprogrammable real-time video/image signal processor (VISP) has been developed for use in real-time motion picture encoding during low-bit-rate transmission for TV conference systems. In addition to stand-alone microprocessor functional units, the VISP integrates a high-speed variable seven-stage pipeline arithmetic circuit for video/image data processing and various controllers for easy I/O (input/output) and multiple-chip connections A 25-ns instruction cycle time is attained by using complementary reduced-swing CMOS logic circuits. The chip (14 mm×13.4 mm) was fabricated using a double-metal-layer 1.2-μm CMOS process technology and contains 220000 transistors     

基于DSP的自动调焦系统

由于数字图像处理理论的逐渐成熟和完善,现今的自动调焦系统已由原基于光学系统的自动调焦转换为基于各种数字图像处理方法的自动调焦.由此介绍一种基于DSP芯片TMS320C6416为核心处理器进行图像采集、预处理和实施控制的自动调焦系统.TMS320C6416芯片的总体性能可比C62xx提高一个数量级.重点说明了该实时数字图像处理系统的硬件组成、工作原理和软件算法.结果表明该系统具有高度的实时性和稳定性,能够快速准确的完成自动调焦.     

应用多级门限法去除气象回波图像噪声

文中介绍了应用功率、杂波校正因子（ＣＣＯＲ）和信号质量指数（ＳＱＩ）等多级门限联合处理的气象目标回波图像噪声去除算法。通过利用气象回波信号底层处理时的相关信息进行地杂波和白噪声的去除,突破了以往只能在高层采用图像处理的去除噪声的局限。由于充分利用了信号与地杂波和白噪声的不同特征信息,仅增加少量运算就去除了噪声干扰,同时很好地保留了小信号。经过在自行研制的基于Ｃ３Ｘ的并行ＤＳＰ阵列处理机上现场运行并     

基于ADSP-BF533的音频处理系统设计

进行数字信号处理运算的微处理器用于实时快速地实现数字信号处理算法。针对ADSP-BF533的特点介绍了基于该芯片的音频处理系统电路设计,主要包括复位电路、电源单元、存储器单元及模数/数模转换单元等,可作为音频信号处理的通用系统。     

按频率抽取的基4FFT算法在FPGA中实现

雷达成像的数据处理运算量非常巨大，要达到准实时甚至全实时的成像处理速度，就需要高性能的处理设备。结合自己的工程实践，介绍了按频率抽取的基4 FFT算法在FPGA器件中的实现。基于高速FPGA的SAR实时信号处理机是该系统的核心部分，这方面的研究国内才刚刚起步，该文的工作对SAR雷达系统的硬件实现具有重要意义，为SAR实时成像处理提供了一条有效途径，具有良好的应用前景，此技术的实现在实时信号处理领域也具有重要意义。     

基于DSP+FPGA的实时视频信号处理系统设计

实时视频信号处理的实时性和跟踪算法的复杂性是一对矛盾,为此采用DSP+FPGA的架构设计,同时满足实时性和复杂性的要求,提高了系统的整体性能。DSP作为主处理器,利用其高速的运算能力,快速有效地处理复杂的跟踪算法;FPGA作为协处理器,完成视频图像的接收、存储、预处理,使设计具有更大的灵活性。系统采用了形心跟踪和相关跟踪两种算法。实验证明,该系统可以稳定地实时跟踪运动目标。     

Design of a real-time digital Simulator for a D-STATCOM system

Real-time digital simulation of power electronic systems requires significant computational resources due to increasingly complex system configurations, control algorithms, and higher switching frequency. Consequently, it is prudent to exploit various computer resources for optimizing the design of simulators/controllers for such systems. This paper presents the design and implementation details of a real-time digital simulator for a Voltage-Source-Converter-based Distribution STATic COMpensator (D-STATCOM) power system. The design process adopts a modular approach utilizing distributed digital signal processor/field-programmable gate array resources of a digital processing platform. The design has been validated by using an experimental setup of a 5-kVA D-STATCOM system.     

An On-Sensor Bit-Serial Column-Parallel Processing Architecture for High-Speed Discrete Fourier Transform

This brief presents a discrete Fourier transform (DFT) processor based on a bit-serial column-parallel processing architecture suitable for integrating it on CMOS image sensors. Using a column-parallel A/D converter (ADC) array, column-line sensor outputs of the two-dimensional image array are digitized. The ADC outputs are sliced to one bit and are given to the bit-serial column-parallel DFT processor from the MSB to the LSB. A high-speed and cost-effective implementation can be expected. In the case of 256$,times,$256-point DFT for 8-b image data, the processing time is estimated to be 2 ms at a clock frequency of 100 MHz, which corresponds to the 500-frames/s real-time processing.     

A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine

A network-on-chip (NoC) based parallel processor is presented for bio-inspired real-time object recognition with visual attention algorithm. It contains an ARM10-compatible 32-bit main processor, 8 single-instruction multiple-data (SIMD) clusters with 8 processing elements in each cluster, a cellular neural network based visual attention engine (VAE), a matching accelerator, and a DMA-like external interface. The VAE with 2-D shift register array finds salient objects on the entire image rapidly. Then, the parallel processor performs further detailed image processing within only the pre-selected attention regions. The low-latency NoC employs dual channel, adaptive switching and packet-based power management, providing 76.8 GB/s aggregated bandwidth. The 36 mm² chip contains 1.9 M gates and 226 kB SRAM in a 0.13 mum 8-metal CMOS technology. The fabricated chip achieves a peak performance of 125 GOPS and 22 frames/sec object recognition while dissipating 583 mW at 1.2 V.     

基于面阵CCD的激光告警系统的图像采集与处理

光栅衍射型激光告警系统是一种基于光栅衍射效应、可实时探测来袭激光参量信息的光电对抗设备。为了获取入射激光的波长和入射角度,以光栅衍射效应为基本原理,采用面阵CCD进行图像采集、数字信号处理器进行图像处理,并依据信号特点开发了目标识别算法。通过理论分析和实验验证,设计出了一套基于面阵CCD的光栅衍射型激光告警系统的图像采集与处理系统,实现了对激光目标的探测。结果表明,该系统可有效地识别来袭激光并准确标记,具有良好的稳定性、实时性。