A robust digital baseband predistorter constructed using memory polynomials

Power amplifiers (PAs) are inherently nonlinear devices and are used in virtually all communications systems. Digital baseband predistortion is a highly cost-effective way to linearize PAs, but most existing architectures assume that the PA has a memoryless nonlinearity. For wider bandwidth applications such as wideband code-division multiple access (WCDMA) or wideband orthogonal frequency-division multiplexing (W-OFDM), PA memory effects can no longer be ignored, and memoryless predistortion has limited effectiveness. In this paper, instead of focusing on a particular PA model and building a corresponding predistorter, we focus directly on the predistorter structure. In particular, we propose a memory polynomial model for the predistorter and implement it using an indirect learning architecture. Linearization performance is demonstrated on a three-carrier WCDMA signal.     

Amplifier linearization using RF feedback and feedforwardtechniques

The performance of feedback as a distortion reduction technique is highly dependent on the integrity of the feedback path. Any error or noise generated in this path is directly reflected into the output of the amplifier. Linearized RF power amplifiers (PAs) using Cartesian feedback require a demodulator in the feedback loop, and this is a potential source of linear errors, nonlinear errors, and noise. RF feedback with Cartesian compensation is proposed as a technique for overcoming some of these problems. The scheme is most suited to systems requiring an RF input. In addition, the RF nature of the input, feedback, and error signals enables the addition of a feedforward loop to further improve the linearization capability while still maintaining good efficiency. Design equations and simulation results are given for such a system. Disadvantages include the limited bandwidth (estimated at 1 MHz) and the need for additional circuits to generate the RF input signal when included in an integrated transmitter     

Amplifier linearization using simultaneous harmonic and basebandinjection

A novel linearization scheme utilizing injection of distortion signal at the input of amplifier is described. Harmonic and baseband signal generated by predistortion circuits is fed to the input of the main amplifier and by controlling the power level of the harmonic and baseband signal properly, mixing products can be made to cancel out with the FET inherent distortion signals. Unlike many other techniques, no precise phase adjustment is required for the RF signal path. For verification, the two-tone performance of a constructed linearized amplifier is measured and a reduction of the third-order IMD power level of about 27 dB is observed     

Adaptive neuro-fuzzy inference system (ANFIS) digital predistorter for RF power amplifier linearization

This paper describes an adaptive digital predistorter (ADP) for RF power amplifier (PA) linearization using an adaptive neuro-fuzzy inference system (ANFIS). The ANFIS predistorter (PD) employs the advantage of real-time modeling of the PA's responses in determining the PD's functions. The amplitude and phase corrections for the PD are represented in an easy-to-understand fuzzy if-then rule, while the parameters involved in the fuzzy representation are trained using neural networks algorithms, namely gradient-descent and least squares estimate (LSE). Experimental results show that a 26.3-dB improvement in linearity for a two-tone signal is obtained, while a distorted WCDMA signal is suppressed by at least 12 dB. The adaptability of the ANFIS PD to instantaneous variation in PA responses through time is also demonstrated, and results show that the ANFIS PD is capable of adapting to simulated environmental changes, which is a topic often omitted by researchers in this area. Further testing demonstrated that the tuning parameters involved in the training could be reduced by more than half for a fairly nonlinear PA without significantly degrading the suppression capability.     

Amplifier linearization using compact microstrip resonant cell-theory and experiment

This paper presents a novel technique for reducing the intermodulation distortions (IMDs) in power amplifiers. In this method, both second- and third-harmonic components generated by the transistor are reflected back simultaneously by the compact microstrip resonant cell (CMRC) at the input port with proper phases to mix with the fundamental signal for the reduction of IMDs. A rigorous mathematical analysis on the effectiveness of multiharmonic reflections has been formulated and derived using the Volterra series. Moreover, the delay mismatch factor of the proposed method is analytically studied and the result shows that a better tolerance to the delay error can be achieved by using CMRC circuitry. Standard two-tone test measurements reveal 32- and 22-dB reductions for the third-order IMD and fifth-order IMD, respectively, without affecting the fundamental signal at 2.45 GHz. Meanwhile, the proposed approach gives a peak power added efficiency of 53% with 11.5 dB transducer gain and 15 dBm output power for a single-stage SiGe bipolar junction transistor. The adjacent channel power ratio (ACPR) is -55dBc for a data rate of 384-kb/s quadrature phase shift keyed modulated signal with 2-MHz spanning bandwidth, and this ACPR is maintained for a broad range of output power level.     

An accurate digital baseband predistorter design for linearization of RF power amplifiers by a genetic algorithm based Hammerstein structure

In this paper, a novel digital predistorter design based on the Hammerstein structure is proposed in order to linearize radio frequency power amplifiers. A genetic algorithm optimization method has been proposed to accurately identify the coefficients of a Wiener model for the power amplifier. Digital predistorter design based on the proposed Hammerstein model has been carried out according to the accurate Wiener model. The validation of the suggested model is carried out using the simulation of the power amplifier and the digital predistortion excited by 64QAM signals in the advanced design system software. According to the simulation results, the criterion of an adjacent channel power ratio decreased by about 16 dB. The simulation results show the adjacent channel power ratio of almost ??46 dBc. In order to assess the feasibility of the proposed predistorter, it is completely implemented in the Kintex FPGA using Vivado HLS. This proposed model enables a more accurate modeling of nonlinear distortion and memory effects compared to the previous linearization methods. This paper presents the new linearization method using the genetic algorithm based Hammerstein structure.     

A novel digital predistorter technique using an adaptive neuro-fuzzy inference system

This letter presents a novel digital predistorter technique using an adaptive neuro-fuzzy inference system (ANFIS). The proposed approach employs real-time input and output signals of a nonlinear power amplifier as inputs to the ANFIS, so as to approximate the inverse functions of the power amplifier. The antecedent and consequent parameters of the FIS constructed by the ANFIS are tuned using backpropagation and least squares algorithms. Simulation shows that this novel technique has improved the linearity of a WCDMA signal by a further 4 dBc compared to a conventional look-up table (secant) approach. Moreover, this proposed technique is capable of adapting to instantaneous variation in the power amplifier response through time, which is a topic often omitted by researchers in this area.     

Modeling of HPA and HPA linearization through a predistorter: Global Broadcasting Service applications

This paper presents a technique to linearize the high power amplifier (HPA) through a predistorter (PD). The characteristics of the PD circuit are derived based on the extension of Saleh's model for HPA and a simple linear-log model. Numerical results are shown for Global Broadcasting Service (GBS) applications.     

Piecewise-polynomial and cascade models of predistorter for linearization of power amplifier

To combat non-linear signal distortions in a power amplifier we suggest using predistorter with cascade structure in which first and second nodes have piecewise-polynomial and polynomial models. On example of linearizing the Winner-Hammerstein amplifier model we demonstrate that cascade structure of predistorter improves precision of amplifier??s linearization. To simplify predistorter??s synthesis the degree of polynomial model used in first node should be moderate, while precision should be improved by higher degree of second node??s polynomial.     

New predistorter using triangular memory polynomial for power amplifier of OFDM-based wireless broadband communication system

A triangular memory polynomial (TMP) predistorter is presented in this paper to linearize a power amplifier's nonlinear with memory effects.Compared with the traditional memory polynomial (MP) predisto...     

基于分离法和分段线性模型的高速预失真技术

本文提出一种基于分离法和分段线性模型的有记忆HPA(High Power Amplifier)预失真技术,并给出基于查找表的FPGA高速实现方案.该预失真方案首先应用进化算法自适应辨识出有记忆HPA的(LTI+分段线性函数)模型,然后根据分离法原理,求出预失真器模型的参数.本文的分离法和文献[12]的方法相比,运算量较小,而且精度更高,易于高速FPGA实现,适合于高速卫星发射机.matlab仿真结果证明该方法的性能很好.     

Genetic algorithm optimization of a hybrid analog/digital predistorter for RF power amplifiers

This study presents a genetic algorithm optimization of a hybrid analog/digital predistorter, in order to reduce the intermodulation distortion (IMD) caused by the nonlinear properties of the radio frequency (RF) power amplifier (PA). Designed predistorter based on polynomial work function and the coefficient of the polynomial is optimized in order to reduce IMD by spectrum monitoring. The design procedure and validation of predistorter have been carried out by Agilent-ADS2005A. In order to validate the predistorter two different modulation schemes as CDMA and 16-QAM have been used. Also in order to verifying the linearization a test power amplifier circuit has been examined including Motorola MOSFET MRF9742 showing the nonlinear characteristics with memory. Simulations have been shown that adjacent channel power ratio (ACPR) improvements were acceptable for both CDMA and 16-QAM modulation schemes.     

An address generation scheme to minimize the control memory requirements in microprogrammed digital computers

Minimization of the control memory bit dimension as well as the word dimension and simplification of the address generation network constitute major problems in the synthesis of microprogrammed digital systems. The purpose of the present paper is to dovolop a now more efficient methodology for implementing the next address generation circuit of control memory words in n. microprogrammed system. The proposed algorithm has two advantages : it minimizes the complexity of the address calculating network and at the same time minimizes tlio control memory size in both bit and word dimensions. The methodology has been proved to be superior to existing methods.     

Analogue elliptical filters with digital control and memory

To control active filter characteristics a new type of integrated circuit (IC) of Xicor Inc. is used. This is an analogue potentiometer with digital control and non volatile memory. Usage of this IC is convenient when the storage of the last results is required. The control parameters are estimated for applications on elliptical low-pass and high-pass voltage-controlled voltage source filters. Practically obtained diagrams are given.     

Two-block model of a digital corrector for linearization of an analog radio channel

A two-block model of an analog radio channel of a digital communication system is proposed. Problems of identification of the model of the data transmission channel and synthesis of a digital precorrector for adaptive linearization of nonlinear dynamic distortions are solved using the stochastic gradient method. The results of comparative analysis of two-block and one-block structures are presented.     

Direct digital frequency synthesiser with high memory compressionratio

A 16 bit, 100 MHz, low-power direct digital frequency synthesiser is presented. A simple trigonometric approximation is applied to ROM compression to achieve a compact architecture. The compression ratio for the look-up table is 455:1 and the spurious-free dynamic range 96 dBc     

A dual SQUID linearization concept using a phase modulation scheme

A critical control system evaluation is presented of basic flux-locked loop systems. The development of a new superconducting quantum interference device (SQUID) linearization method is then described, where no magnetic flux feedback is necessary to cancel the applied flux. It is shown that a dual SQUID configuration will be able to produce a true phase modulation system that is easily demodulated with a phase-locked loop. The theoretical performance of the proposed configuration is verified by simulations, and the performance and limitations are discussed in detail. It is shown that small dc correction voltages at the output of the SQUID's significantly decrease output noise, as is the case with an increase in SQUID dc bias currents. An optional feedback system is also described for optimal performance of the dual SQUID configuration     

带基波放大器的前馈功率放大器设计

在前馈双环功率放大器系统中,"Loop2"对误差信号放大器增益的要求很高,且误差信号放大器对系统的输出增益没有贡献.针对上述问题,提出了一种改进方法,在"Loop1"中加入一个基波放大器,以提高"Loop1"中信号的对消电平和精度,降低"Loop2"中误差信号放大器的增益要求,使误差信号放大器也放大部分基波信号,从而达到提高系统输出功率,改善3阶交调失真的目的.     

Design and application of a GaAs digital RF memory chip

The design and performance of a GaAs integrated memory/logic chip designed for digital RF memory (DRFM) applications is described. This chip, called a programmable delay-line element (PDLE), implements the basic DRFM storage and delay functions. The RAM-with-logic configuration combines a 4-kb static RAM with 750 logic gates, providing on a single chip the components for storage, address generation, demultiplexing, multiplexing, and control functions normally provided by a variety of separate chips. A distributed control organization, where the chip is configured to provide as outputs all the signals required as inputs to another identical chip, is used. Chips cascaded into strings implement the programmable delay lines required for DRFM systems. Problems associated with complex signal distribution networks are avoided since, within a string, signal distribution requires only local interconnections between adjacent chips. Correct operation of all functions was demonstrated in a four-chip string which provides a total memory capacity of 16 kb. The maximum sampling rate was 800 MHz, and power dissipation was approximately 2 W per chip     

On digital filter structures with low coefficient sensitivities

A simple network transformation method is proposed to generate equivalent digital filter structures whose multiplier coefficients are functions of the parameters of the transformation. An application of this proposed approach, illustrated here, is in generating structures with low coefficient sensitivities.