65 nm体硅工艺NMOS中单粒子多瞬态效应的研究

针对NMOS场效应晶体管由重离子辐射诱导发生的单粒子多瞬态现象,参考65 nm体硅CMOS的单粒子瞬态效应的试验数据,采用TCAD仿真手段,搭建了65 nm体硅NMOS晶体管的TCAD模型,并进一步对无加固结构、保护环结构、保护漏结构以及保护环加保护漏结构的抗单粒子瞬态效应的机理和能力进行仿真分析。结果表明,NMOS器件的源结和保护环结构的抗单粒子多瞬态效应的效果更加明显。     

双阱CMOS器件单粒子瞬态效应机理研究

介绍了一种65 nm 双阱CMOS工艺设计的六管SRAM单元的抗辐射性能。通过三维有限元数值模拟的方法,分析了SRAM单元的单粒子瞬态效应在NMOS管中的电荷收集过程和瞬态脉冲电流的组成部分,并提出一种高拟合度的临界电荷计算方案。双阱器件共享电荷诱发的寄生双极放大效应对相邻PMOS管的稳定性有着显著的影响,高线性能量传输提高了器件单粒子翻转的敏感性。电学特性表明,全三维器件数值仿真的方法能够有效评估因内建电势突变产生的瞬态脉冲电流。该方法满足器件仿真对精确度的要求。     

保护环对130nm体硅PMOS抗单粒子瞬态特性的影响

基于TCAD（TechnologyComputerAidedDesign）仿真软件,通过对带有不同宽度保护环的130nto体硅PMOS器件进行单粒子辐照仿真,研究了保护环结构对深亚微米器件因单粒子辐照所产生的寄生双极效应．仿真结果表明,保护环结构能够大幅缩短器件SET（SingleEventTransient）电流的脉冲宽度,有效抑制寄生双极电荷收集,这种抑制作用随着保护环宽度增加而增强,最终趋于稳定．通过对加固器件的面积和抗辐射性能的折衷考虑,改进了保护环结构,并以宽度为0．38μm的保护环为例,证明了改进后的结构能够在保证器件抗单粒子性能及电学特性,同时节省29．4％的面积．     

纳米器件单粒子瞬态仿真研究

利用计算机辅助设计软件,研究了不同条件下28 nm体硅器件的单粒子瞬态（SET）效应,分析了不同器件间距、线性能量转移值和粒子入射角度对器件SET效应的影响。随着器件漏极间距的减小,SET脉冲幅度和脉冲宽度随之减小。与垂直入射的情况相比,倾角入射下SET脉冲幅度和宽度的减小程度更加明显,电荷共享效应更加显著。仿真结果表明,合理调节反相器相异节点的器件间距,利用器件间的电荷共享可以有效减弱重离子产生的SET脉冲,减少单粒子效应的反应截面。     

应变Si NMOS器件总剂量辐射对单粒子效应的影响

针对应变Si NMOS器件总剂量辐射对单粒子效应的影响机制,采用计算机TCAD仿真进行研究。通过对比实验结果,构建50 nm应变Si NMOS器件的TCAD仿真模型,并使用该模型研究处于截至态(V_ds=1 V)的NMOS器件在总剂量条件下的单粒子效应。实验结果表明,总剂量辐照引入的氧化层陷阱正电荷使得体区电势升高,加剧了NMOS器件的单粒子效应。在2 kGy总剂量辐照下,漏极瞬态电流增加4.88%,而漏极收集电荷增量高达29.15%,表明总剂量辐射对单粒子效应的影响主要体现在漏极收集电荷的大幅增加方面。     

负偏置温度不稳定性导致单粒子瞬态脉冲的压缩与展宽

摘要：本文基于3D TCAD 器件模拟,研究了130nm体硅工艺下,负偏置温度不稳定性（NBTI）对单粒子瞬态（SET）脉冲的影响。研究结果表明：当粒子轰击高输入反相器的PMOS管时,NBTI能够导致所产生的SET脉冲的宽度和幅度随时间不断压缩,当粒子轰击低输入反相器的NMOS管时,NBTI能够导致所产生的SET脉冲的宽度和幅度随时间不断展宽。基于研究结果,本文首次提出：NBTI对粒子轰击NMOS管所产生的SET脉冲的影响已经十分严重,在进行抗辐照加固设计时必须考虑NBTI所造成的影响。     

部分耗尽SOI工艺器件辐射效应的研究

对0.13μm部分耗尽SOI工艺的抗辐射特性进行了研究.首先通过三维仿真研究了单粒子事件中的器件敏感区域,随后通过实验分析了器件的总剂量效应.三维仿真研究了离子入射位置不同时SOI NMOS器件的寄生双极效应和电荷收集现象,结果表明,离子入射在晶体管的体区和漏区时,均可以引起较大水平的电荷收集.对SRAM单元的单粒子翻转效应(SEU)进行了仿真,结果表明,体区和反偏的漏区都是翻转的敏感区域.通过辐照实验分析了器件的总剂量效应,在该工艺下对于隐埋氧化层,关断状态是比传输门状态更劣的辐射偏置条件.     

基于三维模型的InGaP/GaAs HBT单粒子效应仿真

为全面评估航天型号用元器件的抗辐射性能,对InGaP/GaAs异质结双极晶体管(Heterojunction Bipolar Transistor,HBT)的单粒子效应进行了仿真研究。首先,介绍了空间辐射环境中重离子诱发器件产生单粒子瞬态脉冲的机理。然后,建立了InGaP/GaAs HBT器件三维仿真模型,并利用蒙特卡罗方法模拟了不同能量的C、F、Cl、Br、I等重离子在器件中的射程和LET值。最后,基于ISE-TCAD仿真软件对器件的单粒子瞬态脉冲电流曲线进行了仿真和分析。结果表明:重离子在器件中产生的集电极瞬态脉冲电流可达几百微安,集电极瞬态脉冲电流与重离子的能量成反比,与离子的原子序数成正比。由此可知,InGaP/GaAs HBT器件对单粒子效应比较敏感,且对不同重离子的敏感程度不同。这可以为航天型号用元器件的设计选型和可靠性评估提供技术支撑。     

粒子入射条件对28nm SRAM单元单粒子电荷共享效应影响的TCAD仿真研究

利用器件仿真工具TCAD,建立28 nm体硅工艺器件的三维模型,研究了粒子入射条件和器件间距等因素对28 nm体硅工艺器件单粒子效应电荷共享的影响规律。结果表明,粒子LET值增大、入射角度的增大、器件间距的减小和浅槽隔离(STI)深度的减少都会增加相邻器件的电荷收集,增强电荷共享效应,影响器件敏感节点产生的瞬态电流大小;SRAM单元内不同敏感节点的翻转阈值不同,粒子LET值和入射角度的改变会对SRAM单元的单粒子翻转造成影响;LET值和粒子入射位置变化时,多个SRAM单元发生的单粒子多位翻转的位数和位置也会变化。     

N阱掺杂对PMOS管的SET效应影响研究

基于Synopsys公司的3D-TCAD器件仿真软件,在65 nm体硅CMOS工艺下研究了场效应晶体管(FET)抗辐射性能与工艺参数的关系,分析了N阱掺杂对单管PMOS单粒子瞬态脉冲(SET)效应的影响。针对PMOS管SET电流的各组分进行了分析,讨论了粒子轰击后器件各端口电流的变化情况。研究结果表明,增大N阱掺杂浓度能有效降低衬底空穴收集量,提升N阱电势,抑制寄生双极放大效应,减少SET脉冲宽度。该研究结果对从工艺角度提升PMOS器件的抗辐射性能有指导意义。     

SEU reduction effectiveness of common centroid layout in differential latch at 130-nm CMOS technology

In this paper, we apply the common centroid layout technique in a differential latch structure (i.e., Quatro) and evaluate its effectiveness in reducing single event upset vulnerability. SPICE simulations demonstrate that higher charge sharing efficiency between the differential pair of sensitive devices results in higher critical charge of the latch. Both regular and common centroid layouts show the same heavy ion upset Linear Energy Transfer (LET) threshold because this is determined by the worst case critical charge (i.e., there is no charge sharing). Additionally, the magnitude decrease in the cross section of common centroid layout than that of the regular layout is not significant in 130-nm CMOS bulk technology because cross section covers the highest charge sharing efficiency and the lowest charge sharing efficiency from statistical point of view.     

Total ionizing dose effects in shallow trench isolation oxides

The peaked evolution of leakage current with total ionizing dose observed in transistors in 130 nm generation technologies is studied with field oxide field effect transistors (FOXFETs) that use the shallow trench isolation as gate oxide. The overall radiation response of these structures is determined by the balance between positive charge trapped in the bulk of the oxide and negative charge in defect centers at its interface with the silicon substrate. That these are mostly interface traps and not border traps is demonstrated through dynamic transconductance and variable-frequency charge-pumping measurements. These interface traps, whose formation is only marginally sensitive to the bias polarity across the oxide, have been observed to anneal at temperatures as low as 80 °C. At moderate or low dose rate, the buildup of interface traps more than offsets the increase in field oxide leakage due to oxide-trap charge. Consequences of these observations for circuit reliability are discussed.     

一种新型锁相环电荷泵的分析与设计

在分析传统电荷泵的一些不理想因素的基础上,提出一种新型的电路结构,以解决电荷泵的电流失配、电荷共享、电荷注入现象。本设计电路结构简单,电流匹配好,输出电压稳定。基于65nm CMOS工艺仿真结果表明:电荷泵充放电电流大小基本相等,环路稳定后输出电压Vc最大起伏为20μV。     

多晶硅薄膜晶体管中的晶粒间界电荷分享效应

通过对晶粒间界两侧耗尽区建立准二维模型,研究晶粒间界电荷分享效应对多晶硅薄膜晶体管阈值电压的影响.研究表明,考虑了晶粒间界电荷分享效应的阈值电压将变小,其中晶粒尺寸对阈值电压的影响最大.在此基础上,建立了多晶硅薄膜晶体管的阈值电压解析模型.     

A novel single-event-hardened charge pump using cascode voltage switch logic gates

A single-event-hardened charge pump for phase-locked loops is proposed based on radiation-hardened-by-design technique (RHBD). By applying a novel digital control circuit between the charge pump and the low-pass filter, the vulnerability of the charge pump to single event transients (SET) is considerably reduced. Besides, this control circuit does not change the original structure of the charge pump as well as the loop parameters. Simulation results based on SMIC 130 nm bulk CMOS technology showed a significant reduction of the voltage perturbation in the input of the voltage-controlled oscillator. Moreover, by implementing the proposed structure to the system, SET tolerance in VCO and DIV is improved to some extent, and the output noise of the charge pump is smaller than the original structure. In fact, the period jitter of the phase-locked loop is reduced by 12.5%–22.5% with the changes in operating frequency. The newly added circuit has the fairly low sensibility to SETs if it is properly designed.     

Design and optimization of BCCD in CMOS technology

This paper optimizes the buried channel charge-coupled device (BCCD) structure fabricated by complementary metal oxide semiconductor (CMOS) technology. The optimized BCCD has advantages of low noise, high integration and high image quality. The charge transfer process shows that interface traps, weak fringing fields and potential well between adjacent gates all cause the decrease of charge transfer efficiency (CTE). CTE and well capacity are simulated with different operating voltages and gap sizes. CTE can achieve 99.999% and the well capacity reaches up to 25 000 electrons for the gap size of 130 nm and the maximum operating voltage of 3 V.     

锁相环中电荷泵的分析与设计

用SMIC0.18μmCMOS工艺设计了一种改进型电荷泵电路。该电路基本思想是使用电流参考支路和运放来实现充放电电流的高度匹配,改进则基于重复利用运放的考虑。传统结构为了消除电荷共享效应需要一个单位增益运放,而这一设计省去这个运放,简化了设计,同时也能够达到充放电电流的良好匹配。芯片测试结果显示,输出电压在0.4～1.4V的范围内,电荷泵充放电电流约为1.1mA,失配小于2%。     

薄有源层非晶硅薄膜晶体管特性的研究

本文研究了薄ａ－Ｓｉ：Ｈ有源层结构的ａ－Ｓｉ：Ｈ ＴＦＴ的特性，实验结果表明，当ａ－Ｓｉ：Ｈ层的厚度小于一个临界值时，ａ－Ｓｉ：Ｈ厚度的变化对ａ－Ｓｉ：Ｈ ＴＦＴ静态特性的影响明显增大，本文中详细分析了有源层背面空间电荷层对ａ－Ｓｉ：Ｈ ＴＦＴ特性的影响，从表面有效空间电荷层的概念出发，从理论上分析了有源层厚度与阈值电压的关系，计算的临界有源层厚度为１３０ｎｍ，这与实验结果基本一致。     

Gain-coupled distributed-feedback GaInAs-GaAs laser structuresdefined by maskless patterning with focused ion beams

First-order periodic gain modulation in GaInAs-GaAs laser structures has been realized by maskless focused ion-beam implantation. The structures were implanted with Ga⁺-ions at an ion energy of 130 keV and a line dose of 1*10⁷ 1/cm. The periodicity of the gratings was designed for laser operation at 77 K and room temperature. With optical pumping we have observed single-mode laser operation due to the distributed feedback effect at wavelengths between 849 mn and 944 mn at 77 K (grating periods between 124 and 140 nm) and between 954 nm and 1005 mn at room temperature (grating periods between 140 and 148 nm)