可配置高精度FFT/IFFT的设计

提出了一种可配置高精度FFT/IFFT处理器的设计.设计中采用单蝶形混合基串行结构,降低了系统的复杂性,节省了一定的资源.提出了一种新颢的块浮点算法,有效避免了溢出问题并且提高了精度.运算点数可以通过对产生地址计数器的位选择配置为64、128、256、512、1024,实部、虚部均为16bit数据,不仅可以实现FFT运算,还可以实现IFFT运算.在SMIC0.13μm CMOS工艺下综合的面积为1.55mm<'2>,最高频率为210MHz.测试结果显示了本设计的高精度特性.     

快速傅里叶变换在OFDM系统中的应用

本文简要分析了未来OFDM数字通信系统的基本模型和可能采用的信号调制与解调的方法,在此基础上详细地解析了数据序列经过快速傅里叶逆变换 /快速傅里叶变换 (IFFT/FFT)后的输出结果与M进制数字调制解调之间的联系,并给出了能够实现OFDM调制解调的合适的IFFT/FFT算法,实际仿真结果表明快速傅里叶变换及反变换在未来OFDM技术中具有一定的实用价值。     

基于FPGA的FFT/IFFT处理器的实现

提出一种利用并行算法来实现FFT（快速傅里叶变换）及其逆变换IFFT（快速傅里叶逆变换）的设计方法。该处理器可由用户动态配置成64、256、1024点复数FFT或其逆变换IFFT。     

基于FPGA的OFDM调制解调系统设计与实现

正交频分复用(OFDM)是第四代移动通信的核心技术,该技术在高速数据传输中得到了广泛的应用。文章给出了正交频分复用系统的基本模型和该系统所采用的调制与解调方法;根据OFMD的特点,本设计提出了一种基于IFFT/FFT的OFDM调制解调器的低成本FPGA的实现方法。在ISE环境下完成对OFDM无线通信系统中快速傅里叶变换算法的仿真,仿真结果表明快速傅里叶变换在OFDM技术中具有一定的使用价值。实践证明,该方法具有设计简单、快速、高效和实时性等特点。     

一种应用于多带正交频分复用超宽带的IFFT/FFT处理器

针对多带正交频分复用超宽带(MB-OFDM UWB)系统,提出了一种高吞吐量、混合字长、混合基、4并行数据路径的128点IFFT/FFT处理器结构.该处理器采用具有误差补偿的改进Booth定长乘法器和CSD常量乘法器,有效地提高了精度和减少了硬件的复杂度.通过分析,本方案比混合基多路径延迟反馈(MRMDF)结构减少了49%的乘法器资源,在硬件开销相当的情况下,比双并行数据路径结构减少了30%的存储器资源和提高了33%的吞吐量,使该处理器在精度、硬件开销和速度上做了最好的折衷.在0.18μm COMS工艺下,该处理器的最大工作频率达到300 MHz,吞吐量为1.2 Gsamples/s,满足了吉比特无线个人域网络(WPAN)的要求.     

流水线结构FFT/IFFT处理器的设计与实现

针对实时高速信号处理的要求，设计并实现了一种高效的FFT处理器。在分析了FFT算法的复杂度和硬件实现结构的基础上，处理器采用了按频率抽取的基—4算法，分级流水线以及定点运算结构。可以根据要求设置成4P点的FFT或IFFT。处理器可以对多个输入序列进行连续的FFT运算，消除了数据的输入输出对延时的影响。平均每完成一次N点FFT运算仅需要Ⅳ个时钟周期。整个设计基于Verilog HDL语言进行模块化设计。并在Altera公司的Cyclone Ⅱ器件上实现。     

基于802.11a的FFT/IFFT处理器设计

设计了一种应用于802.11a的64点FFT/IFFT处理器.采用单蝶形4路并行结构,提出了4路并行无冲突地址产生方法,有效地提高了吞吐率,完成64点FFT/IFFT运算只需63个时钟周期.提出的RAM双乒乓结构实现了对输入和输出均为连续数据流的缓存处理.不仅能实现64点FFT和IFFT,而且位宽可以根据系统任意配置.为了提高数据运算的精度,设计采用了块浮点算法,实现了精度与资源的折中.16位位宽时,在HJTC 0.18μmCMOS工艺下综合,内核面积为:0.626 7 mm2,芯片面积为:1.35 mm×1.27 mm,最高工作频率可达300 MHz,功耗为126.17 mW.     

WIMAX系统中可配置FFT/IFFT的设计与实现

针对WIMAX系统中变长子载波的特点,通过采用流水线乒乓结构,以基2、基4混合基实现了高速可配置的FFT/IFFT。将不同点数的FFT旋转因子统一存储,同时对RAM单元进行优化,节约了存储空间;此外对基4蝶形单元进行优化,减少了加法和乘法运算单元。仿真和综合结果表明,设计满足了WIMAX高速系统中不同带宽下FFT/IFFT的要求。     

用于MB-OFDM UWB系统的FFT/IFFT处理器的设计与实现

设计了一种应用于超宽带(UWB)无线通信系统中的FFT/IFFT处理器。该处理器采用基24算法进行FFT运算,利用8路并入并出的流水线结构实现该算法,提高了处理器的数据吞吐率,降低了芯片功耗。提出了一种新颖的数据处理方式,在保证信噪比的情况下节约了逻辑资源。在乘法器的设计环节,针对UWB系统的具体特点,在结构上对乘法器进行了改进和优化,提高了乘法器的性能。最后,设计的FFT/IFFT处理器采用TSMC 0.18μm CMOS标准工艺库综合,芯片的内核面积为0.762mm2(不含测试电路)。在1.8V,25℃条件下,最大工作时钟317.199MHz,在UWB典型的工作频率下,内核功耗为33.5304mW。     

A 1-GS/s FFT/IFFT processor for UWB applications

In this paper, we present a novel 128-point FFT/IFFT processor for ultrawideband (UWB) systems. The proposed pipelined FFT architecture, called mixed-radix multipath delay feedback (MRMDF), can provide a higher throughput rate by using the multidata-path scheme. Furthermore, the hardware costs of memory and complex multipliers in MRMDF are only 38.9% and 44.8% of those in the known FFT processor by means of the delay feedback and the data scheduling approaches. The high-radix FFT algorithm is also realized in our processor to reduce the number of complex multiplications. A test chip for the UWB system has been designed and fabricated using 0.18-/spl mu/m single-poly and six-metal CMOS process with a core area of 1.76/spl times/1.76 mm/sup 2/, including an FFT/IFFT processor and a test module. The throughput rate of this fabricated FFT processor is up to 1 Gsample/s while it consumes 175 mW. Power dissipation is 77.6 mW when its throughput rate meets UWB standard in which the FFT throughput rate is 409.6 Msample/s.     

Cost-Effective Triple-Mode Reconfigurable Pipeline FFT/IFFT/2-D DCT Processor

This investigation proposes a novel radix-4² algorithm with the low computational complexity of a radix-16 algorithm but the lower hardware requirement of a radix-4 algorithm. The proposed pipeline radix-4² single delay feedback path (R4²SDF) architecture adopts a multiplierless radix-4 butterfly structure, based on the specific linear mapping of common factor algorithm (CFA), to support both 256-point fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) and 8times8 2D discrete cosine transform (DCT) modes following with the high efficient feedback shift registers architecture. The segment shift register (SSR) and overturn shift register (OSR) structure are adopted to minimize the register cost for the input re-ordering and post computation operations in the 8times8 2D DCT mode, respectively. Moreover, the retrenched constant multiplier and eight-folded complex multiplier structures are adopted to decrease the multiplier cost and the coefficient ROM size with the complex conjugate symmetry rule and subexpression elimination technology. To further decrease the chip cost, a finite wordlength analysis is provided to indicate that the proposed architecture only requires a 13-bit internal wordlength to achieve 40-dB signal-to-noise ratio (SNR) performance in 256-point FFT/IFFT modes and high digital video (DV) compression quality in 8 times 8 2D DCT mode. The comprehensive comparison results indicate that the proposed cost effective reconfigurable design has the smallest hardware requirement and largest hardware utilization among the tested architectures for the FFT/IFFT computation, and thus has the highest cost efficiency. The derivation and chip implementation results show that the proposed pipeline 256-point FFT/IFFT/2D DCT triple-mode chip consumes 22.37 mW at 100 MHz at 1.2-V supply voltage in TSMC 0.13-mum CMOS process, which is very appropriate for the RSoCs IP of next-generation handheld devices.     

Design of an FFT/IFFT Processor for MIMO OFDM Systems

In this paper, we present a novel 128/64 point fast Fourier transform (FFT)/ inverse FFT (IFFT) processor for the applications in a multiple-input multiple-output orthogonal frequency-division multiplexing based IEEE 802.11n wireless local area network baseband processor. The unfolding mixed-radix multipath delay feedback FFT architecture is proposed to efficiently deal with multiple data sequences. The proposed processor not only supports the operation of FFT/IFFT in 128 points and 64 points but can also provide different throughput rates for 1-4 simultaneous data sequences to meet IEEE 802.11n requirements. Furthermore, less hardware complexity is needed in our design compared with traditional four-parallel approach. The proposed FFT/IFFT processor is designed in a 0.13-mum single-poly and eight-metal CMOS process. The core area is 660times2142 mum² , including an FFT/IFFT processor and a test module. At the operation clock rate of 40 MHz, our proposed processor can calculate 128-point FFT with four independent data sequences within 3.2 mus meeting IEEE 802.11n standard requirements     

An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n

A pipelined Fast Fourier Transform and its inverse (FFT/IFFT) processor, which utilizes hardware resources efficiently, is proposed for MIMO-OFDM WLAN 802.11n. Compared with a conventional MIMO-OFDM implementation, (in which as many FFT/IFFT processors as the number of transmit/receive antennas is used), the proposed architecture (using hardware sharing among multiple data sequences) reduces hardware complexity without sacrificing system throughput. Further, the proposed architecture can support 1–4 input data sequences with sequence lengths of 64 or 128, as needed. The FFT/IFFT processor is synthesized using TSMC 0.18 um CMOS technology and saves 25% area compared to a conventional implementation approach using radix-2³ algorithm. The proposed FFT/IFFT processor can be configured to improve power efficiency according to the number of input data sequences and the sequence length. The processor consumes 38 mW at 75 MHz for one input sequence with 64-point length; it consumes 87 mW at 75 MHz for four input sequences with length 128-point and can be efficiently used for IEEE 802.11n WLAN standard.

一个符合IEEE 802.11a标准的新颖FFT/IFFT处理器设计

本文提出了一种新颖的FFT/IFFT处理器结构,并用可编程逻辑器件(CPLD)实现了该结构.这种新型结构有效地结合了传统流水线结构和循环结构的优点,并恰当地满足了802.11a 协议要求的速率,达到了实现面积远小于其它结构的目的.在本文中,用CPLD分别实现了这种新型结构和传统流水线结构,仿真结果证明所提出的新型结构在占用面积上具有较大的优越性.     

A power-scalable reconfigurable FFT/IFFT IC based on a multi-processor ring

A single-chip reconfigurable FFT/IFFT processor that employs a ring-structured multiprocessor architecture is presented. Multi-level reconfigurability is realized by dynamically allocating computation resources needed by specific applications. The processor IC was fabricated in 0.25-/spl mu/m CMOS. It performs 8-point to 4096-point complex FFT/IFFT with power-consumption scalability and provides useful trade-offs between algorithm flexibility, implementation complexity and energy efficiency.     

应用于超宽带系统中的低功耗、高速FFT/IFFT处理器设计

设计了一种应用于超宽带(UWB)无线通信系统中的FFT/IFFT处理器.采用8×8×2混合基算法进行FFT运算,实现了2路64点或者1路128点FFT功能,并为该算法提出了一种新型的8路并行反馈结构.该结构提高了处理器的数据吞吐率,降低了芯片功耗.为了减少处理器中的乘法数目,提高时序性能,提出了改进型移位加算法.设计的FFT/IFFT处理器采用SMIC 0.13μm CMOS工艺制造,芯片的核心面积为1.44mm2.测试结果表明,该芯片最高数据吞吐率到达1Gsample/s,在典型的工作频率500Msample/s下,芯片功耗为39.6mW.与现有同类型FFT芯片相比,该芯片面积缩小了40%,功耗减少了45%.     

Scalable FFT Processors and Pipelined Butterfly Units

This paper considers partial-column radix-2 FFT processors and realizations of butterfly operations. The area and power-efficiency of butterfly units to be used in the proposed processor organization based on bit-parallel multipliers, distributed arithmetic, and CORDIC are analyzed and compared. All the selected butterfly units are synthesized onto the same 0.11 μ ASIC technology allowing the results to be compared. The proposed processor organization permits the area of the FFT implementation to be traded against the computation time, thus the final structure can be easily tailored according to the requirements of the given application. The power consumption comparison shows that butterflies based on bit-parallel multipliers are power-efficient but have limitations on clock frequency. Butterflies based on distributed arithmetic could be used when higher clock frequencies are used. If extremely long FFTs are needed, the CORDIC based butterflies are applicable. Jarmo Takala received his M.Sc. (hons) degree in Electronics and Dr.Tech. degree in Information Technology from Tampere University of Technology, Tampere, Finland (TUT) in 1987 and 1999, respectively. From 1992 to 1996, he was a Research Scientist at VTT-Automation, Tampere, Finland. Between 1995 and 1996, he was a Senior Research Engineer at Nokia Research Center, Tampere, Finland. From 1996 to 1999, he was a Researcher at TUT. Currently, he is Professor in Computer Engineering at TUT and head of the Insitute of Digital and Computer Systems of TUT. His research interests include circuit techniques, parallel architectures, and design methodologies for digital signal processing systems. Konsta Punkka received his M.Sc. degree (hons) in Electrical Engineering from Tampere University of Technology (TUT), in 2002. He is currently working towards his Dr.Tech. degree as a research scientist in the Institute of Digital and Computer Systems at TUT. His research interests include optimization and implementation of DSP architectures.     

64点基-4 FFT/IFFT的FPGA实现

文章通过采用三级流水线设计方式的基-4碟形单元,实现了按时问抽取的,位长为8bit的64点复数FFT/IFFT的设计.并且通过simulink仿真,采用VHDL语言描述,最后通过Quartus得以验证.