A Quantum-Corrected Monte Carlo Study on Quasi-Ballistic Transport in Nanoscale MOSFETs

In this paper, the authors study a quasi-ballistic transport in nanoscale Si-MOSFETs based upon a quantum-corrected Monte Carlo device simulation to explore an ultimate device performance. It was found that, when a channel length becomes shorter than 30 nm, an average electron velocity at the source-end of the channel increases due to ballistic transport effects, and then, it approaches a ballistic limit in a sub-10-nm regime. Furthermore, the authors elucidated a physical mechanism creating an asymmetric momentum distribution function at the source-end of the channel and the influences of backscattering from the channel region. The authors also demonstrated that an electron injection velocity at a perfectly ballistic transport is independent of the channel length and corresponds well to a prediction from Natori's analytical model     

Impact of Line-Edge Roughness on Double-Gate Schottky-Barrier Field-Effect Transistors

The impact of line-edge roughness (LER) on double-gate (DG) Schottky-barrier field-effect transistors (SBFETs) in the level of device and circuit was investigated by a statistical simulation. The LER sequence is statistically generated by a Fourier analysis of the power spectrum of the Gaussian autocorrelation function. The results show that SBFETs are more sensitive to the LER effect in the high-$V_{rm gs}$ region and less sensitive in the subthreshold region compared with DG FinFETs. The aggressive fluctuation of drive current can be attributed to the variation of tunneling barrier width. Lowering the Schottky-barrier height and increasing the silicon-body thickness can suppress the parameter fluctuations from the LER effect. The simulation also shows that a 6T SRAM cell consisting of SBFETs is more vulnerable to noise disturbance than its counterpart consisting of FinFETs, particularly for the read operation, which is due to a larger mismatch of drivability of SBFETs within the cell.      

Experimental Investigation on the Quasi-Ballistic Transport: Part II—Backscattering Coefficient Extraction and Link With the Mobility

Using a new extraction methodology taking into account multisubband population and carrier degeneracy, we have experimentally determined backscattering coefficients, ballistic ratios, and injection velocities of n- and p-FDSOI devices with gate lengths down to 30 nm in the saturated and, for the first time, in the linear regimes. The evolution of these quasi-ballistic parameters is examined as a function of the inversion charge in the channel and at temperatures ranging from 50 to 293 K, showing stronger ballistic ratios in the saturated regime than in the linear one. We particularly focus on the linear regime, and a model linking ballisticity ratios and effective mobility is proposed and validated experimentally for different gate lengths. According to the experimental evaluation of the device mean-free path and its evolution with both the inversion charge in the channel and the temperature, we investigate the mobility degradation with decreasing gate lengths, highlighting the importance of Coulomb scattering on this unexpected mobility behavior.      

Experimental Investigation on the Quasi-Ballistic Transport: Part I—Determination of a New Backscattering Coefficient Extraction Methodology

A new fully experimental method to determine the backscattering coefficient and the ballistic ratio of n- and p-FDSOI and multigate nanodevices is proposed in this paper. This technique is the first one that takes multisubband population, carrier degeneracy, and short channel effects into account. Owing to self-consistent Poisson–SchrÖdinger simulations, common assumptions such as one subband occupied by carriers are investigated. For the first time, universal abaci, which are functional whatever the architecture dimensions and the gate/substrate polarizations, have been developed in order to accurately extract backscattering coefficients for n- and p-FDSOI MOSFETs, both in linear and saturated regimes.      

直接隧穿栅电流对CMOS逻辑电路的影响

对于纳米级的CMOS电路,由于MOS器件具有超薄的氧化层,栅隧穿漏电流的存在严重地影响了电路的正常工作。本文基于可靠性理论和电路级仿真深入地研究直接隧穿电流对CMOS逻辑电路的影响。仿真结果很好地与理论分析相符合,这些理论和仿真将有助于以后的集成电路设计。     

Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency and Apparent Mobility

As devices continue scaling down into nanometer regime, carrier transport becomes critically important. In this paper, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top–down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is adopted, which takes into account the impact of temperature dependence of parasitic source resistance in SNWTs. The highest ballistic efficiency at room temperature is observed in sub-40-nm n-channel SNWTs due to their quasi-1-D carrier transport. The apparent mobility of GAA SNWTs are also extracted, showing their close proximity to the ballistic limit as shrinking the gate length, which can be explained by Shur's model. The physical understanding of the apparent mobility in SNWTs is also discussed using flux's scattering matrix method.      

Influence of Elastic and Inelastic Phonon Scattering on the Drive Current of Quasi-Ballistic MOSFETs

In this paper, we study the influence of elastic and inelastic phonon scattering on the drive current of Si MOSFETs under quasi-ballistic transport. Inelastic phonon emission involving energy relaxation helps achieve ballistic current, even in the presence of scattering, if the channel length is scaled down to the 10-nm scale. This result agrees with Natori's previous predictions. However, for longer channel devices, inelastic phonon emission degrades the drain current due to space charge effects caused by charge accumulation. We also demonstrate that source-end potential engineering to electrically reduce the bottleneck barrier length can result in a ballistic current even in longer channel devices.      

Importance of Backscattering Effects in Ballistic Quantum Transport in Mesoscopic Ring Structures

We have found that in the ballistic electron transport in a ring structure, the junction-backscattering contribution is critical for all the major features of the Aharonov-Bohm-type interference patterns. In particular, by considering the backscattering effect, we present new and clear interpretation about the physical origin of the secondary minima in the electrostatic Aharonov-Bohm effect and that of the h/2e oscillations when both the electric and magnetic potentials are present. We have devised a convenient scheme of expanding the conductance by the junction backscattering amplitude, which enables us to determine most important electron paths among infinitely many paths and to gain insight about their contributions to the interference patterns. Based on the scheme, we have identified various interesting interference phenomena in the ballistic ring structure and found that the backscattering effect plays a critical role in all of them.     

Impact of Energy Quantization on the Performance of Current-Biased SET Circuits

The current-biased single electron transistor (SET) (CBS) is an integral part of almost all hybrid CMOS SET circuits. In this paper, for the first time, the effects of energy quantization on the performance of CBS-based circuits are studied through analytical modeling and Monte Carlo simulations. It is demonstrated that energy quantization has no impact on the gain of the CBS characteristics, although it changes the output voltage levels and oscillation periodicity. The effects of energy quantization are further studied for two circuits: negative differential resistance (NDR) and neuron cell, which use the CBS. A new model for the conductance of NDR characteristics is also formulated that includes the energy quantization term.      

Kink效应对低温CMOS读出电路的影响

在深低温下（T〈50K），CMOS器件会出现Kink效应，即Ⅰ-Ⅴ特性曲线会发生扭曲。当漏源电压较大时（Vds〉4V），漏电流突然加大，电流曲线偏离正常的平方关系。本文通过实验表明，Kink效应对CMOS读出电路中的一些电路结构产生较严重的影响，Kink效应会导致源跟随器输出产生严重的非线性；对于共源放大器和两级运放，Kink效应会使其增益产生非线性。最后，针对影响低温读出电路性能的Kink效应进行分析和研究，提出在低温CMOS读出集成电路设计中如何解决这些问题的方案。     

Kink效应对低温CMOS读出电路的影响

在深低温下(T＜50K),CMOS器件会出现Kink效应,即Ⅰ-Ⅴ特性曲线会发生扭曲.当漏源电压较大时(Vds＞4V),漏电流突然加大,电流曲线偏离正常的平方关系.本文通过实验表明,Kink效应对CMOS读出电路中的一些电路结构产生较严重的影响,Kink效应会导致源跟随器输出产生严重的非线性;对于共源放大器和两级运放,Kink效应会使其增益产生非线性.最后,针对影响低温读出电路性能的Kink效应进行分析和研究,提出在低温CMOS读出集成电路设计中如何解决这些问题的方案.     

Ultra-Wideband Signal Impact on the Performances of IEEE 802.11b and Bluetooth Networks

This paper presents the results of a coexistence study investigating the impact of ultra-wideband (UWB) interference on IEEE 802.11b and Bluetooth networks. The results are based on the experimental test measurements made at the University of Oulu, Finland. Simple high-power UWB transmitters are used to interfere with victim networks. Preliminary results show that only under extreme interference conditions with thousands of equivalent Federal Communications Commission– (FCC)-compliant devices in close proximity, will the IEEE 802.11b and Bluetooth networks experience significant performance degradation. The impact of the UWB interference on the IEEE 802.11b network was insignificant if the distance to UWB transmitters was greater than 40 cm. The impact on Bluetooth was even less noticeable. In our study, several high-power UWB transmitters that greatly exceed the FCC radiation regulations have been used, and the measurement settings presents the worst case scenario because of the very short distance between the interferers and the victim system. Effectively our study approximates the use of thousands of FCC-complaint UWB devices in the same space.     

Scaling Limits of Double-Gate and Surround-Gate Z-RAM Cells

We consider the scaling of the capacitorless single-transistor [zero-capacitor RAM (Z-RAM)] dynamic RAM (DRAM) cells having surround-gate and double-gate structures. We find that the scaling is limited to the channel length of approximately 25 nm for both types of cells, which is somewhat more pessimistic than previously believed. The mechanisms that are found to be of most importance in imposing the scaling limits are as follows: 1) short-channel effects; 2) quantum confinement of carriers in the body; and 3) band-to-band tunneling at the source/drain-to-body junctions. Like other DRAM cells, practical considerations such as the process variations in cell dimensions, random doping fluctuations, and single-event upsets are likely to remain as important scaling concerns for Z-RAM cells.     

Impact of Security/AAA on Intelligent Transport Systems

On-demand type DSRC (Dedicated Short Range Communication) system is one of the future target RVC (Road-to-Vehicle Communication) system in ITS (Intelligent Transport Systems). This paper investigates the permissible range of contents download volume focusing on the duration time of vehicle passage thought a spot and the download time of contents in addition to authentication process time. It is clarified that the most priority technical issue is the realization of the real-time characteristics in the On-demand type DSRC system.     

The Realization of Large-Scale Photonic Integrated Circuits and the Associated Impact on Fiber-Optic Communication Systems

Large-scale photonic integrated circuits (LS PICs) have been extensively deployed throughout the fiber optic communication network. This paper discusses the properties of the LS PICs, the interaction between them, and what is necessary to create an optical transport system that fully utilizes the properties of the LS PIC     

5G无线网络架构对传输网的影响

为了满足3种5G典型业务的覆盖和容量的需求,5G网络中引入了非独立和独立部署4G和5G组网架构以及集中单元(CU)/分布单元(DU)分离的设备形态。新的无线网络架构对于未来传输网的部署也提出了新的挑战。基于当前5G网络架构的标准进展,从无线网络的角度分析了5G网络架构对传输网的影响和需求。     

有源电路和无源电路术语的讨论

本文讨论了理想电路、实际电路中有源电路和无源电路术语的精确含义和受控源的概念,指出理想电路中有源电路和无源电路术语容易引起歧义;举例说明含有有源元件的理想电路既可以是有源电路,也可以是无源电路。笔者提出了对理想电路应使用理想有源电路和理想无源电路术语,对实际电路应使用实际有源电路和实际无源电路术语的观点。     

Modeling and Analysis of Parasitic Resistance in Double-Gate FinFETs

A comprehensive model is presented to analyze the three-dimensional (3-D) source-drain (S/D) resistance of undoped double-gated FinFETs of wide and narrow S/D width. The model incorporates the contribution of spreading, sheet, and contact resistances. The spreading resistance is modeled using a standard two-dimensional (2-D) model generalized to 3-D. The contact resistance is modeled by generalizing the one-dimensional (1-D) transmission line model to 2-D and 3-D with appropriate boundary conditions. The model is compared with the S/D resistance determined from 3-D device simulations and experimental data. We show excellent agreement between our model, the simulations, and experimental data.     

Explicit Analytical Charge and Capacitance Models of Undoped Double-Gate MOSFETs

An analytical, explicit, and continuous-charge model for undoped symmetrical double-gate (DG) MOSFETs is presented. This charge model allows obtaining analytical expressions of all total capacitances. The model is based on a unified-charge-control model derived from Poisson's equation and is valid from below to well above threshold, showing a smooth transition between the different regimes. The drain current, charge, and capacitances are written as continuous explicit functions of the applied bias. We obtained very good agreement between the calculated capacitance characteristics and 2-D numerical device simulations, for different silicon film thicknesses.