Improved FFSBM Algorithm and Its VLSI Architecture for AVS Video Standard

The Video part of AVS （Audio Video Coding Standard） has been finalized recently. It has adopted variable block size motion compensation to improve its coding efficiency. This has brought heavy computation burden when it is applied to compress the HDTV （high definition television） content. Based on the original FFSBM （fast full search blocking matching）, this paper proposes an improved FFSBM algorithm to adaptively reduce the complexity of motion estimation according to the actual motion intensity. The main idea of the proposed algorithm is to use the statistical distribution of MVD （motion vector difference）. A VLSI （very large scale integration） architecture is also proposed to implement the improved motion estimation algorithm. Experimental results show that this algorithm-hardware co-design gives better tradeoff of gate-count and throughput than the existing ones and is a proper solution for the variable block size motion estimation in AVS.     

AVS分数像素插值算法的VLSI实现

基于AVS运动补偿分数像素插值算法,提出了一种新的VLSI结构,满足了AVS基准档次6.2级别(1920×1080,4:2:2,30f/s)高清视频实时解码的要求。介绍了AVS分数像素插值算法,采用一种新的基于移位寄存器的寄存器文件作为内部像素存储器,提高了并行处理效率,并将脉动阵列应用到AVS插值滤波器中,有效提高了运动补偿插值运算的速度。     

具有高效缓冲策略的运动估计阵列处理器结构

基于改进的线性处理器阵列,提出了一种用于全搜索运动估计的阵列处理器结构,它可以并行执行运算而只要求串行的数据输入.分析表明这种结构不仅执行效率高,而且内部缓冲区很小.由于其简单的结构和规则的数据流,它可以方便地在FPGA器件中实现,用作实时编码器的协处理器.     

蝶形运动估计算法及其VLSI实现

视频技术发展要求更高速,更利于硬件实现的运动估计算法.提出了一种蝶形运动估计算法,该算法采用蝶形搜索模板、快速截止技术和运动向量预测技术.该算法较钻石搜索算法提速43.26%-80%,并且图像质量更好.同时,本文采用加法树和片内并行存储器,构建该算法的VLSI实现结构.通过两种数据映射方法(拉丁方映射和4×4块映射),该结构不但解决了快速搜索算法的数据不规则性难题,并且节省了带宽.当系统时钟为27MHz,数据总线为16位,外部存储器带宽要求仅为4.57Mbit/s.比较其它硬件实现结构,该结构采用了更少的处理单元数,更小的缓存单元,但却获得更快的速度和更高的灵活性.     

Buffer structure optimized VLSI architecture for efficient hierarchical integer pixel motion estimation implementation

Integer pixel motion estimation (IME) is one crucial module with high complexity in high-definition video encoder. Efficient algorithm and architecture joint design is supposed to tradeoff multiple target parameters including throughput capacity, logic gate, on-chip SRAM size, memory bandwidth, and rate distortion performance. Data organization and on-chip buffer structure are crucial factors for IME architecture design, accounting for multiple target performance tradeoff. In this work, we combine global hierarchical search and local full search to propose hardware efficient IME algorithm, and then propose hardware VLSI architecture with optimized on-chip buffer structure. The major contribution of this work is characterized by: (1) improved hierarchical IME algorithm with presearch and deliberate data organization, (2) multistage on-chip reference pixel buffer structure with high data reuse between integer and fraction pixel motion estimations, (3) highly reused and reconfigurable processing element structure. The optimized data organization and buffer structure achieves nearly 70 % buffer saving with less than average 0.08, 0.12 dB the worst case, PSNR degradation compared with full search based architecture. At the hardware cost of 336 and 382 K logic gate and 20 kB SRAM, the proposed architecture achieves the throughput of 384 and 272 cycles per macroblock, at system frequency of 95 and 264 MHz for 1080p and QFHD @30fps format video coding.     

Bio-inspired heterogeneous architecture for real-time pedestrian detection applications

Along with the development of powerful processing platforms, heterogeneous architectures are nowadays permitting new design space explorations. In this paper, we propose a novel heterogeneous architecture for reliable pedestrian detection applications. It deploys an efficient Histogram of Oriented Gradient pipeline tightly coupled with a neuro-inspired spatio-temporal filter. By relying on hardware–software co-design principles, our architecture is capable of processing video sequences from real-word dynamic environments in real time. The paper presents the implemented algorithm and details the proposed architecture for executing it, exposing in particular the partitioning decisions made to meet the required performance. A prototype implementation is described and the results obtained are discussed with respect to other state-of-the-art solutions.     

Block-matching algorithm based on an adaptive reduction of the search area for motion estimation

The motion estimation and compensation technique is widely used for video coding applications but the real-time motion estimation is not easy due to its enormous computations. In this paper, a new adaptive reduction of search area for the block-matching algorithm is presented to reduce the computational complexity of the full search block-matching algorithm for low bit-rate video coding. The proposed method exploits the correlation of successive video frames and adjusts the size of search area depending on the displaced block difference and the block classification information in the previous frames of the block. Simulation results show that the proposed algorithm has similar mean square error performance to the full search block-matching algorithm but only requires less a half computational complexity than the full search algorithm.     

Three-level pipelined multi-resolution integer motion estimation engine with optimized reference data sharing search for AVS

Integer motion estimation (IME), which acts as a key component in video encoder, is to remove temporal redundancies by searching the best integer motion vectors for dynamic partition blocks in a macro-block (MB). Huge memory bandwidth requirements and unbearable computational resource demanding are two key bottlenecks in IME engine design, especially for large search window (SW) cases. In this paper, a three-level pipelined VLSI architecture design is proposed, where efficiently integrates the reference data sharing search (RDSS) into multi-resolution motion estimation algorithm (MMEA). First, a hardware-friendly MMEA algorithm is mapped into three-level pipelined architecture with neglected coding quality loss. Second, sub-sampled RDSS coupled with Level C?+?are adopted to reduce on-chip memory and bandwidth at the coarsest and middle level. Data sharing between IME and fractional motion estimation (FME) is achieved by loading only a local predictive SW at the finest level. Finally, the three levels are parallelized and pipelined to guarantee the gradual refinement of MMEA and the hardware utilization. Experimental results show that the proposed architecture can reach a good balance among complexity, on-chip memory, bandwidth, and the data flow regularity. Only 320 processing elements (PE) within 550 cycles are required for IME search, where the SW is set to 256?×?256. Our architecture can achieve 1080P@30 fps real-time processing at the working frequency of 134.6 MHz, with 135 K gates and 8.93 KB on-chip memory.     

一种采用内部预测的快速菱形算法

高效的运动估计算法是视频编解码技术的研究重点.为提高视频编码中运动估计的速度,基于误差函数的单峰假设,提出一种采用内部预测的快速菱形算法,通过对菱形算法进行内部预测从而减少运动估计的搜索点数,并利用运动矢量的相关性来进行起点预测,将图像划分为不同运动类型从而选用不同的搜索方式.先排除静止块,对小运动块直接进行一步菱形小模板搜索.大运动块则采用内部预测的快速菱形算法.实验结果证明此算法在保证图像质量的前提下,大大加快了搜索速度.     

Content adaptive fast motion estimation based on spatio-temporal homogeneity analysis and motion classification

In video coding, research is focused on the development of fast motion estimation (ME) algorithms while keeping the coding distortion as small as possible. It has been observed that the real world video sequences exhibit a wide range of motion content, from uniform to random, therefore if the motion characteristics of video sequences are taken into account before hand, it is possible to develop a robust motion estimation algorithm that is suitable for all kinds of video sequences. This is the basis of the proposed algorithm. The proposed algorithm involves a multistage approach that includes motion vector prediction and motion classification using the characteristics of video sequences. In the first step, spatio-temporal correlation has been used for initial search centre prediction. This strategy decreases the effect of unimodal error surface assumption and it also moves the search closer to the global minimum hence increasing the computation speed. Secondly, the homogeneity analysis helps to identify smooth and random motion. Thirdly, global minimum prediction based on unimodal error surface assumption helps to identify the proximity of global minimum. Fourthly, adaptive search pattern selection takes into account various types of motion content by dynamically switching between stationary, center biased and, uniform search patterns. Finally, the early termination of the search process is adaptive and is based on the homogeneity between the neighboring blocks.Extensive simulation results for several video sequences affirm the effectiveness of the proposed algorithm. The self-tuning property enables the algorithm to perform well for several types of benchmark sequences, yielding better video quality and less complexity as compared to other ME algorithms. Implementation of proposed algorithm in JM12.2 of H.264/AVC shows reduction in computational complexity measured in terms of encoding time while maintaining almost same bit rate and PSNR as compared to Full Search algorithm.     

基于运动空间相关性和时间连续性的运动估算快速算法

运动估算是视频信号的帧间预测编码中的一个重要环节,其效率和精度直接影响到编码器的性能。由于全搜索算法搜索速度较低,而很少采用,故目前普遍采用三步法、交叉法等各种快速近似算法,但是这些算法匹配精度较低,而且某些情况下应用效果不好。为解决上述算法存在的问题,在对视频编码中运动物体的空间相关性和时间连续性进行分析的基础上,给出了一种利用运动物体的空间相关性和时间连续性来进行运动估算的快速算法。实验结果表明,该算法计算每个宏块运动矢量所需的平均搜索次数低于三步法,而匹配精度则非常接近于全搜索算法,并且采用该算法的编码器,其总的编码输出位数少于采用全搜索算法的编码器。     

一种新的快速两级块匹配运动估计算法

针对MPEG-2视频编码运动估计,提出了一种新的快速两级块匹配算法.分析表明 该算法的数据流量和计算量更小,且更易于VLSI实现.实验表明该算法具有很好的质量性 能.     

H.264中基于多分辨率高效帧间预测算法

针对H.264视频编码标准,提出一种帧间编码的快速模式选择和运动搜索算法。此算法基于多分辨率运动估计方案和新率失真模型进行预测模式快速选择,并结合带提前退出准则的快速搜索算法来加速搜索过程。新算法能使运动估计的计算复杂度大幅降低。实验结果表明,同全搜索算法相比,在编码效率略微下降条件下,编码速度提高60到120倍。     

一种基于H.264的可变块快速运动估计算法

H.264是最新的视频编码标准,它相对于以前的视频编码标准在编码效率上有了巨大的提高。高编码效率得益于采用了一系列新的编码技术,这也导致了较高的计算复杂度。H.264运用了可变块运动估计方法,这也是H.264编码过程中最耗时的模块。提出了一种基于H.264的可变块快速运动估计算法。该算法基于以下3种策略:静止块的预测、非静止块的预测搜索和合并过程中的自适应精细搜索。试验结果证明,该算法能够将计算复杂度降低到快速全搜索运动估计算法的3%,而PSNR和码率几乎与快速全搜索算法得到的结果相当。     

An Efficient VLSI Architecture for Motion Compensation of AVS HDTV Decoder

In the part 2 of advanced Audio Video coding Standard （AVS-P2）, many efficient coding tools are adopted in motion compensation, such as new motion vector prediction, symmetric matching, quarter precision interpolation, etc. However, these new features enormously increase the computational complexity and the memory bandwidth requirement, which make motion compensation a difficult component in the implementation of the AVS HDTV decoder. This paper proposes an efficient motion compensation architecture for AVS-P2 video standard up to the Level 6.2 of the Jizhun Profile. It has a macroblock-level pipelined structure which consists of MV predictor unit, reference fetch unit and pixel interpolation unit. The proposed architecture exploits the parallelism in the AVS motion compensation algorithm to accelerate the speed of operations and uses the dedicated design to optimize the memory access. And it has been integrated in a prototype chip which is fabricated with TSMC 0.18-#m CMOS technology, and the experimental results show that this architecture can achieve the real time AVS-P2 decoding for the HDTV 1080i （1920 - 1088 4 ： 2 ： 0 60field/s） video. The efficient design can work at the frequency of 148.5MHz and the total gate count is about 225K.     

H.264中基于全零块检测的快速运动搜索算法

为了降低视频编码标准H．264中运动搜索的复杂度，提出了一种新的基于全零块检测的运动搜索提前中止算法。根据整数离散余弦变换（DCT）和量化的特点，该算法给出了自适应的检测门限和提前中止条件。通过检测门限与绝对差和（SAD）的比较来判断是否停止运动搜索。实验结果表明，在图像质量基本不变的情况下，此方法可以有效减少运动搜索的计算量。     

Interactive scheduling for mobile multimedia service in M2M environment

Computational load of motion estimation in advanced video coding (AVC) standard is significantly high and its more true for HDTV sequences. In this paper, video processing algorithm is mapped onto a learning method to improve machine to machine (M2M) architecture, namely, the parallel reconfigurable computing (PRC) architecture, which consists of multiple units, First, we construct a directed acyclic graph (DAG) to represent the video coding algorithms comprising motion estimation. In the future trillions of devices are connected (M2M) together to provide services and that time power management would be a challenge. Computation aware scheme for different machine is reduced by dynamically scheduling usage of multi-core processing environment for video sequence depending up complexity of the video. And different video coding algorithm is selected depending upon the nature of the video. Simulation results show the effectiveness of the proposed method.     

一种自适应的基于中心偏置特性的矩形搜索方法

H.264编码标准中为了得到更高的压缩比,针对计算量比较大的运动估计部分,采用了六边形运动估计算法。与全搜索算法相比,六边形算法减少了搜索时间,但是,六边形算法采用了固定的模板及固定的搜素步骤,没有充分的利用到视频图像的中心偏置特性。充分利用视频图像的中心偏置特性,提出了一种新的矩形搜索算法,使搜索具有自适应特性,试验表明,在图像质量保持不变的条件下,该算法的搜索速度大幅提高。     

H.266/VVC中一种改进的仿射运动估计算法

通用视频编码标准H.266/VVC通过引入多种新的编码技术,如仿射运动补偿预测、自适应运动矢量精度、多核变换等,以支持360°视频和HDR视频的编解码,从而为用户提供最优的视频质量,但是在H.266/VVC帧间预测过程中,仿射运动估计计算复杂度高导致编码时间显著增加。针对该问题,提出一种改进的仿射运动估计算法。通过对仿射高级矢量预测（AAMVP）候选列表的构建过程进行改进,并构建一种AAMVP候选列表候选项筛选准则,使得列表的候选项更接近编码块真实的运动矢量,从而缩短编码时间。同时对仿射运动估计中迭代搜索最优仿射运动矢量的迭代过程进行优化,以加快迭代搜索速度。实验结果表明,在低时延的编码器配置下,相比VVC原始算法,当BD-BR增加了0.023%时,该算法的总体编码时间平均缩短13%,在保证编码质量的前提下能够有效降低编码的计算复杂度。     

基于上下文的自适应运动搜索算法

通过分析序列编码结果,根据已编码帧预测模式分布和序列的运动信息,对运动特性不同的宏块选择不同的运动搜索方案。结合提前退出策略以及分层的搜索模式,提出一种新的运动搜索算法。实验结果表明,算法编码质量接近全搜索算法,算法执行时间小于全搜索算法,在速度和质量上都优于钻石搜索算法、新3步法、六边形搜索算法,适用于不同运动特性的视频序列。