一种宽带数字T/R组件的设计与实现

提出了一种L波段宽带数字T/R组件的设计方案和实现方法,该方案结合DDWS技术和正交调制技术来产生宽带雷达信号,通过Gbit光纤实现宽带数字T/R组件与雷达主机的数据传输,用一片FPGA完成整个组件的控制。宽带数字T/R组件的参数为中心频率1300 MHz、带宽100 MHz。     

宽带分数延时滤波器的优化设计及FPGA实现

提出了一种可变分数延时宽带数字滤波器的优化设计方法,该方法首先采用内插的方法提高采样率,降低信号的归一化带,再采用Farrow结构来实现分数延时,通过抽取,恢复信号的初始采样率.其实现形式采用基于多相滤波的级联结构,使得内插和抽取相互抵消,降低滤波器的阶数,提高运算效率.采用基于FPGA的并行分布式算法,设计利用了器件的结构特点以及与器件特性独立的2种方法,在时域实现了高速、高阶的宽带分数延时滤波器,并在Altera Stratix FPGA上进行了仿真验证,最高工作频率分别为184 MHz和119 MHz.     

基于多相滤波的数字接收机的FPGA实现

给出了一种基于多相滤波的数字信道化接收机的实现方法,系统的处理带宽为875MHz,解决了高速ADC与FPGA处理速度之间的矛盾。为了克服信道化接收机的接收盲区,采用信道重叠的方法,连续覆盖瞬时带宽。在信道化处理后接测频模块,可以消除虚假信号的输出和提高测频精度。整个接收机在单片FPGA中实现,能够检测同时到达的两个信号,并实时输出脉冲描述字（PDW）,经FPGA时序仿真结果验证了算法模型的正确性和有效性。     

多相滤波的数字相干检波原理及FPGA实现

多相滤波是实现数字下变频及数字相干检波的关键技术,是雷达、声纳和通信等系统中为数字信号处理提供高质量的正交信号的有效手段。文中讨论了多相滤波的基本原理,给出了采用多相滤波的方法对中频带限信号处理的仿真分析,并结合一款脉冲压缩雷达中频数字化接收机的实现方案进行工程验证,结果表明,在技术指标上可有效克服正交通道不一致问题,具有较高的应用价值。     

基于多相滤波的通用数字信道化技术

传统的信道化技术一旦信道带宽确定后,滤波计算时分解的相数和信道化后的时域分辨率也相应确定,耦合性较强,导致信道化技术在实际工程使用时灵活性存在一定的不足。文中首先给出了基于多相滤波的实信号数字信道化数学模型;然后,在此基础上推导了通用数字信道化数学表达式;最后,通过仿真验证了通用数字信道化技术的正确性。文中提出的通用数字信道化技术有效实现了信道带宽与多相滤波相数、信道化后时域分辨率的解耦,增加了系统设计和信道化技术应用的便捷性。     

A polyphase filter based on CMOS inverters

A new idea for generation of quadrature signals on chip is presented. The topology is based on a passive RC polyphase filter, where the resistive parts are made active by using inverters. The active filter combines quadrature generation, isolation, and gain without losing quadrature performance compared to a regular RC polyphase filter. The filter technique is demonstrated in a 10 GHz front-end application where a broadband VCO, having a tuning range of 1.44 GHz, drives an active polyphase filter to generate quadrature LO signals. According to simulations the quadrature phase error shows a typical tuned behavior and stays below 0.8° for the complete tuning range. Since the signal amplitude is high throughout the filter the noise is low, below 160 dBc/Hz at 10 MHz offset. The high amplitude also reduces the need for high gain tuned buffers, thereby enabling significant reductions in chip area.     

Narrow-band FIR filtering with FPGAs using sigma-delta modulation encoding

This paper addresses the problem of implementing narrow-band FIR filters using FPGAs. Rather than employing a conventional multiply-accumulate unit to compute the inner-product, an alternative method based on re-quantization of the input data stream using a sigma-delta modulator is presented. The re-quantization process preserves the dynamic range of the signal components contained in the bandwidth of the filter, while shifting the re-quantization noise to the spectral region to be rejected by the filter. The reduced bit length representation of the re-quantized input data samples removes the requirment for a full multiplier in the filter hardware. This makes the method very attractive for realization using FPGA technology. The filtering technique is described and implementation results using a Xilinx XC4010 FPGA are presented. A 200-tap filter implemented in a single FPGA achieves a computation rate of 415 MOPS and has a memory bandwidth of 1.66 Gbytes/s. An extension of the method using a quadrature re-quantizer and filter is also presented.     

一种多模式合成孔径雷达数字接收机

针对一种多模式极化合成孔径雷达（SAR）,给出了中频数字接收机工作参数选择,混频滤波方法,实现了三种带宽信号的数字正交解调。通过分析同相、正交通道误差对正交解调性能的影响,确定了滤波器最佳设计准则。最后给出了基于FPGA的实现结构,仿真试验结果表明中频数字接收机性能比一般模拟接收机有显著提高。     

基于FPGA的高速数字下变频系统设计

基于FPGA设计了一高速数字下变频系统,在设计中利用并行NCO和多相滤波相结合的方法有效的降低了数据的速率,以适合数字信号处理器件的工作频率.为了进一步提高系统的整体运行速度,在设计中大量的使用了FPGA中的硬核资源DSP48.Xilinx ISE14.4分析报告显示,电路工作速度可达360MHz.最后给出了在Matlab和ModelSim中仿真的结果,验证了各个模块以及整个系统的正确性.     

A 100 MS/s 4 MHz Bandwidth 70 dB SNR $Delta Sigma$ ADC in 90 nm CMOS

This paper describes the results of an implementation of a high speed $Delta Sigma$ ADC in 90 nm CMOS process, which is developed for a direct-conversion digital TV receiver. The $Delta Sigma$ ADC is based on a switched-capacitor fourth-order single-loop $Delta Sigma$ modulator with a 4-bit quantizer. The ADC uses a triple sampling technique and a two-step summation scheme for low power and high speed operation. Also, a digital signal processing block, including a decimation filter, a channel selection filter and a digital programmable gain amplifier (PGA), is implemented in the same process. The decimation filter is based on a polyphase IIR filter with a decimation ratio of 5, while the channel selection filter is based on two path lattice wave digital IIR filter. The ADC achieves 69.95 dB SNR and 66.85 dB SNDR over a 4 MHz bandwidth with a sampling frequency of 100 MHz. The fabricated $Delta Sigma$ ADC and the digital signal processing block occupy 0.53$~$mm$^2$ and 0.09 mm$^{2}$, and consume 11.76 mW per channel.      

基于FPGA的超宽带波形设计及应用

文中介绍了一种基于高速现场可编程门阵列(FPGA)加上高速数字模拟转化器(DAC)的超宽带任意波形产生的方法,详细阐述了数字上变频技术(DUC)、并行数控振荡器(NCO)和多相有限长单位脉冲响应(FIR)滤波器的原理,提出了基于多相FIR滤波和并行NCO结构的DUC实现方法。该方法最大的特点就是降低了运算速度,便于在FPGA内实现,从而可直接产生带宽大于1 GHz 的任意波形。最后介绍了该方法在工程中的应用,并给出了测试指标。此方法已广泛应用于各类宽带雷达上     

CDMA2000数字中频的设计

在CDMA2000系统中，信道是经过QPSK四相扩频正交调制传输的，数字中频与模拟中频相比能产生严格的幅相平衡正交信号，处理时能保证有严格的线性相位，为此介绍了CDMA2000系统数字中频调制解调实现的方案，对其中抗混叠滤波器，数字频率合成器的设计方法进行了详细的讨论，最后给出了用基于高密度逻辑门电路可编程集成片编辑器（FPGA Compiler)实现的结果。     

变带宽宽带数字下变频器的设计及其FPGA实现

针对宽带数字接收系统要求处理带宽可变和高度抑制干扰的特点,从传统的基于多相结构的宽带DDC出发,引入窄带DDC中整形滤波的概念,设计了带宽可变、阻带抑制高的变带宽宽带DDC,且在FPGA上实现并验证了其设计的有效性。     

A 5-6-GHz polyphase filter with tunable I/Q phase balance

A tunable polyphase filter with integrated input and output buffers was designed and fabricated in a 0.4 /spl mu/m SiGe BiCMOS technology with a 5-6-GHz bandwidth. Series tunable capacitors (varactors) provide phase tunability for the differential quadrature outputs of the polyphase filter. The tunable phase can be used to improve image rejection in Weaver or Hartley architectures, or mitigate in-phase and quadrature (I/Q) phase error in direct conversion or low-IF receivers. The die area of the fabricated circuit with pads is 920 /spl mu/m/spl times/ 755 /spl mu/m. Based on measurements, approximately 15/spl deg/ of I/Q phase imbalance can be tuned out using the fabricated polyphase filter, proving the concept of tunable phase. To the authors' knowledge, this is the first reported tunable I/Q balance polyphase network.     

A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth

This paper presents the design of a 2-2 cascaded continuous-time sigma-delta modulator. The cascaded modulator comprises two stages with second-order continuous-time resonator loopfilters, 4-bit quantizers, and feedback digital-to-analog converters. The digital noise cancellation filter design is determined using continuous-time to discrete-time transformation of the sigma-delta loopfilter transfer functions. The required matching between the analog and digital filter coefficients is achieved by means of simple digital calibration of the noise cancellation filter. Measurement results of a 0.18-/spl mu/m CMOS prototype chip demonstrate 67-dB dynamic range in a 10-MHz bandwidth at 8 times oversampling for a single continuous-time cascaded modulator. Two cascaded modulators in quadrature configuration provide 20-MHz aggregate bandwidth. Measured anti-alias suppression is over 50 dB for input signals in the band from 150 to 170 MHz around the sampling frequency of 160 MHz.     

宽带数字信道化接收机的FPGA实现

为解决现代电子战对接收机处理带宽宽、灵敏度高及实时性处理的要求,提出一种数字信道化接收机的设计方法。在推导高效信道化接收机模型的基础上,采用多相滤波器结构实现的数字信道化接收机。该接收机利用超高速A/D对数据进行高速采样,然后由高性能FPGA进行数据抽取、多相滤波、CORDIC算法等信道化实时处理。为了提高实时性,采用并行IFFT实现。该信道化接收机不仅能稳定输出载频及相位信息,还能处理三路同时到达的不同信号。实际的性能测试结果表明该接收机的功能正确并达到预定指标。     

全数字可配置信道分路技术的设计方法

提出一种全数字可配置信道分路技术的设计方法,是针对多相阵列FFT算法进行的一种串行结构设计,能够按照分路路数灵活配置多相滤波器组和FFT级数,可支持甚至达到上百路的分路路数。对全数字可配置信道分路的设计方法中涉及到的多相滤波器组和FFT两个主要模块的FPGA实现方法进行了详细阐述。基于该设计方法进行了4路、8路和16路信道分路应用的FPGA硬件设计,给出了硬件占用资源情况和误码测试结果,从而证明该设计方法的可实现性。     

Tunable combline filter with continuous control of center frequency and bandwidth

A new combline filter structure with a continuous tunability for both the center frequency and bandwidth is presented in this paper. The passband-width tunability is achieved by placing variable coupling reducers between the filter resonators. The coupling reducers, operating as bandwidth control subnetworks, are designed as detuned resonators made up of a line segment ending in a variable capacitor. The proposed filter structure is experimentally validated with the design, construction in suspended stripline technology, and characterization of a low-cost filter prototype for terrestrial digital video broadcasting receivers operating in the UHF band (470-862 MHz). Other relevant factors, such as the intermodulation distortion produced by the varactors used to control the bandwidth electronically or the power-handling performance of the constructed filter, are also discussed. The reconfigurable filter module described in this paper is very suitable for the design of flexible multifunction receiver subsystems simultaneously supporting signals with a different bandwidth.     

A New Transceiver Architecture for the 60-GHz Band

A new “half-RF” architecture incorporates a polyphase filter in the signal path to allow the use of a local oscillator frequency equal to half the input frequency. The receiver performs 90 $^{circ}$ phase shift and two downconversion steps to produce quadrature baseband outputs. The transmitter upconverts the quadrature baseband signals in two steps, applies the results to a polyphase filter, and sums its outputs. Each path employs a dedicated 30-GHz oscillator and is fabricated in 90-nm CMOS technology. The receiver achieves a noise figure of 5.7–7.1 dB and gain/phase mismatch of 1.1 dB/2.1$^{circ}$ while consuming 36 mW. The transmitter produces a maximum output level of $-$7.2 dBm and an image rejection of 20 dB while drawing 78 mW.      

一种宽带信号数字下变频的实现方法

在宽带、超宽带应用中,单一信号带宽达几百兆赫兹;或者在不同中频同时调制多个信号产生的宽带信号也达数百兆赫兹,用常规的数字下变频方法很难实现。文章提出了一种基于DFT滤波器组的高效数字下变频结构,分析了该解调算法的特点和实现性能。对已知信号带宽和中频的宽带信号,对比了DFT滤波器组和多相分解算法的性能。对信号带宽和中频均在变化的信号,给出了实现思路。最后,给出了该DFT滤波器组的硬件实现方案。