Sidewall-related narrow channel effect in mesa-isolatedfully-depleted ultra-thin SOI NMOS devices

The paper reports the sidewall-related narrow channel effect in mesa-isolated fully-depleted ultra-thin SOI NMOS devices. Based on the study, contrary to bulk NMOS devices, for a channel width shrinking from 1 μm to 0.2 μm, the threshold voltage of mesa-isolated ultra-thin SOI NMOS devices with a 1000 Å thin film doped with 10¹⁷ cm^-3, decreases by 0.145 V for a front gate oxide of 100 Å and a sidewall oxide of 150 Å as a result of the sidewall edge effect     

An SOI voltage-controlled bipolar-MOS device

This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI MOSFET allows lateral bipolar current to be added to the MOS channel current and thereby enhances the current drive capability of the device. Part of the bipolar current emitted by the source terminal merges into the channel before reaching the drain, which renders the base width substantially shorter than the gate length. This novel operating mode of a short-channel SOI transistor is particularly attractive for high-speed operation, since the device is capable of both reduced voltage swing operation and high current drive, n-p-n and p-n-p devices, as well as complementary inverters have been successfully fabricated.     

Hot carrier degradation for narrow width MOSFET with shallow trench isolation

We have investigated the hot carrier reliability characteristics of narrow width MOSFET with shallow trench isolation. In the case of maximum substrate current condition, the lifetime of nMOSFET is slightly degraded by decreasing the device width. However, a significant degradation of device lifetime of the narrow width device was observed under channel hot electron condition (V_g=V_d). In the case of pMOSFET, we also found enhanced degradation of narrow width device under channel hot electron condition. Enhanced degradation of MOSFETs can be explained by both the current crowding and enhanced charge trapping at the shallow trench isolation edge. Considering pass transistor in DRAM cell, the degradation of lifetime for narrow width device under high gate bias condition causes a significant impact on circuit reliability.     

Application of Scanning Capacitance Microscopy on SOI device with wafer edge low yield pattern

As semiconductor technology keeps scaling down, many advanced technology and process were applied in the semiconductor process. Especially for the application of IOT (internet of thing) technology, the low leakage and low power consumption product was the key component for this kind of application. SOI (Silicon-On-Insulator) wafer process is one of the advanced and important branches of the semiconductor manufacturing process. Its intrinsic advantage, low leakage and lower power consuming make it very suitable for personal communication device and IOT which match well with the application requirement. As is well known the SOI wafer is different form the normal bulk silicon wafer. The active sits on the silicon oxide insulator, which makes the final device separate from the substrate. Basically, all of the devices are floating on a nonconductive oxide layer. It comes with many challenges for process and analysis as compared with the conventional bulk silicon process.The most conventional analysis method is not applicable in the SOI device such as the PVC (passive voltage contrast) and current image methodology which are a very powerful and important in the failure analysis.In this paper, scanning capacitance is successfully used as the substitution of the PVC method. The SCM (Scanning Capacitance Microscopy) is a complicated process. Since all of the abnormality or physical change will affect the measured capacitance, then the capacitance signal will theoretically has many information with itself, including open, short and leakage. Through the detailed study, the contact level top-down SCM was successfully applied on the SOI unit. By proper setting of SCM bias condition, it can not only visualize the possible leaky location but also can reveal the possible path. Further nanoprobing and TEM (Transmission Electron Microscopy) have confirmed the SCM analysis.     

An advanced Ge preamorphization salicide technology forultra-thin-film SOI CMOS devices

In this letter, we propose a new approach to implement salicide on thin-film silicon-on-insulator (SOI) through the amorphization of the source/drain (S/D) regions by a germanium implantation. The amorphous film greatly reduces the silicide formation energy and effectively controls the silicide depth. This results in a much lower thermal cycle and increased flexibility in the choice of metal thickness. SOI NMOS devices fabricated using this novel salicide technology have shown substantially reduced S/D resistance as well as good device performance. This technology is applicable to PMOS SOI MOSFETs as well     

Simulation of SOI devices and circuits using BSIM3SOI

A versatile SOI model derived from the BSIM3v3 bulk MOSFET model is capable of simulating partially and fully depleted devices with options for self-heating and floating body effects. The model can automatically switch between fully and partially depleted regimes. After refining body current models we for the first time present successful dc and transient device and circuit simulation of an SOI MOSFET technology with L_eff below 0.2 μm     

Narrow-width SOI devices: the role of quantum-mechanical size quantization effect and unintentional doping on the device operation

The ultimate limits in scaling of conventional MOSFET devices have led the researchers from all over the world to look for novel device concepts, such as ultrathin-body (UTB) silicon-on-insulator (SOI), dual-gate SOI devices, FinFETs, focused ion beam MOSFETs, etc. These novel devices suppress some of the short channel effects exhibited by conventional MOSFETs. However, a lot of the old issues still remain and new issues begin to appear. For example, in UTB SOI devices, dual-gate MOSFETs and in FinFET devices, quantum-mechanical size quantization effects significantly affect the overall device behavior. In addition, unintentional doping leads to considerable fluctuation in key device parameters. In this work we investigate the role of two-dimensional quantization effects in the operation of a narrow-width SOI device using an effective potential scheme in conjunction with a three-dimensional ensemble Monte Carlo particle-based device simulator. We also investigate the influence of unintentional doping on the operation of this device. We find that proper inclusion of quantization effects is needed to explain the experimentally observed width dependence of the threshold voltage. With regard to the problem of unintentional doping, impurities near the middle portion of the source end of the channel have most significant impact on the device drive current and the fluctuations in the device threshold voltage.     

Electromagnetic susceptibility characterization of double SOI device

Under a research project of monolithic pixel detectors, a double silicon on insulator (DSOI) structure was introduced based on fully depleted SOI (FDSOI) technology. It not merely integrates the sensor and readout circuit on the same processed wafer, but also increases radiation tolerance. Electromagnetic susceptibility (EMS) is also an important reliability issue in pixel detectors. The readout circuit should avoid false signal generation due to coupled noise from the substrate. This paper evaluates the performance of DSOI devices regarding total ionizing dose (TID) effect compensation in transistors by applying a negative bias to the middle silicon layer, and evaluates the electromagnetic susceptibility of the substrate by a ring oscillator. The experiment results show that the DSOI device is able to compensate for TID, and the threshold voltage and leakage current are recoverable. However, the reduction of TID effect on the DSOI device is at the expense of increasing susceptibility to electromagnetic interference (EMI) on the substrate.     

Operation of SOI CMOS devices at liquid-nitrogen temperature

Liquid-nitrogen-temperature (LNT) operation of silicon-on-insulator (SOI) CMOS devices has been investigated experimentally. The maximum carrier mobilities in these devices increase by factors from 1.25 to 4.5 between room temperature and LNT. At LNT, the increase in depletion-layer width and the resulting threshold-voltage increase are limited by the silicon film thickness. For SOI devices with a body contact, the series resistance between channel and body contact increases at lower temperature, resulting in a current kink in saturation I-V characteristics     

Investigation on hot-carrier-induced degradation of SOI NLIGBT

The hot-carrier-induced (HCI) degradations of silicon-on-insulator (SOI) lateral insulated gate N-type bipolar transistor (NLIGBT) are investigated in detail by DC voltage stress experiment, TCAD simulation and charge pumping test. The substrate current I_sub and on-state resistance Ron at different voltage stress conditions are measured to assess the HCI effect on device performance. The electric field and impact ionization rate are simulated to assist in providing better physical insights. And charge pumping current is measured to determinate the front-gate interface states density directly. The degradation mechanisms under different gate voltage stress conditions are then presented and summarized.     

An analytical back gate bias dependent threshold voltage model forSiGe-channel ultrathin SOI PMOS devices

An analytical threshold voltage model for SiGe-channel ultrathin SOI PMOS devices is presented. As confirmed by the PISCES simulation results, the analytical model provides a good prediction on the threshold voltage. According to the analytical-formula, depending on the back gate bias, the SiGe-channel SOI PMOS device may have a conduction channel at the top or the bottom of the SiGe channel or at the top of the field oxide     

TLP Characterization of large gate width devices

The maximum transient voltage of a MOSFET device is one of the key parameters for power applications. Therefore, transmission line pulse (TLP) characterization is used to assess this. TLP measurements on large gate width devices are difficult to perform due to gate oscillations.In this paper, a method to avoid oscillation when measuring large gate width devices is presented. Device simulations are presented showing gate side oscillation triggered by the rising edge of the 100 ns TLP pulse. Adding a resistor in series with the gate largely damps the oscillation. Comparison between system level simulation and captured TLP waveforms is done and the correlation is discussed.     

Threshold voltage degradation under high Vgs and low Vds on 200 V SOI power devices

The hot-carrier degradation behavior of the 200 V lateral insulated gate bipolar transistor and lateral diffused MOS transistor both on SOI substrates (SOI-LIGBT and SOI-LDMOS) under high Vgs and low Vds is experimentally investigated. It is shown that the hot electron injection and trapping into gate oxide in the channel region will domains the degradation, which results in the positive threshold voltage (Vth) shift, however, it is very interesting that the degradation level in SOI-LIGBT device is much more serious than that in SOI-LDMOS device. Finally, an improved method to reduce the Vth degradation of SOI-LIGBT is also presented, which is adding a P-type buried layer under the source to change the hole current path. All the results have been verified by MEDICI simulations.     

The influence of stud bumping stress on device degradation in scaled MOSFETs

This paper presents the effect of area bumping on device degradation in scaled metal-oxide-semiconductor field-effect transistors (MOSFETs). We have investigated the gate channel length dependence of g_m degradation after stud bumping above the MOSFETs and changes in the charge pumping currents for those devices. The von Mises’s equivalent stress is used to simulate the distribution of mechanical stress at the gate edges. From the relationship between the distribution of the von Mises’s equivalent stress and the change in the charge pumping currents after stud bumping, we show that stress concentrates within 0.1 μm of the gate edges. Furthermore, by estimating the amount of increased interface-state density we predicted that stud bumping stress greatly influences the device degradation of scaled MOS devices.     

The influence of gate edge shape on the degradation in hot-carrierstressing of n-channel transistors

The hot-carrier properties of planar and graded gate structures (upturning of the gate edge in the gate overlap region) of n-MOS transistors were examined. It was found that the type of degradation suffered by each type of device depends on the shape of the gate edge. This is interpreted in terms of the degree of gate control of the gate over the region in which the damage takes place in the different devices. The nongraded gate (NGG) devices degrade chiefly by a V_t shift, whereas the graded gate (GG) devices show a pronounced transconductance decay, with practically no V_t shift. It is suggested that the damage is situated in the gate overlap region, and that the different degradations result from a weaker field control of the gate over the degraded region leading to a series resistance type of effect in the case of the GG structure. This is supported by two-dimensional simulations     

Single-transistor-latch-induced degradation of front- andback-channel thin-film SOI transistors

The front- and back-channel transistor characteristics in thin-film silicon-on-insulator (SOI) MOSFETs have been studied before and after front-channel hot-carrier stress resulting from single-transistor latch. This stress causes the following significant changes: (a) a reduction of the front-channel current for a given gate voltage, (b) an increase in front-channel drain-source breakdown voltage when measured in the reverse mode, and (c) a decrease in the back-channel transconductance. These changes can be attributed to the hot-carrier induced interface traps on both front and back interfaces near the drain junction     

The temperature mobility degradation influence on the zero temperature coefficient of partially and fully depleted SOI MOSFETs

The zero temperature coefficient (ZTC) is investigated experimentally in partially (PD) and fully depleted (FD) SOI MOSFET fabricated in a 0.13 μm SOI CMOS technology. A simple model to study the behavior of the gate voltage at ZTC (V_ZTC) is proposed in the linear and the saturation region. The influence of the temperature mobility degradation on V_ZTC is analyzed for PD and FD devices. Experimental results show that the temperature mobility degradation is larger in FD than in PD devices, which is responsible for the V_ZTC decrement observed in FD instead of the increment observed in PD devices when the temperature increases. The analysis takes into account temperature dependence model parameters such as threshold voltage and mobility. The analytical predictions are in very close agreement with experimental results in spite of the simplification used for the V_ZTC model as a function of temperature in the linear and the saturation region.     

An empirical model for device degradation due to hot-carrier injection

An empirical model for device degradation due to hot-carrier injection in submicron n-channel MOSFET's is presented. Relationships between device degradation, drain voltage, and substrate current are clarified on the basis of experiments and modeling. The presented model makes it possible to predict the lifetime of submicron devices by determining a certain criterion, such as taking a Vthshift of 10 mV over ten years as being allowable. This could also provide quantitative guiding principles for devising "hot-carrier resistant" device structures.