PECVD在TSV领域的应用

PECVD设备及工艺技术已在半导体前道互连工艺及TSV领域展现了其广阔的应用前景,介绍了拓荆PECVD在TSV领域的应用,展现其良好的工艺表现。     

基于边沿延时翻转的绑定前硅通孔测试方法

硅通孔（Through-Silicon Via,TSV）在制造过程中发生开路和短路等故障会严重影响3D芯片的可靠性和良率,因此对绑定前的TSV进行故障测试是十分必要的.现有的绑定前TSV测试方法仍存在故障覆盖不完全、面积开销大和测试时间大等问题.为解决这些问题,本文介绍一种基于边沿延时翻转的绑定前TSV测试技术.该方法主要测量物理缺陷导致硅通孔延时的变化量,并将上升沿和下降沿的延时分开测量以便消除二者的相互影响.首先,将上升沿延时变化量转化为对应宽度的脉冲信号;然后,通过脉宽缩减技术测量出该脉冲的宽度;最后,通过触发器的状态提取出测量结果并和无故障TSV参考值进行比较.实验结果表明,本文脉宽缩减测试方法在故障测量范围、面积开销等方面均有明显改善.     

TSV制程关键工艺设备技术及发展

论述了TSV技术发展面临的设备问题,并重点介绍了深硅刻蚀、CVD/PVD沉积、电镀铜填充、晶圆减薄、晶圆键合等几种制约我国TSV技术发展的关键设备。     

三维集成电路中硅通孔缺陷建模及自测试/修复方法研究

硅通孔(Through Silicon Via, TSV)是3维集成电路(3D IC)进行垂直互连的关键技术,而绝缘层短路缺陷和凸点开路缺陷是TSV两种常见的失效形式。该文针对以上两种典型缺陷建立了TSV缺陷模型,研究了侧壁电阻及凸点电阻与TSV尺寸之间的关系,并提出了一种基于TSV缺陷电阻端电压的检测方法。同时,设计了一种可同时检测以上两种缺陷的自测试电路验证所提方法,该自测试电路还可以级联起来完成片内修复功能。通过分析面积开销可得,自测试/修复电路在3D IC中所占比例随CMOS/TSV工艺尺寸减小而减小,随TSV阵列规模增大而减小。     

在图像传感器和存储产品中应用硅通孔工艺的300 mm光刻与键合技术

三维集成的技术优势正在延伸到大量销售的诸如消费类电子设备潜在应用的产品领域。这些新技术也在推进着当前许多生产工艺的包封能力,其中包括光刻工艺和晶圆键合。〉还需要涂胶．形成图形和刻蚀图形结构。研究了一些用于三维封装的光刻和晶圆键合技术问题并将叙述全部的挑战和适用的解决方案。技术方面的处理结果将通过晶圆键合和光刻工序一起讨论。     

RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

3D integration including Through Silicon Vias is more and more considered as the solution to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are hardly required to achieve 3D products and to make design recommendations. In this paper, a 3D process flow is detailed and used to integrate specific RF structures including copper-filled TSVs with 3 μm wide and 15 μm deep dimensions. Both measurements and simulations of these structures lead to the extraction of frequency-dependent parameters and the building of a SPICE compatible π-shaped analytical parametrical model of the TSV.     

小型化硅基毫米波MEMS三维异构集成开关滤波器件

针对传统开关滤波器组件体积庞大、重量重、调试复杂、集成度低的问题,设计并制作了一种小型化六通道毫米波硅基MEMS三维异构集成开关滤波器件。该器件以四层堆叠的高阻硅材料为衬底,工作频段覆盖18~40 GHz,内部集成了6款小型化空间堆叠的MEMS滤波器和2个单片开关,采用3D-TSV（硅通孔）异构集成工艺,实现了开关与滤波器组的晶圆级集成。为了优化毫米波频段集成滤波器性能,提出了MEMS混合交叉耦合多层堆叠SIW（基片集成波导）滤波器拓扑结构,且其工艺与整个开关滤波器件兼容,极大提升了滤波器的带外抑制。经测试,该开关滤波器件带内插损<8.2 dB（包括2个开关共约4 dB的损耗）,反射损耗>10 dB,带边1 GHz处带外抑制>40 dBc。该器件体积仅19.0 mm×16.5 mm×1.1 mm,比传统开关滤波器体积减小了99.7%。     

Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs

Under the current process and layer bonding technology for the TSV (through-silicon-via) based 3D ICs, it is known that the TSV resource is one of the major sources of the function failure of the chip. Furthermore, TSV takes much larger size and pitch than the normal logic components. For this reason, a careful allocation of the TSV resource has been required in 3D IC designs, and several works have been proposed to allocate minimal TSVs. This work also addresses the problem of TSV allocation and optimization, but overcomes one of the critical limitations of the previous works, which is the unawareness or no exploitation of the possibility of TSV resource sharing, previously merely resorting to a simple binding of the data transfers to TSVs. This is because the previous 3D layer partitioners have performed TSV allocation and minimization without any link to the data transfer information accessible from the high-level synthesis flow. This work proposes a set of TSV resource sharing and optimization algorithms (as a post-processing of 3D layer partitioning) by utilizing the life time information of the data transfers taken from the high-level synthesis. Specifically, we propose three algorithms for TSV resource sharing and optimization, which can be selectively applied depending on the sharing granularity and design complexity: (1) word-level TSV sharing, (2) bit-level TSV sharing, and (3) TSV refinement combined with register replication. Through experiments with benchmark designs, it is confirmed that our proposed algorithms are able to reduce the number of TSVs by 41.1% on average in word-level TSV sharing and 26.0% in bit-level TSV sharing compared with the results produced by the conventional layer partitioning with no TSV sharing while still meeting the timing constraint of designs.     

RF-TSV design, modeling and application for 3D multi-core computer systems

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.     

Current status of CMOS low voltage and low power wireless IC designs

This paper surveys recent research on CMOS low voltage and low power IC designs for wireless applications. Advancements and challenges in using nanometer IC processes are addressed, and the impacts of device scaling on wireless systems are discussed. Recent advances in device technologies and system architectures are presented. State-of-the-art low power wireless systems, both from academia and from industry, are summarized. Circuit design techniques and challenges for low voltage and low power applications are discussed, along with RF performance and power trade-offs. Examples of common RF building blocks, e.g. LNA's and VCO's, designed for sub-1V power supplies are presented.     

Characterization and modeling of RF substrate coupling effects in 3D integrated circuit stacking

This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in TSV. A good compatibility between RF measurements and RF simulations allows validating modeling tools for predictive studies. Next, parametric studies are performed in order to study impact of TSV design and materials on substrate coupling noise.