基于边沿延时翻转的绑定前硅通孔测试方法

硅通孔（Through-Silicon Via,TSV）在制造过程中发生开路和短路等故障会严重影响3D芯片的可靠性和良率,因此对绑定前的TSV进行故障测试是十分必要的.现有的绑定前TSV测试方法仍存在故障覆盖不完全、面积开销大和测试时间大等问题.为解决这些问题,本文介绍一种基于边沿延时翻转的绑定前TSV测试技术.该方法主要测量物理缺陷导致硅通孔延时的变化量,并将上升沿和下降沿的延时分开测量以便消除二者的相互影响.首先,将上升沿延时变化量转化为对应宽度的脉冲信号;然后,通过脉宽缩减技术测量出该脉冲的宽度;最后,通过触发器的状态提取出测量结果并和无故障TSV参考值进行比较.实验结果表明,本文脉宽缩减测试方法在故障测量范围、面积开销等方面均有明显改善.     

PECVD在TSV领域的应用

PECVD设备及工艺技术已在半导体前道互连工艺及TSV领域展现了其广阔的应用前景,介绍了拓荆PECVD在TSV领域的应用,展现其良好的工艺表现。     

A transformer with high coupling coefficient and small area based on TSV

Transformer is an important passive device, which is widely used in radio frequency (RF) Integrated circuit (IC). In this paper, three-dimensional transformers with turn ratios of 1:1, 1:2, and 1:3 and with primary and secondary windings nested by TSV technology is proposed. To evaluate the characteristics, the proposed transformers are simulated by HFSS software. The simulation results show that their coupling coefficients are 0.966, 0.966, 0.967, and their area are 3.6 × 10⁻³, 6.0 × 10⁻³, 9.6 × 10⁻³mm². Compared with the other literature, the proposed transformers have good coupling and small area.     

对角线六边形的TSV冗余结构设计

硅通孔(TSV)在制造过程中容易产生各类故障缺陷,导致3D芯片合格率降低。为了解决这一问题,提出一种新的对角线六边形冗余结构,对均匀故障的修复率保持在99%以上,对聚簇故障的修复率与路由冗余结构相近,并高于环形冗余结构。实验结果表明,与环形和路由冗余结构相比,该结构的面积开销分别减小了1.64%和72.99%,修复路径长度分别降低了39.4%和30.81%;与路由结构相比,该结构的时间开销缩短了62.55%。     

三维集成电路中TSV的热特性研究

基于Comsol Multiphysics平台,通过使用有限元仿真对三维集成电路的硅通孔(TSV)模型进行了热仿真分析。分别探究了TSV金属层填充材料及TSV的形状、结构、布局和插入密度对三维(3D)集成电路TSV热特性的影响。结果表明:TSV金属层填充材料的热导率越高,其热特性就越好,并且采用新型碳纳米材料进行填充比采用传统金属材料更能提高3D集成电路的热可靠性;矩形形状的TSV比传统圆形形状的TSV更有利于3D集成电路散热;矩形同轴以及矩形双环TSV相比其他结构TSV,更能提高TSV的热特性;TSV布局越均匀,其热特性越好;随着TSV插入密度的增加,其热特性越好,当插入密度达6%时,增加TSV的数目对TSV热特性的影响将大幅减小。     

一种考虑MOS效应及频变特性的类传输线型锥形TSV通孔电学模型

为准确描述锥形TSV通孔寄生电阻、电容、电感高频下MOS效应及其频变特性,本文首先推导出了锥形TSV通孔压控MOS电容的解析模型。其次基于修正后的双传输线寄生参数提取公式对锥形TSV通孔内寄生参数进行了提取。最终建立了一种考虑MOS效应及频变特性的类传输线型锥形TSV通孔电学模型。通过仿真工具验证模型精度,结果显示：在100GHz频带内模型与仿真结果吻合度较高,可以准确描述高频下锥形TSV通孔内寄生参数的半导体物理特性及频变特性,可用来预测锥形TSV通孔的电学特性,对优化三维集成电路电学性能有一定指导意义。     

TSV制程关键工艺设备技术及发展

论述了TSV技术发展面临的设备问题,并重点介绍了深硅刻蚀、CVD/PVD沉积、电镀铜填充、晶圆减薄、晶圆键合等几种制约我国TSV技术发展的关键设备。     

Fast thermal analysis for fixed-outline 3D floorplanning

Three dimensional integrated circuits (3D ICs) can alleviate the problem of interconnection, a critical problem in the nanoscale era, and are also promising for heterogeneous integration. However, the thermal challenge in industry is one of key obstacles to adopt the 3D ICs technology. Various thermal analysis models for 3D IC have been proposed in literature. However, the long simulation cycle makes runtime of thermal management inefficient during floorplanning phase. In this paper, we propose a fast thermal analysis method for fixed-outline 3D floorplanning. Before floorplanning, we simulate the thermal distribution of each block placed on different positions. Based on the simulated thermal profiles, bilinear interpolation is adopted to quickly estimate temperature during floorplanning. After the block planning, a heuristic method, which combines the shortest path and min-cost-max-flow, is presented for TSV allocation with minimization of chip temperature and wirelength. Compared with the superposition of thermal profiles method, the proposed thermal analysis method can reduce the peak temperature by 6.7% on average with short runtime for 3D fixed-outline floorplanning, which demonstrates the efficiency and effectiveness of the proposed thermal analysis method.     

三维集成电路中硅通孔缺陷建模及自测试/修复方法研究

硅通孔(Through Silicon Via, TSV)是3维集成电路(3D IC)进行垂直互连的关键技术,而绝缘层短路缺陷和凸点开路缺陷是TSV两种常见的失效形式。该文针对以上两种典型缺陷建立了TSV缺陷模型,研究了侧壁电阻及凸点电阻与TSV尺寸之间的关系,并提出了一种基于TSV缺陷电阻端电压的检测方法。同时,设计了一种可同时检测以上两种缺陷的自测试电路验证所提方法,该自测试电路还可以级联起来完成片内修复功能。通过分析面积开销可得,自测试/修复电路在3D IC中所占比例随CMOS/TSV工艺尺寸减小而减小,随TSV阵列规模增大而减小。     

在图像传感器和存储产品中应用硅通孔工艺的300 mm光刻与键合技术

三维集成的技术优势正在延伸到大量销售的诸如消费类电子设备潜在应用的产品领域。这些新技术也在推进着当前许多生产工艺的包封能力,其中包括光刻工艺和晶圆键合。〉还需要涂胶．形成图形和刻蚀图形结构。研究了一些用于三维封装的光刻和晶圆键合技术问题并将叙述全部的挑战和适用的解决方案。技术方面的处理结果将通过晶圆键合和光刻工序一起讨论。     

Improved transmission line model for high-frequency modelling of through silicon vias

Accurate and reliable models can support Through Silicon Via (TSV) testing methods and improve the quality of 3D ICs. A model for expressing resistance and inductance of TSVs at frequencies up to 50 GHz is proposed. It is based on the two-parallel transmission cylindrical wires model, known also as the Transmission Line Model and improved through the fitting to ANSYS Q3D simulation results. The proximity effect between neighbouring TSVs that alters the paths through which current flows is empowered at high frequencies. The consideration of the dependence of the proximity effect on frequency for calculating TSV resistance and inductance is the main contribution of this work. Additionally, the modelling of resistance is extended to accurately correspond to a TSV in an array. The proposed models are in good agreement with the simulator results with an average error below 2% and 5.4% for the resistance and the inductance, respectively. The maximum error is 3% and 9.1%, respectively. In the case of the resistance of a TSV in an array, the maximum error is 4.7%. As long as the coefficients of the proposed equations have been extracted, the time for resistance and inductance calculation based on the presented models is negligible, compared to the time-consuming EM simulation.     

RF characterization and modelling of high density Through Silicon Vias for 3D chip stacking

3D integration including Through Silicon Vias is more and more considered as the solution to overcome conventional 2D IC issues. In this way, TSV analytical equivalent models are hardly required to achieve 3D products and to make design recommendations. In this paper, a 3D process flow is detailed and used to integrate specific RF structures including copper-filled TSVs with 3 μm wide and 15 μm deep dimensions. Both measurements and simulations of these structures lead to the extraction of frequency-dependent parameters and the building of a SPICE compatible π-shaped analytical parametrical model of the TSV.     

Algorithms for TSV resource sharing and optimization in designing 3D stacked ICs

Under the current process and layer bonding technology for the TSV (through-silicon-via) based 3D ICs, it is known that the TSV resource is one of the major sources of the function failure of the chip. Furthermore, TSV takes much larger size and pitch than the normal logic components. For this reason, a careful allocation of the TSV resource has been required in 3D IC designs, and several works have been proposed to allocate minimal TSVs. This work also addresses the problem of TSV allocation and optimization, but overcomes one of the critical limitations of the previous works, which is the unawareness or no exploitation of the possibility of TSV resource sharing, previously merely resorting to a simple binding of the data transfers to TSVs. This is because the previous 3D layer partitioners have performed TSV allocation and minimization without any link to the data transfer information accessible from the high-level synthesis flow. This work proposes a set of TSV resource sharing and optimization algorithms (as a post-processing of 3D layer partitioning) by utilizing the life time information of the data transfers taken from the high-level synthesis. Specifically, we propose three algorithms for TSV resource sharing and optimization, which can be selectively applied depending on the sharing granularity and design complexity: (1) word-level TSV sharing, (2) bit-level TSV sharing, and (3) TSV refinement combined with register replication. Through experiments with benchmark designs, it is confirmed that our proposed algorithms are able to reduce the number of TSVs by 41.1% on average in word-level TSV sharing and 26.0% in bit-level TSV sharing compared with the results produced by the conventional layer partitioning with no TSV sharing while still meeting the timing constraint of designs.     

RF-TSV design, modeling and application for 3D multi-core computer systems

The state-of-the-art multi-core computer systems are based on Very Large Scale three Dimensional (3D) Integrated circuits (VLSI). In order to provide high-speed vertical data transmission in such 3D systems, efficient Through-Silicon Via (TSV) technology is critically important. In this paper, various Radio Frequency (RF) TSV designs and models are proposed. Specifically, the Cu-plug TSV with surrounding ground TSVs is used as the baseline structure. For further improvement, the dielectric coaxial and novel air-gap coaxial TSVs are introduced. Using the empirical parameters of these coaxial TSVs, the simulation results are obtained demonstrating that these coaxial RF-TSVs can provide two-order higher of cut-off frequencies than the Cu-plug TSVs. Based on these new RF-TSV technologies, we propose a novel 3D multi-core computer system as well as new architectures for manipulating the interfaces between RF and baseband circuit. Taking into consideration the scaling down of IC manufacture technologies, predictions for the performance of future generations of circuits are made. With simulation results indicating energy per bit and area per bit being reduced by 7% and 11% respectively, we can conclude that the proposed method is a worthwhile guideline for the design of future multi-core computer ICs.     

Current status of CMOS low voltage and low power wireless IC designs

This paper surveys recent research on CMOS low voltage and low power IC designs for wireless applications. Advancements and challenges in using nanometer IC processes are addressed, and the impacts of device scaling on wireless systems are discussed. Recent advances in device technologies and system architectures are presented. State-of-the-art low power wireless systems, both from academia and from industry, are summarized. Circuit design techniques and challenges for low voltage and low power applications are discussed, along with RF performance and power trade-offs. Examples of common RF building blocks, e.g. LNA's and VCO's, designed for sub-1V power supplies are presented.     

Characterization and modeling of RF substrate coupling effects in 3D integrated circuit stacking

This work addresses parasitic substrate coupling effects in 3D integrated circuits due to Through Silicon Vias (TSV). Electrical characterizations have been performed on dedicated test structures in order to extract electrical models of substrate coupling phenomena when RF signals are propagated in TSV. A good compatibility between RF measurements and RF simulations allows validating modeling tools for predictive studies. Next, parametric studies are performed in order to study impact of TSV design and materials on substrate coupling noise.     

噪声干扰对超宽带通信干扰效果分析

从通信干扰角度,基于频域分析方法,针对跳时-脉冲位置调制-超宽带（TH-PPM-UWB）体制,分析了不同噪声干扰信号对通信系统的干扰效果,并运用MATLAB仿真软件,在AWGN信道下,对不同噪声干扰信号的干扰效果进行了蒙特卡洛实验仿真,并对实验结果进行了对比分析,给出了干扰效果（误比特率）与噪声干扰信号功率、带宽和中心频率的关系。为实现对超宽带通信系统干扰的实装研制打下理论基础,具有一定的军事价值。     

一种对三维芯片中硅通孔进行完整建模与寄生参数提取的有效方法

针对三维芯片中硅通孔（through-silicon via, TSV）的准确电学建模问题,本文提出了一种电阻电容（RC）电路模型以及相应的有效参数提取技术。该电路模型同时考虑了半导体效应与静电场影响,适合于低频与中频的电路信号范围。该方法采用一种基于悬浮随机行走（floating random walk, FRW）算法的静电场电容提取技术,然后将它与刻画半导体效应的MOS电容结合,形成等效电路模型。与Synopsys公司软件Sdevice所采用的对静电场/半导体效应进行完整仿真的方法相比,本文方法计算效率更高,并且也能处理一般的TSV电路版图。对多个含TSV的结构进行了计算实验,结果验证了本文方法在从10KHz到1GHz频率范围内的建模准确性,也显示出它相比Sdevice方法最多有47倍的加速比。     

试议3D封装到来时的机遇与挑战

揭示了在摩尔定律即将失效的大背景下,电子信息产业的开发思维、生产方式将发生一系列变革;阐述了3D封装将是电子产业发展的必然趋势;反映了检测手段的提高是3D封装目前面临的主要难题。分析了我国信息电子产业在此环境下所面临的机遇和挑战。     

微镜阵列激光成像技术及其性能分析

提出了一种激光三维成像技术,该方法以推扫方式工作,采用数字微镜器件(Digital Mirror Device,DMD)来进行激光回波脉冲飞行时间(Time of Flight,TOF)的空间转换。由于目标上不同距离点回波脉冲的飞行时间不同,当脉冲到达时微透镜阵列将从一个状态转换到另一个状态,在接收端传感器焦平面上显示不同相对位置的条纹,利用条纹相对距离可以重建目标的剖面轮廓距离像。相比于其他三维成像技术,该技术具有成像速率高、探测视场角大、结构简单、体积小易于集成化等优点。