Digital sinusoidal PWMs for a micro-controller based single-phase inverter,Part 1: Principles of digital sinusoidal PWM generation

Nowadays, Digital Sinusoidal Pulse Width Modulation (DSPWM) is playing a major role in the generation of pure sinusoidal waveforms using micro-controller based inverters (Kawabata, Miyashita and Yamamoto 1991 Kawabata, T., Miyashita, T. and Yamamoto, Y. 1991. “Digital Control of Three-Phase PWM Inverter With LC Filter,”. IEEE Transactions on Power Electronics, 6: 62–72.  [Google Scholar]; Herrmann, Langer and Broeck 1993 Herrmann, U., Langer, H. G. and Broeck, H. V.D. 1993. “Low Cost DC to AC Converter for Photovoltaic Power Conversion in Residential Applications,”. 24th Annual IEEE Power Electronics Specialists Conference. 1993, Seattle, WA, USA.  [Google Scholar]; Ying-Yu 1995 Ying-Yu, T. “DSP-Based Fully Digital Control of a PWM DC-AC Converter for AC Voltage Regulation,”. 26th Annual IEEE Power Electronics Specialists Conference. Atlanta, GA.  [Google Scholar]; PICREF-1 1997 PICREF-1. 1997. Uninterruptible Power Supply Reference Design Vol. 2004. Microchip Technology [Google Scholar]; Shih-Liang, Meng-Yueh, Jin-Yi, Li-Chia and Ying-Y 1999 Shih-Liang, J., Meng-Yueh, C., Jin-Yi, J., Li-Chia, Y. and Ying-Yu, T. 1999. “Design and Implementation of an FPGA-Based Control IC for AC-Voltage Regulation,”. IEEE Transactions on Power Electronics, 14: 522–532.  [Google Scholar]; The Electrical Engineering Handbook 2000 The Electrical Engineering Handbook. 2000. , 2nd ed., New York: CRC Press LLC.  [Google Scholar]; Koutroulis, Chatzakis, Kalaitzakis and Voulgaris 2001 Koutroulis, E., Chatzakis, J., Kalaitzakis, K. and Voulgaris, N. C. 2001. “A Bidirectional, Sinusoidal, High-Frequency Inverter Design,”. IEE Proceedings-Electric Power Applications, 148: 315–321.  [Google Scholar]; Skvarenina 2002 Skvarenina, T. L. 2002. “The Power Electronics Handbook,”. In Industrial Electronics Series, Edited by: Irwin, J. D. New York: CRC.  [Google Scholar]; Pop, Chindris and Dulf 2004 Pop, O., Chindris, G. and Dulf, A. 2004. “Using DSP Technology for True Sine PWM Generators for Power Inverters,”. 27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 1: 141–146.  [Google Scholar]; Zhongyi, Mingzhu and Yan 2005 Zhongyi, H., Mingzhu, L. and Yan, X. “Core Techniques of Digital Control for UPS,”. IEEE International Conference on Industrial Technology.  [Google Scholar]). The types of DSPWM that can be generated depend on the micro-controller hardware resources and are therefore limited, but provide performance benefits not possible with an analogue controller. For instance, digital controllers offer a programmable solution and therefore more flexibility, as advanced algorithms and additional features can be added to the system in software instead of hardware (Monti, Santi, Dougal, and Riva 2003 Monti, A., Santi, E., Dougal, R. A. and Riva, M. M. 2003. “Rapid Prototyping of Digital Controls for Power Electronics,”. IEEE Transactions on Power Electronics, 18: 915–923.  [Google Scholar]; Brush 2005 Brush, L. “Trends in Digital Power Management: Power Converter and System Demand Characteristics,”. Twentieth Annual IEEE Applied Power Electronics Conference and Exposition. Austin, TX [Google Scholar]). Digital controllers are also less sensitive to environmental conditions and show precise behaviour compared with their analogue counterparts (Skvarenina 2002 Skvarenina, T. L. 2002. “The Power Electronics Handbook,”. In Industrial Electronics Series, Edited by: Irwin, J. D. New York: CRC.  [Google Scholar]). This two-part article looks at the benefits and limitations of three major DSPWMs for a single-phase full-bridge inverter and investigates their performance. In Part 1, the theory of the three major DSPWMs are presented, including mathematical models and simulation results. It looks at the PWM patterns required to generate these DSPWMs and the benefits and limitations of each. To evaluate the proposed mathematical models and simulation results, a 2kVA single-phase full-bridge inverter was developed and the DSPWMs implemented. In Part 2, experimental results from the implementation of the DSPWMs on the prototype 2kVA inverter are presented, which confirms the validity of the proposed analysis in Part 1. Moreover, the performance, including efficiency and losses (switching, conduction, and transformer) of the different DSPWMs implemented on the 2kVA inverter under different loads were examined and recommendations presented.     

Impedance calculations for modified coplanar waveguides

In view of the fact that recessed-gale FETs (Furutsuka et al, 1979 HILBERG , W. , 1969 , From approximations to exact relations for characteristic inpedances . I.E.E.E. Transactions on Microwave Theory and Techniques , 17 , 259 – 265 . [Google Scholar]) can sustain higher breakdown voltages and hence more power than conventional FETs, it is important to design new microwave transmission lines compatible with recessed-gate FETs on GaAs monolithic integrated circuits (MICs). Structures and impedances of three modified coplanar waveguides (CPWs) are presented here: (1) a finite-thickness CPW with a third ground plane for improved heat-sinking, (2) an abrupt-recessed strip CPW, and (3) a graded-recessed strip CPW. All of the above CPWs are structured to fit the recessed-gate FETs on MICs. The gap dimensions of the structures are assumed to be sufficiently small so that conformal mapping techniques suitable for a quasi-static mode can be applied.     

An adaptive pulse-width control loop

Clock distribution and generation circuitry forms a critical component of current synchronous digital systems. Digital system clocks must not only have low jitter and low skew, but also a well-controlled duty cycle in order to facilitate versatile clocking techniques. In high-speed complementary metal oxide semiconductor (CMOS) clock buffer design, the duty cycle of a clock is liable to be changed when the clock passes through a multistage buffer because the circuit is not pure digital (Fenghao and Svensson 2000 Fenghao, M and Svensson, C. 2000. Pulsewidth control loop in high-speed CMOS clock buffers. IEEE Journal of Solid-State Circuits, 35: 134–141.  [Google Scholar]). In this paper, we propose a pulsewidth control loop referred as adaptive pulsewidth control loop (APWCL) that adopts the same architecture as the conventional PWCL, but with two modifications. The first one relates to implementation of the pseudo inverter control stage (PICS), while the second to involvement of adaptive control loop. The first modification provides generation of output pulses during all APWCL's modes of operation and the second faster locking time. For 1.2?μm double-metal double-poly CMOS process with V_dd ?=?5?V and operating frequency of 100?MHz, results of SPICE simulation show that the duty cycle can be well controlled in the range from 20% up to 80% if the loop parameters are properly chosen.     

Minmax-concave total variation denoising

Total variation (TV) denoising is a commonly used method for recovering 1-D signal or 2-D image from additive white Gaussian noise observation. In this paper, we define the Moreau enhanced function of \(L_1\) norm as \({\varPhi }_\alpha (x)\) and introduce the minmax-concave TV (MCTV) in the form of \({\varPhi }_\alpha (Dx)\), where D is the finite difference operator. We present that MCTV approaches \(\Vert Dx\Vert _0\) if the non-convexity parameter \(\alpha \) is chosen properly and apply it to denoising problem. MCTV can strongly induce the signal sparsity in gradient domain, and moreover, its form allows us to develop corresponding fast optimization algorithms. We also prove that although this regularization term is non-convex, the cost function can maintain convexity by specifying \(\alpha \) in a proper range. Experimental results demonstrate the effectiveness of MCTV for both 1-D signal and 2-D image denoising.     

Improved Q-Factor Calculations for Single Port Filter-Antenna Measurement

These days most of the research work in the area of filter-antenna design is focused on having high quality factor for certain frequency band. These type of filter-antennas are difficult to design as the design engineers are required to have low quality factor for the radiating band of frequency. Hence a precise value of $Q$ -factor is required to understand the radiating and filtering properties of filter-antennas. Filter-antennas are single port devices as the second port is considered as radiating port. Return loss is used, in order to yield $Q$ -factor through calculations for such devices. However, the conventional method for calculating $Q$ -factor found to be inaccurate in most of the low $Q$ -factor cases. This paper proposes a method that out performs the conventional method of calculating $Q$ -factor. Non-ideal fabrication process is also discussed for accurate evaluation of $Q$ -factor. Experimental results show that proposed method can be employed to calculate $Q$ -factor with reasonable accuracy for simulated and measured results.     

On estimation of the power density spectrum with particular reference to a non stationary phenomenon

Results of measurement of the Power Density Spectrum (Pds)of the cable impedance profile (reflection density function) are reported. Spectral analysis techniques using the modified periodogram method (Mpm)and the maximum entropy method (Mem)have been used to obtain estimates of the relevant Pds from the measured data. The results of the two methods are compared. Resolution, bias and stability are examined. The results indicate that the resolution and stability obtainable using Mem are superior but with short records there is evidence of loss of detail.     

A High Gain,Low-Power Low-Noise Amplifier for Ultra-Wideband Wireless Systems

This paper presents a high gain, low-power common-gate ultra-wideband low-noise amplifier employing a simple configuration for wideband input matching. In our design, a series resistance-inductance network at the source combines with the parasitic capacitance of a transistor to form a parallel RLC input matching configuration in the common-gate input stage. Because of the additional resistance, this matching configuration partially alleviates the restriction of transconductance of the input transistor and also provides wideband matching. The low-noise amplifier was fabricated using the TSMC 0.18  \(\mu \) m technology with an average noise figure of 3.75 dB, a power gain of 18.68 dB with a ripple of \(\pm \)  0.8 dB, an input return loss less than \(-10\)  dB from 3 to 7.6 GHz, and DC power consumption of 8.56 mW, including the output buffer with a 1.8 V supply voltage.     

Quantized IR properties reconfirmed in the CO and SiO surface oscillators present in the surface layer of A bamboo stem

From analysis of diffusion diagrams of CO stretching band (2500～2180 cm^?1), bending band (800～200 cm^?1) and SiO stretching band (1100～700 cm^?1) measured in a skin surface layer of a bamboo stem (silicate cellulose), azimuthal directions where oscillators oriented were shown as (?'=?-90) ?_N=a·N-b, with a=28.3, 2×28, 22.7, b=25, 47.5, 10. And N=1,2.....14, N=1, .....6. N=1,2.....16. The optical activity (reflection integral) was shown for the CO stret. band as M_i(N)=a·N+b, with a=21.8, b=42 and N =1,2.....9. And for the bending band as M_i(N)=a·N² +b·N?c, with a=1.87×10¹, b=3.73×10³, c=7.06×10² with N=1,2.....9. Six stepnized fine series in CO weak reflection bands were confirmed as, \(\bar v = A \cdot N^2 + B \cdot N + C (cm^{ - 1} )\) and \(\bar v_{C - 1} = A \cdot N^{1/2} + B (cm^{ - 1} )\) with N=1,2.....22. Mean values of the vibrational quantized states of the A, B and C-series in the SiO stretching weak band with R?1.0% were shown as, \(\overline {\Delta E} _m = 4.54 \times \bar v_{\text{m}}^{\text{2}} - 1.449 \times \bar v_m + 1.27 \times 10^7 \) (meV) with \(\bar v = E/hc\) .     

Efficient Reverse Converters for 4-Moduli Sets {2^{2n-1}-1, 2^{n}, 2^{n}+1, 2^{n}-1} and {2^{2n-1}, 2^{2n-1}-1, 2^{n}+1, 2^{n}-1} Based on CRTs Algorithm

Speed and complexity of a reverse converter are two important factors that affect the performance of a residue number system. In this paper, two efficient reverse converters are proposed for the 4-moduli sets {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } and {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } with 5 \(n\) -bit and 6 \(n\) -bit dynamic range, respectively. The proposed reverse converter for moduli set {2 \(^{2n-1}-1\) , 2 \(^{n}\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed based on CRT and New CRT-I algorithms and in two-level structure. Also, an efficient reverse converter for moduli set {2 \(^{2n-1}\) , 2 \(^{2n-1}-1\) , 2 \(^{n}+1\) , 2 \(^{n}-1\) } has been designed by applying New CRT-I algorithm. The proposed reverse converters are based on adders and hence can be simply implemented by VLSI circuit technology. The proposed reverse converters offer less delay and hardware cost when compared with the recently introduced reverse converters for the moduli sets {2 \(^{n}+1\) , 2 \(^{n}-1\) ,2 \(^{n}\) , 2 \(^{2n+1}-1\) } and {2 \(^{n}+1\) , 2 \(^{n}-1\) , 2 \(^{2n}\) , 2 \(^{2n+1}-1\) }.     

Transverse Thermoelectricity in a Tilted Metallic Multilayer Structure

Thermoelectricity is investigated in a material designed to show anisotropic transport properties: Copper/constantan/copper $ \cdot \cdot \cdot $ multilayer structures were prepared by sintering of a compressed stack of alternating foils of these materials and are described by effective “in-plane” properties $S_\parallel $ and $k_\parallel $ for the Seebeck-coefficient and the thermal conductivity along the layers, and “out-of-plane”-properties $S_ \bot $ and $k_ \bot $ along the stack axis. Samples in form of thin slabs prepared by cutting the stack obliquely to the stack axis showed thermoelectric fields transverse to temperature gradients across the slab due to off-diagonal elements in the Seebeck-tensor, and may be used as devices for detection of laser radiation.     

Algorithms for bounding end-to-end delays in Wireless Sensor Networks

Wireless Sensor Networks (WSNs) have many characteristics that are attractive to a myriad of applications. In particular, nodes employ multi-hop communications to collaboratively forward sensed data back to one or more sinks. In this context, reducing the end-to-end delay between the sink and sensor/source nodes is of interest to many applications. In particular, those that require a fixed, upper bound on end-to-end delays. To this end, we focus on bounding the end-to-end delay from the sink to each source. We first formulate the problem as a Binary Integer Program (BIP). As the problem is NP-hard, this paper proposes and studies two centralized, heuristic algorithms: Tabu and Domino. The key approach used by both algorithms is to determine the minimal number of extra wake-up slots required by a given network in order to ensure the delay of all end-to-end paths is within a given bound. We conducted two sets of experiments. The first set compares BIP, Tabu, and Domino in WSNs with up to 80 nodes. These experiments serve to compare the proposed algorithms against BIP, which become computationally expensive in large scale WSNs. The results show that, compared to BIP, the number of additional wake-up times generated by Tabu and Domino are within 5 and 10 % of the optimal solution. In the second set of experiments, which evaluates the algorithms in WSNs with 100–500 nodes, the average number of extra wake-up slots activated by Domino is 13 % greater than Tabu. These algorithms have a time complexity of \({\mathcal {O}} (\alpha n^2 T + n^3)\) and \({\mathcal {O}}(n^3)\) respectively, where \(n\) is the number of nodes, \(T\) is the number of slots in one period, and \(\alpha\) is the maximum number of iterations carried out by the Tabu algorithm.     

Diagnosis of Wireless Sensor Networks in Presence of Permanent and Intermittent Faults

In this paper we consider the problem of distributed fault diagnosis in Wireless Sensor Networks (WSNs). The proposed Fault Diagnosis Algorithm (FDA) aims to handle both permanent and intermittent faults. The sensor nodes with permanent communication faults can be diagnosed by using the conventional time-out mechanism. In contrast, it is difficult to detect intermittent faults due to their inherent unpredictable behavior. The FDA is based on the comparison of sensor measurements and residual energy values of neighboring sensor nodes, exploiting their spatial correlations. To handle intermittent faults, the comparisons are made for \(r\) rounds. Two special cases of intermittent faults are considered: one, when an intermittently faulty node sends similar sensor measurement and similar residual energy value to some of its neighbors in all \(r\) rounds; another, when it sends these values, either or both of which deviates significantly from that of some neighbors in all \(r\) rounds. Through extensive simulation and analysis, the proposed scheme is proved to be correct, complete, and efficient to handle intermittent faults and hence, well suited for WSNs.     

Optimal Location of Energy Efficient DF Relay Node in $$\varvec{\kappa}$$ κ – $$\varvec{\mu }$$ μ Fading Channel

We investigate the optimal location of an adaptive decode and forward relay operating over a \(\kappa\)–\(\mu\) fading channel. The \(\kappa\)–\(\mu\) statistics provides a generalized line-of-sight propagation model which includes fading models like Rayleigh, Nakagami, Rician as special cases. We restrict our analysis to collinear relay placement, i.e. the relay node \((R_n)\) is on the same straight line between the source node \((S_n)\) and the destination node \((D_n)\). In the non-cooperative mode, \(D_n\) accepts only the two-hop transmission via \(R_n\) and discards any direct signal that may be available from \(S_n\). On the other hand, in the cooperative mode, \(D_n\) accepts both the replicas and combine them following either selection combining (SC) or maximum ratio combining (MRC). It is interesting to see that such cooperation does not always lead to energy saving, especially for small \(S_n-D_n\) separation. Also, worth mentioning the fact that MRC may not be optimal from the energy efficiency perspective, and SC can outperform MRC under certain channel conditions. In our paper, we also studied how parameters like spectral efficiency (R), path loss exponent (n), and fading parameters (\(\kappa ,\mu\)) affect the optimal relay placement location.

     

E-TCAM: An Efficient SRAM-Based Architecture for TCAM

Ternary content addressable memories (TCAMs) perform high-speed search operation in a deterministic time. However, when compared with static random access memories (SRAMs), TCAMs suffer from certain limitations such as low-storage density, relatively slow access time, low scalability, complex circuitry, and higher cost. One fundamental question is that can we utilize SRAM to combine it with additional logic to achieve the TCAM functionality? This paper proposes an efficient memory architecture, called E-TCAM, which emulates the TCAM functionality with SRAM. E-TCAM logically divides the classical TCAM table along columns and rows into hybrid TCAM subtables and then maps them to their corresponding memory blocks. During search operation, the memory blocks are accessed by their corresponding subwords of the input word and a match address is produced. An example design of \(512\times 36\) of E-TCAM has been successfully implemented on Xilinx Virtex- \(5\) , Virtex- \(6\) , and Virtex- \(7\) field-programmable gate arrays (FPGAs). FPGA implementation results show that E-TCAM obtains \(33.33\)  % reduction in block-RAMs, \(71.07\)  % in slice registers, \(77.16\)  % in lookup tables, \(53.54\)  % in energy/bit/search, and offers \(63.03\)  % improvement in speed, compared with the best available SRAM-based TCAM designs.     

δ-Bit serial binary addition with linear threshold networks

In this paper we investigate δ-bit serial addition in the context of feed-forward linear threshold gate based networks. We show that twon-bit operands can be added in $2\left\lceil {\sqrt n } \right\rceil $ overall delay with a feed-forward network constructed with $\left\lceil {\sqrt n } \right\rceil + 1$ linear threshold gates and $\frac{1}{2}\left( {5\left\lceil {\sqrt n } \right\rceil ^2 + 9\left\lceil {\sqrt n } \right\rceil } \right) + 2$ latches. The maximum weight value is $2^{\left\lceil {\sqrt n } \right\rceil } $ and the maximum fan-in is $3\left\lceil {\sqrt n } \right\rceil + 1$ . We also investigate the implications our scheme have to the performance and the cost under small weights and small fan-in requirements. We deduce that if the weight values are to be limited by a constantW, twon-bit operands can be added in $\left[ {\log W} \right] + \tfrac{n}{{\left[ {\log W} \right]}}$ overall delay with a feed-forward network that has the implementation cost [logW]+1, in terms of linear threshold gates, $\tfrac{1}{2}(5[\log W]^2 + 9[\log W]) + 2$ in terms of latches and a maximum fan-in of 3[logW]+1. We also prove that, if the fan-in values are to be limited by a constantF+1, twon-bit operands can be added in $[\tfrac{F}{3}] + \tfrac{n}{{[\tfrac{F}{3}]}}$ overall delay with a feed-forward network that has the implementation cost $[\tfrac{F}{3}] + 1$ , in terms of linear threshold gates, $\tfrac{1}{2}(5[\tfrac{F}{3}]^2 + 9[\tfrac{F}{3}]) + 2$ in terms of latches, and a maximum weight value of $2^{[\tfrac{F}{3}]} $ . An asymptotic bound of $O(\tfrac{n}{{\log n}})$ is derived for the addition overall delay in the case that the weight values have to be linearly bounded, i.e., in the order ofO(n). The implementation cost in this case is in the order ofO(logn), in terms of linear threshold gates, and in the order ofO(log² n), in terms of latches. The maximum fan-in is in the order ofO(logn). Finally, a partition technique, that substantially reduces the overall cost of the implementation for all the schemes in terms of delay, latches, weights, and fan-in with some few additional threshold gates, is also presented.     

A 5 GHZ CMOS Power VCO with Novel Frequency-Modulation for RF Transmitter

A 5 GHz transformer-feedback power oscillator with novel frequency modulation (FM) up to 10 MHz is presented in this paper. The novel FM is achieved by a CMOS transistor between transformer and ground, which is designed for varying the equivalent inductance and mutual inductance of the transformer and shows no DC connection with the oscillation circuit. The major frequency tuning is realized by the variable capacitor which is controlled by a phase lock loop. The RF VCO with 210 MHz tuning range operates in class-E mode to achieve a cost-effective transmitter, which demonstrates a high DC-to-RF conversion efficiency of 39 %. A RF power of 15.1 dBm and phase noise better than \(-\) 109 dBc/Hz @ 100 kHz from the central frequency of 5.5 GHz is obtained with the biasing conditions V \(_\mathrm{ds}\) = 1.8 V and V \(_\mathrm{gs}\) = 0.65 V. The VCO also demonstrates an ultra-low voltage operation capability: with V \(_\mathrm{ds}\) = V \(_\mathrm{gs}\) = 0.6 V and DC power consumption of 9 mW, the output power is 4.5 dBm and the phase noise better than \(-\) 93 dBc/Hz @ 100 kHz. The die size of the transformer-feedback power oscillator is only \(0.4\times 0.6\) mm \(^{2}\) .