ASIC design of a high speed low power circuit for factorial calculation using ancient Vedic mathematics

ASIC design of a high speed low power circuit for factorial calculation of a number is reported in this paper. The factorial of a number can be calculated using iterative multiplication by incrementing or decrementing process and iterative multiplication can be computed through parallel implementation methodology. Parallel implementation along with Vedic multiplication methodology for calculation of factorial of a number ensures significant reduction in propagation delay and switching power consumption due to reduction of stages in multiplication process, in comparison with the conventionally used Vedic multiplication methodologies like ‘Urdhva-tiryakbyham’ (UT) and ‘Nikhilam Navatascaramam Dasatah’ (NND) based implementation methodology. Transistor level implementation was carried out using spice specter with standard 90 nm CMOS technology and the results were compared with the above mentioned conventional methodologies. The propagation delay for the calculation of 4-bit factorial of a number was only ∼42.13 ns while the power consumption of the same was ∼58.82 mW for a layout area of ∼6 mm². Improvement in speed was found to be ∼33% and ∼24% while corresponding reduction of power consumption in ∼34.48% and ∼24% for the factorial calculation circuitry in comparison with UT and NND based implementations, respectively.     

基于可编程逻辑器件的LED显示屏控制系统设计

针对利用单片机设计LED显示屏控制系统中所存在的问题,提出了基于可编程逻辑器件设计和实现的大屏幕LED显示系统,并用串并结合的方案取代以往控制器和显示屏之间串行的数据传输方式。此外,增加光频转换器TSL235,根据环境变化实时调整显示亮度。该系统具有刷新速度快、亮度高、灵活配置、功耗低等特点,外接16 MHz时钟,显示屏能够清晰地显示汉字。     

单板匿影模块的实现

介绍了采用在系统可编程器件完成单板匿影模块的设计,并给出了主要电路的超高速集成电路硬件描述语言（VHDL）,提供了实现匿影电路的模块化、单板的方法。     

面向复杂数字系统的乘法器教学设计

分析和研究了面向复杂数字系统设计的乘法器教学设计问题。课程以二进制乘法为基础,强调乘法器原理在课程中核心地位,通过分析实例与计算过程,逐步过渡到有符号定点数乘法器设计;以复杂数字系统设计为应用目标,设计有限冲击响应滤波器设计实验;教学实践表明,乘法器教学改革有助于提高学生的核心竞争力,在新工科背景下,培养学生实践中解决问题的能力和创新精神。     

基于VHDL语言实现FPGA设计

介绍采用VHDL语言在现场可编程门阵列器件(FPGA)上实现通用芯片8255的设计,并简要介绍8255的结构,给出VHDL语言设计程序。     

可编程并行接口电路设计与分析

采用自顶向下的设计方法,用原理图和硬件描述语言这2种输入对并行通信接口芯片进行设计分析并行通信接口的基本功能实现的关键点以及解决的方法．在MAXPLUSII编译环境下综合．得到比较理想的仿真结果．     

基于VHDL的数字逻辑电路设计

分析了硬件描述语言VHDL的特点、结构和描述;说明了基于VHDL进行数字逻辑电路设计的方法;结合实例介绍了VHDL在数字逻辑电路设计中的应用方法。     

基于FPGA的中高频感应电炉控制电路设计方案

中高频电炉是利用电磁感应原理加热和溶化金属的。提出一种优化系统控制电路的方案,基于Altera FPGA可编程器件,利用VerilogHDL语言实现对可控硅的整流脉冲、逆变脉冲以及工作振荡频率的跟踪和系统保护控制的模块化,将其集成到片上,形成片上控制系统,从而提高整个控制系统的可靠性、稳定性和抗干扰性。     

Design and implementation of high-speed real-time data acquisition system based on FPGA

1 Introduction Electromagnetic radiation will be generated when an electric device, especially video display unit, works, and can give rise to electromagnetic leakage. When the electromagnetic leakage is recognized, the available information can be recove…     

Design and analysis of a compact fast parallel multiplier for high speed DSP applications using novel partial product generator and 4 : 2 compressor

Parallel multiplier is one of the most important building blocks in all the DSP processors, which needs faster computations. To reduce the total transistor count in a multiplier we have proposed two new approaches. The first approach is using a 26 transistor booth encoder and a 8-transistor/partial-product booth selector to generate partial products. The second approach proposes a new circuit for 4 : 2 compressors. The booth encoder and booth selector reported here are the smallest in transistor count, but comparable to the best delay with less power consumption. This paper describes a comparison of a compact 16 × 16 parallel multiplier using the new circuit components. This shows a transistor count advantage of 27% and 52% in partial product generation and partial product accumulation, respectively.     

基于FPGA的SRRC数字滤波器设计与实现

随着数字技术的不断发展,数字滤波在数字信号处理领域占据不可替代的地位。文章首先介绍了数字滤波器的理论,DSP器件在高速和实时系统中的应用有一定局限性的问题提出了基于FPGA消除基带传输系统码间干扰的实现方案。该方案设计了一个33阶的具有对称转置结构的平方根升余弦滚降(SRRC)滤波器。首先通过MATLAB对滤波器系数进行了提取,并对浮点型系数进行量化和CSD编码形成定点型系数,使之能够在FPGA中运行。利用硬件描述语言Verilog对所设计的滤波器各功能模块进行设计。最后釆用仿真综合软件Modelsim和Quartus II对顶层模块进行综合与仿真。仿真后得到的滤波后数据波形图与Matlab下理论性的滤波后数据波形图基本相吻合,证明了所设计的SRRC数字滤波器功能完全正确。     

Parametrized and reusable VLSI macro cells for the low-power realization of 2-D discrete-cosine-transform

The problem of an efficient VLSI realization of the 2-D discrete-cosine-transform and its inverse is addressed in this paper. Two circuits implementing both functions are discussed and characterized from the high-level architectural choices down to the gate-level synthesis on different standard-cell target technologies. The circuits are designed as parametric intellectual property (IP) cells according to a design reuse policy that allows the user to select the most convenient solution for the considered application. Synthesis results show that the circuits are suitable for real time processing of various image formats adopted in H.263/MPEG compression standards. Power consumption reduction methods (clock gating, switching activity reduction) are used according to the statistics of the input signals to reduce the dissipated power. The effects of supply voltage scaling and its consequence on circuit performance are examined in detail, as well as the use of different target technologies. Finally, a comparison with dedicated full-custom low-power circuits presented in the literature show that these IP cells stand for flexibility, parametrization and reusability, still maintaining comparable power consumption and area occupation.