High-performance photonic analogue-digital converter

The authors demonstrate a photonic analogue-digital converter architecture based on temporal-spectral mapping. Linearly chirped optical pulses form a quasi-continuous carrier modulated by the analogue RF signal. The signal is separated into several distinct wavelength channels for parallel demodulation and quantisation. Measurements performed on 70 ps electrical signals indicate six bit resolution     

A new architecture for non-linear analogue-digital conversion

A modified architecture is proposed for the non-linear analogue-digital conversion of a transducer response. It is proved that by making use of a dual-slope A/D converter and by changing the clock frequency fed to the A/D converter during the deintegration period and blocking some of the pulses during this period, a nonlinear A/D conversion can be achieved. This method was used to linearize a Pt-PtRh thermocouple response and excellent results were obtained. Further, it is proved that the frequency change depends only on the maximum slope of the transducer response that is to be corrected.     

Novel low-voltage folder for analogue-to-digital converter

A novel architecture of low-voltage folder is presented for folding analogue-to-digital (A/D) converter applications. With MOS transistors completely replacing the resistor load used in the conventional folder, this circuit has a good power-supply–rejection-ratio (PSRR) 21.2?dB for the output common voltage and can work well even under a very low power supply 1.0?V. A moderately high gain 14.5?dB and a wide input bandwidth 506?MHz are obtained. The circuit dissipates only 1.2?mW from 1.2?V power supply. The performance is verified by Hspice-Avanti-99.4 simulations on 0.18?µm digital CMOS technology.     

30 Gsample/s time-stretch analogue-to-digital converter

High speed analogue-to-digital conversion using a photonic time-stretch preprocessor followed by an electronic digitiser is demonstrated. The preprocessing increases the effective sampling rate and input bandwidth of the digitiser. The system exhibits 30 Gsample/s sampling rate with 26 dB signal-to-noise ratio over a 4 GHz bandwidth     

A variability tolerant system-on-chip ready nano-CMOS analogue-to-digital converter

As integrated circuit technologies progress to nanoscale, process variations become relatively large and significantly impact circuit performance. The proactive management of process variation during the design process is critical to ensure effective device yield and to keep manufacturing costs down. In the present scenario, designers are searching for analogue-to-digital converter (ADC) architectures which are nanoscale CMOS processes tolerant. Expectations of the performance of ADCs are continuously increasing along with the progress of digital systems. A process and supply variation tolerant, System-on-Chip (SoC) ready, 1 GS/s, 6-bit flash ADC suitable for integration into nanoscale digital CMOS technologies is presented. The physical design of the ADC has been done using a generic 90 nm Salicide 1.2 V/2.5 V 1 Poly 9 Metal process design kit. Baseline post layout simulation results at nominal supply and threshold voltages are presented. The parasitic-extracted physical design of the ADC is then subjected to a corner-based methodology of process variation. The results show that process variation causes a maximum variation of 10.5% in the integral non-linearity (INL) and 5.7% in the differential non-linearity (DNL), with both INL and DNL being less than 0.5 LSB. The 90 nm ADC consumes a peak power of 5.794 mW and an average power of 3.875 mW. The comparators for the ADC have been designed using the threshold inverting technique. To show technology scalability of the design, the ADC has also been presented using a 45 nm Predictive Technology Models (PTM). At 45 nm, INL = 0.46 LSB, DNL = 0.7 LSB and a sampling rate of 100 MS/s were obtained. The 45 nm ADC consumes a peak power of 45.42 μW, and average power of 8.8 μW.     

Enhanced input range dynamic comparator for pipeline analogue-to-digital converter

A new dynamic comparator with enhanced input range is reported. Input trip point deviations from ideal values are shown to be less than a conventional comparator over a wide input range. This new dynamic comparator can be beneficial to low supply voltage analogue- to-digital converters (ADCs), especially to pipeline ADCs.     

用自校正方法设计的对数I/V转换器

提出了一种光电流对数压缩I/V转换器设计。该电路能将蓝硅SPD输出的0．1～100μA范围光电流转换成0-3V的模拟电压输出，方便地实现了与MCU的连接。电路核心是制作在同一硅片上两个性能对称的对数放大器，其中之一是自校正参考电路，它的状态由带隙基准源设定。通过对称电路输出的除法运算就消除了温度影响，进而大大提高了温度稳定性，使温度在-20-50℃时，光电流从0．1～100μA的转换误差达1％。     

Combined radix<2 and 1.5 bit/stage pipelined analogue-to-digital converter

A new pipeline architecture that combines the radix<2 and traditional 1.5 bit gain-stages is presented. The 10 bit, 60 MHz, 3 V pipelined analogue-to-digital converter has been designed in a 0.25 /spl mu/m 1p4M CMOS technology using digital self-calibration. The converter achieves more than 57 dB SNDR from a 3 V supply (10% lower than nominal 3.3 V) within -40 to +120/spl deg/C temperature range.     

13 Gsamples/s 5-bit analogue-to-digital converter for coherent optical QPSK receiver

An implementation of an analogue-to-digital converter to be used in a digital coherent QPSK receiver is presented. The converter is manufactured in a SiGe BiCMOS technology and features a resolution of 5 bits with sampling rates >13 Gsamples/s, and dissipates 4.2 W of power.     

Logarithmic data converter suitable for hearing aid applications

A novel method for analogue-to-digital conversion with compressive /spl mu/-law transfer characteristic, suitable for hearing aid applications, is presented. The proposed method can be realised as low-power tunable analogue-to-digital converters in both pipeline and algorithmic architectures and is integratable in CMOS technology.     

具有非线性电压转换有源箝位正激变换器

本文研究一种具有非线性电压转换的正激变换器,通过在有源箝位正激变换器的变压器二次侧增加一个续流二极管和一个输出滤波电感得到。该变换器保留了有源箝位正激变换器的优点,同时,具有更高的占空比利用率,使得其具有宽输入电压适应范围,软开关的实现和二极管电压电流应力的减小,使其功率转换效率进一步提高。研制了一台50~100V输入, 12V输出的原理样机,实验结果验证了理论分析的正确性以及该技术的可行性。     

Design of a power-factor-correction converter based on half-bridgetopology

A single-stage AC/DC converter based on a half-bridge topology suitable for low-power-level applications is proposed. The proposed converter has high power factor, low harmonic distortion, and tight output regulations. An asymmetrical control and synchronous rectification are employed to reduce the switching and rectification losses, respectively. The modeling and detailed analysis are performed to derive the design equations. Based on these design equations, a prototype converter has been designed and tested by experiment. This prototype meets the IEC 61000-3-2 regulations with near-unity power factor and high efficiency     

基于广义对数函数的统一路由策略

通过对最短路径路由策略、有效路由策略、最小信息路径路由策略的算法以及广义对数函数进行研究发现：将广义对数函数内的变量进行部分修改可实现以上三种算法的统一,并且通过对此种统一算法进行改进并且仿真发现,在此统一算法变量连续变化的同时,某些路由策略在复杂网络中的表现同样具有连续性。这表明此种算法可以将以上三种路由策略进行完美的统一。     

真对数放大器SBM064在雷达中频接收机中的应用

SBM064是中电24所生产的真对数放大器.它有20 MHz～30 MHz的输入带宽,开环电压增益大于90dB,输入电压为3μV～90mV,输出电压为10 mV～350 mV,对数精度小于1dB.其具有体积小、功耗低、精度高的特点.文中介绍了SBM064的主要特点以及典型应用电路,在此基础上,给出了一个SBM064在雷...     

基于自激推挽式小型化二次电源的设计

介绍了自激推挽式DC-DC变换器的基本工作原理,给出了实际工作的自激推挽式二次电源的实用电路及主要单元电路的设计方法,利用单变压器设计出＋10V和-10V两路输出的二次电源,在设计中通过选择电流反馈型电路,消减了开关管导通和关断时出现的电流尖峰,通过用MOSFET代替晶体管避免磁通不平衡。最后对电路进行了实验测试,验证了二次电源的稳定性和可靠性,实现了数模混合电路系统供电电路的小型化.     

一种基于CAN总线的高精度角度变送器

针对工业控制系统中对角度位置量高精度、实时性强的测量需求,提出了一种基于CAN总线的高精度角度变送器的设计与实现。以C8051F504型单片机作为处理核心,重点阐述了旋转变压器-数字转换系统模型的构建,并确定了校正参数;利用单片机内部集成的CAN控制器,设计了CAN总线接口电路,详细介绍了器件选型和电路设计的创新点。测试结果表明,设计的角度变送器精度指标高达1.7′,可靠性和实时性强,具有广泛的应用前景。     

Reconfigurable digital controller for a buck converter based on FPGA

This paper presents a complete digitally controlled dc–dc buck converter performed by FPGA circuitry. All tasks, analog to digital conversion, control algorithm and pulse width modulation, were implemented in the FPGA. This approach enables high-speed dynamic response and programmability by the controller, without external passive components. In addition, the controller’s structure can be easily changed without external components. The applied algorithm enables a switching frequency of 100 kHz.     

A direct AC/AC converter based on current-source converter modules

The research on direct AC/AC conversion in the past twenty years has been following two major directions: improving the performance of the original nine-bidirectional-switch matrix converter topology; and using converter topologies composed of unidirectional switches only. In this paper, a direct AC/AC converter topology based on current-source converter modules is proposed. It is shown, through analysis and simulation, that the proposed topology is free of any switching difficulties and gives high-quality sinusoidal waveforms on both sides. Furthermore, with the same number of semiconductor devices as in the original nine-bidirectional-switch matrix converter topology, it is able to perform all aspects of frequency changing, real power flow control, and independent reactive power flow control on both sides. The proposed topology finds applications in electric drive industry, as an AC motor drive, and power system industry, as an asynchronous link.     

一种低功耗多谐振荡式电压频率转换器设计

提出一种新型的低功耗多谐振荡式电压频率转换器电路的设计,采用0.18μm CMOS工艺制程,拥有较大的输入电压范围,根据CSMC 0.18μm工艺参数,在Spectre上仿真。结果表明,该电路在0~1.6 V的输入电压下输出0~2.0 MHz的频率信号,灵敏度1.25 MHz/V,输出频率相对误差小于6.8%,电路的最大功耗0.23 m W。得到预期的设计结果。