A novel scheme to suppress the third-order intermodulation distortion based on dual-parallel Mach–Zehnder modulator

A scheme to enlarge the spurious free dynamic range (SFDR) of the microwave photonic link is proposed based on a dual-parallel Mach–Zehnder modulator (DPMZM). By properly adjusting the phase of the RF signals and the bias voltages of the DPMZM, the second-order spurious components in the optical carrier band (OCB) of the two sub-MZMs can be canceled out completely, and the third-order and fifth-order spurious components in the first-order upper sideband (1-USB) produced by one sub-MZM have equal amplitude but \(180{^{\circ }}\) phase difference with the other sub-MZM. Therefore, as the two optical beams are combined at the output of the DPMZM and the OCB and the 1-USB are abstracted by a bandpass filter to generate the transmitted signal, all the major optical spurious components that contribute to the third-order intermodulation distortion (IMD3) are canceled out. Theoretical analysis and simulation results show that the proposed scheme, without digital linearization and other optical processor, can suppress IMD3 approximately 30 dB and improve the SFDR by \(18~\hbox {dB}\,\hbox {Hz}^{2/3}\) compared with the conventional quadrature biased MZM system.     

A low power tunable Gm–C filter based on double CMOS inverters in 0.35?μm

In this article, an inverter based transconductor using double CMOS pair is proposed for implementation of a second order lowpass G_m?CC Filter. The proposed operational transconductance amplifier (OTA) and biquad filter are designed using standard 0.35???m CMOS technology. Simulation results demonstrate the central frequency tunability from 10?kHz to 2.8?MHz which is suitable for the wireless specifications of Bluetooth (650?kHz), CDMA 2000 (700?kHz) and Wideband CDMA (2.2?MHz) applications. The power consumption of the filter is 445?nW and 178???W at 10?kHz and 2.8?MHz from 3.3?V supply voltage, respectively. The active area occupied by the designed filter on the silicon is 215?×?720???m². The proposed approach guarantees the upper bound on THD to be ?40?dB for 300?mVpp signal swing. Employing the double CMOS pair in the inverters causes PSRR to reach 68.6?dB which is higher than similar works.     

A one-path subsampling quadrature receiver based on a ΣΔ modulator with distributed resonators

This article presents experimental results of a quadrature bandpass sigma–delta (ΣΔ) modulator based on distributed resonators. The modulator employs transmission lines and transconductors as main components and does not require switches in the loop filter as in the case of switched-capacitor (discrete-time) filters. In addition, the proposed complex modulator does not require a quadrature mixer in the receiver. As main feature, the modulator architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The one-bit second-order modulator ADC is able to convert IF signals at fs/2 and 3fs/2 (fs = 50 MHz), achieving an ENOB = 10 bits within a 1 MHz signal bandwidth. Therefore the modulator may be feasible for the typical IF frequencies used in cellular base stations. Furthermore, it provides an image rejection grater than 70 dB. The 0.35 μm BiCMOS chip consumes 28 mW at 3.3 V supply voltage.     

A 2.7–6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2

Frequency multiplication by 3/2 is proposed as a means to expand the frequency generation capabilities of a single LC VCO. Fractional frequency multiplication is obtained by cascading a broadband injection locked modulo-two divider and a multiply-by-three circuit based on edge combining. The proposed solution is inductorless, thus very compact. It allows the generation of all frequencies from 2.7 to 6.1 GHz with a performance suitable for cellular standards. It shows a phase noise floor below ?150 dBc/Hz and a spurious level below ?35 dBc. The multiplier by 3/2 consumes 5 mA and the VCO draws 10 mA from a 1.2 V supply. The additional power consumption due to the multiplier trades with the small area penalty and the flexibility of this solution, compared to the use of multiple LC VCOs.     

A new focus evaluation operator based on max–min filter and its application in high quality multi-focus image fusion

Multidimensional Systems and Signal Processing - Multi-focus image fusion plays an important role in the field of image recognition and analysis. However, current focus evaluation...     

Delay-aware reliable broadcast scheme based on power control for VANETs简

In vehicular Ad-hoc network（VANET）, many multi-hop broadcast schemes are employed to widely propagate the warning messages among vehicles and the key is to dynamically determine the optimal relay vehicle for retransmission. In order to achieve reliable and fast delivery of warning messages, this paper proposes a delay-aware and reliable broadcast protocol（DR-BP） based on transmit power control technique. First, a comprehensive model is derived to evaluate the transmission in vehicle-to-vehicle communications. This model considers the wireless channel fading, transmission delay and retransmissions characters occurring in the physical layer/medium access control（PHY/MAC） layer. Then, a local optimal relay selection mechanism based on the above model is designed. In DR-BP scheme, only the vehicle selected as the optimal relays can forward warning messages and the transmit power is time-varying. Finally, extensive simulations verify the performance of DR-BP under different traffic scenarios. Simulation results show that DR-BP outperforms the traditional slotted 1-persistence（S1P） and flooding scheme in terms of packets delivery ratio and transmission delay.     

A 2×2 SOI mach-zehnder thermo-optical switch based on strongly guided paired multimode interference couplers

A silicon-on-insulator 2×2 Mach-Zehnder thermo-optical switch is developed based on strongly guided paired multimode interference couplers. The multimode-interference couplers were etched deeply for improving coupler characteristics such as self-imaging quality, uniformity and fabrication tolerance. The proposed switch achieves good performances, including a low insertion loss of -11 .OdB, a fiber-waveguide coupling loss of -4.3dB and a fast response speed measured to be 3.5 and 8.8 μs for raise and fall switching time, respectively.     

A 2×2 SOI mach-zehnder thermo-optical switch based on strongly guided paired multimode interference couplers

A silicon-on-insulator 2×2 Mach-Zehnder thermo-optical switch is developed based on strongly guided paired multi-mode interference couplers. The multimode-interference couplers were etched deeply for improving coupler characteristicssuch as self-imaging quality, uniformity and fabrication tolerance. The proposed switch achieves good performances,including a low insertion loss of –11.0dB, a fiber-waveguide coupling loss of –4.3dB and a fast response speed measuredto be 3.5 and 8.8 μs for raise and fall switching time, respectively.     

An A/D interface based on ΣΔ modulator for thermal vacuum sensor ASICs

A new Σ Δ modulator architecture for thermal vacuum sensor ASICs is proposed. The micro-hotplate thermal vacuum sensor fabricated by surface-micromachining technology can detect the gas pressure from 1 to 10⁵ Pa. The amplified differential output voltage signal of the sensor feeds to the Σ Δ modulator to be converted into digital domain. The presented Σ Δ modulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity. Compared with other feed-forward architectures presented before, the circuit complexity, chip area and power dissipation of the proposed architecture are significantly decreased. The correlated double sampling technique is introduced in the 1st integrator to reduce the flicker noise. The measurement results demonstrate that the modulator achieves an SNDR of 79.7 dB and a DR of 80 dB over a bandwidth of 7.8 kHz at a sampling rate of 4 MHz. The circuit has been fabricated in a 0.5 μ m 2P3M standard CMOS technology. It occupies an area of 5 mm² and dissipates 9 mW from a single 3 V power supply. The performance of the modulator meets the requirements of the considered application.     

A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS

This paper presents a 20-Gb/s automatic gain control (AGC) amplifier in a 0.18-μm SiGe BiCMOS for high-speed applications. The proposed AGC amplifier compactly consists of a folded Gilbert variable-gain amplifier (VGA), a post amplifier (PA), a 50-Ω output buffer, and AGC loop including an open-loop peak detector (PD), a RC low-pass filter (LPF), and an error amplifier (EA). The AGC amplifier achieves the broadband characteristic by utilizing inductive peaking and capacitive degeneration as well as f_T-doubler techniques to overcome the large parasitic capacitances. The proposed AGC circuits together with a linear VGA exhibits a wide gain control range of 45 dB for the received signal strength indication (RSSI). The measured AGC amplifier achieves a maximum gain of 21 dB and a -3-dB bandwidth (BW) of 20.6 GHz, which can support up to 25.4-Gb/s data rate. For the pseudorandom bit sequence (PRBS) length 2³¹–1 with a bit-error rate (BER) of 10⁻¹² at 20 Gb/s, the measured input dynamic range is 26 dB (20–400mV_pp) and the peak-to-peak data jitter is less than 8 ps. The AGC amplifier consumes a power of 160 mW from a 3.3-V supply voltage and occupies an area of 850 μm × 850 μm.     

An A/D interface based on ∑△ modulator for thermal vacuum sensor ASICs

A newΣΔmodulator architecture for thermal vacuum sensor ASICs is proposed.The micro-hotplate thermal vacuum sensor fabricated by surface-micrornachining technology can detect the gas pressure from 1 to 10~5 Pa. The amplified differential output voltage signal of the sensor feeds to theΣΔmodulator to be converted into digital domain.The presentedΣΔmodulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity.Compared with other feed-forward architectures present...     

An A/D interface based on ∑Δ modulator for thermal vacuum sensor ASICs

A new ∑Δ modulator architecture for thermal vacuum sensor ASICs is proposed.The micro-hotplate thermal vacuum sensor fabricated by surface-micromachining technology can detect the gas pressure from 1 to 105 Pa.The amplified differential output voltage signal of the sensor feeds to the ∑Δ modulator to be converted into digital domain.The presented ∑Δ modulator makes use of a feed-forward path to suppress the harmonic distortions and attain high linearity.Compared with other feed-forward architectures presented before,the circuit complexity,chip area and power dissipation of the proposed architecture are significantly decreased.The correlated double sampling technique is introduced in the 1st integrator to reduce the flicker noise.The measurement results demonstrate that the modulator achieves an SNDR of 79.7 dB and a DR of 80 dB over a bandwidth of 7.8 kHz at a sampling rate of 4 MHz.The circuit has been fabricated in a 0.5μm 2P3M standard CMOS technology.It occupies an area of 5 mm2 and dissipates9 mW from a single 3 V power supply.The performance of the modulator meets the requirements of the considered application.     

A 2× 2 SOI mach-zehnder thermo-optical switch based on strongly guided paired multimode interference couplers

A silicon-on-insulator 2× 2 Mach-Zehnder thermo-optical switch is developed based on strongly guided paired multimode interference couplers. The multimode-interference couplers were etched deeply for improving coupler characteristics such as self-imaging quality, uniformity and fabrication toierance. The proposed switch achieves good performances, including a low insertion loss of -11.0dB, a fiber-waveguide coupling loss of-4.3dB and a fast response speed measured to be 3.5 and 8.8 μs for raise and fall switching time, respectively.     

A 10 bit 50 MS/s SAR ADC with partial split capacitor switching scheme in 0.18 μm CMOS

This paper presents a 10 bit successive approximation register (SAR) analog-to-digital converter (ADC) in 0.18 μ m 1P6M CMOS technology with a 1.8 V supply voltage. To improve the conversion speed, a partial split capacitor switching scheme is proposed. By reducing the time constant of the bit cycles, the proposed technique shortens the settling time of a capacitive digital-to-analog converter (DAC). In addition, a new SAR control logic is proposed to reduce loop delay to further enhance the conversion speed. At 1.8 V supply voltage and 50 MS/s the SAR ADC achieves a signal-to-noise and distortion ratio (SNDR) of 57.5 dB and spurious-free dynamic range (SFDR) of 69.3 dB. The power consumption is 2.26 mW and the core die area is 0.096 mm².     

A 960 μW 10-bit 70-MS/s SAR ADC with an energy-efficient capacitor-switching scheme

This paper presents a low-power 10-bit 70-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) using a novel energy-efficient capacitor-switching scheme. Compared to the conventional scheme, the proposed split-capacitor V_cm-based capacitor-switching scheme can reduce the capacitor-switching energy by about 92% with better monotonicity. Meanwhile, full-custom SAR logic and registers, variable-delay self-timing cell and dynamic comparator with proposed two-segment DC offset correction scheme are also implemented to improve the conversion speed and accuracy requirements. The prototype was fabricated in 65-nm 1P9M CMOS technology. Measurement results show a peak signal-to-noise-and-distortion ratio (SNDR) of 53.2 dB, while consuming 960 μW from 1.2 V supply voltage. The figure of merit (FoM) is 36.8 fJ/conversion-step and the total active area is only 220×220 μm².     

Novel rate control scheme for intra frame video coding with exponential rate–distortion model on H.264/AVC

Rate control regulates the output bit rate of a video encoder in order to obtain optimum visual quality within the available network bandwidth and to maintain buffer fullness within a specified tolerance range. Due to the benefits of intra-only encoding, such as less computational cost and less latency, it has been more and more widely used. In this paper, we propose an accurate intra-only rate control scheme for H.264/AVC, which includes a novel complexity measurement and a new rate–distortion (R–D) model. We also propose a linear rate–complexity model which takes the intercept into consideration to reduce the estimation error. The proposed R–D model is integrated by the linear rate–complexity model and an exponential rate–quantization model. Based on theoretical analysis and experimental validation, the proposed scheme has high bits prediction precision, and it can also accurately handle buffer fullness. Compared with JVT-W042, our algorithm achieves higher average PSNR and improves the coding quality up to 0.35 dB.     

Data streams classification with ensemble model based on decision-feedback简

The main challenges of data streams classification include infinite length, concept-drifting, arrival of novel classes and lack of labeled instances. Most existing techniques address only some of them and ignore others. So an ensemble classification model based on decision-feedback（ECM-BDF） is presented in this paper to address all these challenges. Firstly, a data stream is divided into sequential chunks and a classification model is trained from each labeled data chunk. To address the infinite length and concept-drifting problem, a fixed number of such models constitute an ensemble model E and subsequent labeled chunks are used to update E. To deal with the appearance of novel classes and limited labeled instances problem, the model incorporates a novel class detection mechanism to detect the arrival of a novel class without training E with labeled instances of that class. Meanwhile, unsupervised models are trained from unlabeled instances to provide useful constraints for E. An extended ensemble model Ex can be acquired with the constraints as feedback information, and then unlabeled instances can be classified more accurately by satisfying the maximum consensus of Ex. Experimental results demonstrate that the proposed ECM-BDF outperforms traditional techniques in classifying data streams with limited labeled data.