An wide-range tunable on-chip radio-frequency LC-tank formed with a post-CMOS-compatible MEMS fabrication technique

An on-chip-micromachined tunable LC-tank, which consists of a metal inter-digitated variable capacitor and a metal solenoid inductor, is developed for wide-range radio-frequency (RF) tuning in multi-GHz band. A low-temperature metal MEMS process is developed to on-chip fabricate the passives. The process can be used for post-CMOS-compatible integration with RF ICs. Both the varactor and the inductor are suspended with a gap from the low-resistivity silicon wafer (i.e. standard CMOS wafer) for effectively depressing RF loss. The fabricated variable capacitor part, the inductor part and the whole tunable LC resonator are sequentially tested, finally resulting in a wide resonance-frequency tuning range of 72% (between about 3.5 and 6.0 GHz) under a low tuning voltage range of 0-4 V, while the Q-factor ranged within 23 and 8.     

A 0.5 V LC-VCO with improved varactor tuning technique for WSN

A 0.5 V LC-VCO implemented in 0.18 μm CMOS technology for wireless sensor network is described in this paper. An improved varactor tuning technique is proposed to decrease low frequency noise up-conversion and AM–FM phase noise of VCO, also it can increase Q of LC tank and reduce power consumption of VCO. For coarse tuning of VCO, it can increase the varactor control voltage variation range. For fine tuning of VCO, it can reduce the varactor nonlinearity. The measured tuning range is 4.58–5.26 GHz and power consumption is 2.2 mW. The measured phase noise is ?114 dBc/Hz at 1 MHz frequency offset from a 4.8 GHz carrier.     

Improvement of the Q-factor,for an adjustable inductor using a 90-μm silicon substrate on plastic

This article presents a four-port adjustable inductor with 0.18?µm Complementary Metal-Oxide-Semiconductor (CMOS) technology on plastic. The inductor has a high Q-factor and a small size for multiband UWB applications. When the four-port adjustable inductor, on VLSI-standard Si substrate, operates near 3, 4, 7.5 and 9?GHz, it has a Q-factor of 6.5, 6.7, 8 and 11.5 and an inductance of 2.1, 1.6, 1.1, 0.6?nH, respectively. Reducing the thickness of the Si substrate to 90?µm and mounting it on plastic causes a 25–31% improvement in the Q-factor, without change in the inductance, due to a reduction in the parasitic effect from the Si substrate. This is useful for multiband applications.     

Fabrication and performance of a micromachined 3-D solenoid inductor

A high-Q and f_res (self-resonant frequency)solenoid inductor was fabricated by using the microelectromechanical systems(MEMS) technology with air-core structure. This inductor has an air core and an electroplated copper coil to reduce the series resistance, and the solenoid structure with laterally laid out structure saves the chip area significantly. The measurement results show that this inductor has high Q-factor and stable inductance over wide range of operating frequency. The maximum Q-factor of this inductor is 38 and the inductance is 1.78 nH at 5 GHz with an air core of 45 μm. Moreover, the Q-factor and the inductance grow with the increasing of the air core.     

Fabrication of 3D MEMS toroidal microinductor for high temperature application

Based on Microelectromechanical systems (MEMS) technique and thick photoresist lithography technology, a new toroidal-type inductor for high temperature application has been successfully developed. In the fabrication process, heat-resistant materials are used, alumina as insulator and supporting materials instead of polyimide, heat resistant glass for underlay instead of normal glass, and copper for coil. The maximum inductance is 87 nH at 0.826 GHz and maximum of quality factor (Q-factor) is 4.63 at 0.786 GHz, at room temperature. With simulation of thermal deformation, it shows that the developed toroidal inductor can be suitable for high temperature application, from 300 to 700 °C.     

Two-port noise figure optimization of source-degenerated cascode CMOS LNAs

This paper presents a noise figure optimization technique for source-degenerated cascode CMOS LNAs with lossy gate inductors. The optimization technique, based on two-port theory, takes into account second order parasitic components. The effect of inductive source degeneration on LNA noise parameters is discussed. Measured noise figures agree well with the simulations confirming the accuracy of the noise model and allowing us to investigate the contributions of various components to the overall noise figure. A 0.18-μm CMOS LNA with an integrated inductor (Q = 7.5) achieves a noise figure of 1.16 dB and a return loss of 20 dB at 1.4 GHz, drawing 39 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 14.5 dB, input P1dB of ?17.5 dBm, and input IP3 of ?13 dBm. LNAs with external inductors having quality factor of Q = 170 and Q = 40 achieve noise figures of 0.65 dB and 0.68 dB and a return loss of 20 dB at 1.4 GHz, drawing 37 mA from a 1.8-V voltage supply, having gain (S ₂₁) of 17 dB, input P1dB of ?22 dBm, and input IP3 of ?14 dBm. The large power consumption of the presented designs was intentionally selected in order to reduce the noise figure, an acceptable trade-off for LNA’s targeted for radio telescope applications, and to assess the impact of the large currents flowing through interconnect metals on the noise figure     

A technique to improve the linearization of frequency–voltage characteristic of LC-VCO

This paper presents a very low-power linearization technique to improve the linearity of frequency-voltage characteristic of LC-VCO (voltage controlled oscillator) using MOS varactor. This reduces the VCO gain (K _VCO) variation and its required value over the tuning voltage range. Low K _VCO improves noise and reference spur performances at the output of phase lock loop/frequency synthesizer (FS). Low K _VCO variation reduces FS loop stability problem. Using this VCO circuit, a fully on-chip integer-N frequency synthesizer has been fabricated in 0.18 μm epi-digital CMOS technology for 2.45 GHz ZigBee application. The measured VCO phase noise is ?115.76 and ?125.23 dBc/Hz at 1 and 3 MHz offset frequencies, respectively from 2.445 GHz carrier and the reference spur of the frequency synthesizer is ?68.62 dBc. The used supply voltage is 1.5 V.     

Selection and modeling of integrated RF varactors on a 0.35-/spl mu/m BiCMOS technology

Integrated varactors are becoming a common feature for many RF designs and in particular RF voltage controlled oscillators (VCOs). Optimization of the quality of both the inductor and the varactor from the VCO core is essential. This work details the characterization and optimization of a number of varactor types available on a typical submicron BiCMOS process. Engineering of the bottom plate of the varactor was used to optimize the quality factor of the varactor. No additional mask layers or processing steps were required to achieve this. Integrated isolated diode varactors with quality factors of 30 at 2 GHz have been demonstrated with tuning capacitance ranges of 2.5. Integrated MOS capacitor varactors with quality factors of 50 at 2 GHz have been demonstrated with tuning capacitance range of 5. A spice model for one of the varactor types is further developed in this paper. Accurate prediction of varactor performance over voltage bias and frequency was achieved.     

非均匀金属线宽和线间距射频螺旋电感品质因子的改善

为了提高品质因子Q,本文提出了一种非均匀金属条宽和非均匀条间距的改进电感结构。从外圈到里圈,改进的电感金属线宽按等差数列逐渐减小,金属间距按等比数列增加。因为该渐变结构有效减弱了线圈中心电流拥挤导致的涡流效应,所以改进结构电感的Q因子大幅度提高（幅值高达42.86%）。为了进一步增大Q因子,新型电感同时采用图形化接地保护结构（PGS）与渐变结构。结果显示,在0.5GHz到16GHz的射频频段内,结合两种技术的新型电感的品质因子Q最优,与固定金属线宽和间距的传统电感相比,Q提高了67%;与仅采纳PGS结构的电感相比,Q提高了23%;与仅采用渐变金属结构的电感相比,Q提高了20%。     

一种Q-频率特性增强的低噪声压控有源电感

提出了一种Q-频率特性增强的低噪声压控有源电感(VCAI),电路主要由双反馈回路、前馈支路及两个电流镜共四个模块构成。其中,双反馈回路一方面用于构成回转器以实现电感特性,另一方面用于产生负阻以提高Q值,并为其配置两个调控端以实现对Q值和电感值的调节;而两个电流镜也配置了两个外部调控端,用来改变电路直流偏置以进一步对Q值和电感值进行调节;前馈支路与回转器的正跨导器相连,以改善VCAI的噪声。最终,通过四个模块相互配合以及四个调控端的协同调控,使得VCAI的Q-频率特性得到增强,即不但在同一频率下Q峰值可以相对于电感值独立调节,而且在不同频率下Q峰值可以基本保持不变,还具有低的噪声。验证结果表明,在3 GHz频率下,Q峰值可从135大范围调节到1 132,而电感值仅从43.50 nH到43.89 nH范围内微弱变化;在2 GHz、3.4 GHz和5 GHz不同频率下,Q峰值分别为682、659和635,变化率仅为6.8%;在1 GHz下,VCAI的输入参考噪声电压为3.2 nV/Hz,相比于未加入前馈支路的9.2 nV/Hz降低了6 nV/Hz。     

Low Voltage Rf Mems Capacitive Shunt Switches

Micro-electro-mechanical-systems(MEMS) switches have low resistive loss, negligible power consumption, good isolation and high power handling capability compared with semiconductor switches. Lifetime of capacitive shunt switches strongly depends on the actuation voltage so low voltage switches is necessary to enhance its performance as well as to broaden its application area. This paper presents the design and simulation of low voltage capacitive shunt MEMS switches together with its RF performance for high frequency applications. The low voltage switches are realized by lowering the spring constant of the beam using serpentine spring designs together with large capacitive area so as to achieve the good RF performance as well. The pull-in voltage is analyzed with commercial CAD finite element analysis software CoventorWare. The electromagnetic performance in terms of scattering parameters, insertion loss, and isolation are analyzed with software Ansoft HFSS10. The switches achieved insertion loss \(<\) 0.47 dB in on state from 2 to 40 GHz; it provided better than 25 dB isolation in off state with a capacitance ratio of 94–96. The actuation voltage as low as 1.5 V with actuation area \(110\,\times \,100\,\upmu \mathrm{m^2}\) along with good RF performance is reported. The design parameter optimization including selection of appropriate number of meanders and its width found to be one of the most sensitive factors affecting the spring stiffness and actuation voltage.     

Wide tuning-range CMOS VCO based on a tunable active inductor

In this paper, a wide tuning-range CMOS voltage-controlled oscillator (VCO) with high output power using an active inductor circuit is presented. In this VCO design, the coarse frequency is achieved by tuning the integrated active inductor. The circuit has been simulated using a 0.18-µm CMOS fabrication process and presents output frequency range from 100 MHz to 2.5 GHz, resulting in a tuning range of 96%. The phase noise is –85 dBc/Hz at a 1 MHz frequency offset. The output power is from –3 dBm at 2.55 GHz to +14 dBm at 167 MHz. The active inductor power dissipation is 6.5 mW and the total power consumption is 16.27 mW when operating on a 1.8 V supply voltage. By comparing this active inductor architecture VCO with general VCO topology, the result shows that this topology, which employs the proposed active inductor, produces a better performance.     

A Reconfigurable Low-Noise Amplifier Using a Tunable Active Inductor for Multistandard Receivers

A reconfigurable low-noise amplifier (LNA) based on a high-value active inductor (AI) is presented in this paper. Instead of using a passive on-chip inductor, a high-value on-chip inductor with a wide tuning range is used in this circuit and results in a decrease in the physical silicon area when compared to a passive inductor-based implementation. The LNA is a common source cascade amplifier with RC feedback. A tunable active inductor is used as the amplifier output load, and for input and output impedance matching, a source follower with an RC network is used to provide a 50 Ω impedance. The amplifier circuit has been designed in 0.18 µm CMOS process and simulated using the Cadence Spectra circuit simulator. The simulation results show a reconfigurable frequency from 0.8 to 2.5 GHz, and tuning of the frequency band is achieved by using a CMOS voltage controlled variable resistor. For a selected 1.5 GHz frequency band, simulation results show S ₂₁ (Gain) of 22 dB, S ₁₁ of ?18 dB, S ₂₂ of ?16 dB, NF of 3.02 dB, and a minimum NF (NFmin) of 1.7 dB. Power dissipation is 19.6 mW using a 1.8 V dc power supply. The total LNA physical silicon area is (200×150) µm².     

A low-cost, wide-band DCO with an on-chip 3-D solenoid inductor in 0.13 μm digital CMOS

This paper presents a wide band, fine-resolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 μm digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 μm process and the die area of the solenoid inductor is 0.013 mm². The DCO tuning range is about 52 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is ?110.17 dBc/Hz at 1 MHz offset.     

A 0.18$$\upmu$$m CMOS voltage multiplier arrangement for RF energy harvesting

This work presents a two-stage voltage multiplier (VM) useful in RF energy harvesting based applications. The proposed circuit is based on the conventional differential drive rectifier, in which the input RF signal has been level shifted using a simple arrangement. This signal is then used to drive the next stage, which has been formed by using gate cross-coupled transistors. As a result, the load driving capability of the proposed architecture increases. The load in this work has been emulated in terms of a parallel RC circuit. The architecture has been implemented using standard 0.18 \(\mu\)m CMOS technology. The measurements of the two-stage conventional VM (CVM) and proposed VM circuits were performed at ISM frequencies 13.56, 433, 915 MHz and 2.4 GHz for R\(_L\) of values 1, 5, 10, 3 and 100 K\(\Omega\) with a fixed value of C\(_L\) equal to 20 pF. The performance evaluation has been done in terms of the power conversion efficiency (PCE) and average output DC voltage. The measured results show an improvement in PCE of 5% (minimum) for 13.56, 433 and 915 MHz frequencies, and up to 2% improvement for a frequency value of 2.4 GHz at the targeted load condition of 5 K\(\Omega ||\)20 pF, when compared with the measured results of the CVM circuit.     

New CRLH-Based Planar Slotted Antennas with Helical Inductors for Wireless Communication Systems,RF-Circuits and Microwave Devices at UHF–SHF Bands

Two novel planar slotted-antennas (PSAs) are presented that exhibit good radiation characteristics at the UHF–SHF bands. The proposed antennas are constructed using metamaterial unit-cells constituted from capacitive slots etched in the radiating patch and grounded spiral shaped inductive stubs. The proposed PSA design is fabricated on a commercially available dielectric substrate, i.e. Rogers RO4003 with permittivity of 3.38 and thickness of 1.6 mm. The first PSA comprising five symmetrical unit-cells of slot–inductor–slot configuration operates over a wide bandwidth extending from 1 to 4.2 GHz with a peak gain of 1.5 dBi and efficiency of 35 % at 2 GHz. The second PSA consists of ten asymmetrical unit-cells of slot–inductor configuration on the same size of substrate as the first PSA, enhances the antenna gain by 2 dB and efficiency by 25 % and operates over 0.75–4.5 GHz. The asymmetrical unit-cell effectively increases the aperture size of the antenna without comprising its size. The electrical size of the antenna is 0.083λ₀ × 0.033λ₀ × 0.005λ₀, where free-space wavelength (λ₀) is 1 GHz.     

A wide-range 22-GHz LC-based CMOS voltage-controlled oscillator

This work presents a novel voltage-controlled oscillator (VCO) design and simulations that combine a varactor bank with a transformer in the LC tank to achieve a high-frequency range. While the varactor bank is responsible for changing the capacitance in the LC tank, the transformer acts as a means to change the value of the inductance, hence allowing tune-ability in the two main components of the VCO. A control mechanism utilises a mixed-mode circuit consisting of comparators and a state machine. It allows efficient tuning of the VCO by controlling the capacitance and transformer in the LC tank. The VCO has a 10.75–22.43 GHz frequency range and the VCO gain, K_VCO, is kept at a low value ranging from 98.6 to 175.7 MHz/V. The simulated phase noise is ?111 dBc/Hz at 1 MHz offset from the 10.75 GHz oscillation frequency. The circuit is designed and simulated in 28 nm CMOS technology and uses a 1 V supply drawing a typical power of 14.74 mW.     

Fabrication and performance of novel RF spiral inductors on silicon

This paper presents and discusses the fabrication and the performance of RF circular spiral inductors on silicon. The substrate materials underneath the inductor coil are removed by wet etching process. In the fabrication process, fine polishing of the photoresist is used to simplify the processes and ensure the seed layer and the pillars contact perfectly, and dry etching technique is used to remove the seed layer. The results show that Q-factor of the novel inductor is greatly improved by removing the silicon underneath the inductor coil. The spiral inductor for line width of 50 μm has a peak Q-factor of 17 at frequency of 1 GHz. The inductance is about 3.2 nH in the frequency range of 0.05-3 GHz and the resonance frequency of the inductors is about 6 GHz. If the strip is widened to 80 μm, the peak Q-factor of the inductor reduces to about 10 and the inductance is 1.5 nH in the same frequency range.     

High power reliability aspects on RF MEMS varactor design

A new kind of RF MEMS switched varactor for high power RF signals (P_input > 1W) has been developed on a simple and innovative design. This device is conceived to perform tuneable capacitor operations up to 10 GHz, in the 0-10W power range. The design principle is discussed in detail and measurement results validating our approach are reported. The fabricated components have undergone both lifetime reliability tests and maximum handled power tests. The measurement campaign has shown 1 billion cycle operations under 1W at 10 GHz, 250 million cycle operations under 5W at 3GHz at 2.5 kHz bipolar actuation, without any failure observed, and a maximum power handling capability up to 10W.     

Flip chip assembled MEMS inductors

High performance suspended MEMS inductors produced using a flip chip assembly approach are described. An inductor structure is fabricated on a carrier and then flip chip assembled onto a substrate to form a suspended inductor for RF-IC applications with significant improvement in Q-factor and frequency of operation over the conventional IC inductors. A spiral MEMS inductor has been successfully produced on a silicon substrate with an air gap of 26 /spl mu/m between the inductor structure and the substrate. The inductance of the device was measured to be /spl sim/2 nH and a maximum Q-factor of 19 at /spl sim/2.5 GHz was obtained after pad/connector de-embedding.